+diff --git a/configs/default b/configs/default
+index 2ca6fe4..a4069cb 100644
+--- a/configs/default
++++ b/configs/default
+@@ -10,7 +10,7 @@ CONFIG_NAME = default
+ # Version info
+ MESA_MAJOR=8
+ MESA_MINOR=0
+-MESA_TINY=0
++MESA_TINY=2
+ MESA_VERSION = $(MESA_MAJOR).$(MESA_MINOR).$(MESA_TINY)
+
+ # external projects. This should be useless now that we use libdrm.
diff --git a/docs/relnotes-8.0.2.html b/docs/relnotes-8.0.2.html
index ad1818c..d73ba9f 100644
--- a/docs/relnotes-8.0.2.html
memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
+diff --git a/src/gallium/drivers/r300/compiler/radeon_program_alu.c b/src/gallium/drivers/r300/compiler/radeon_program_alu.c
+index c48f936..b3da311 100644
+--- a/src/gallium/drivers/r300/compiler/radeon_program_alu.c
++++ b/src/gallium/drivers/r300/compiler/radeon_program_alu.c
+@@ -41,13 +41,16 @@
+
+ static struct rc_instruction *emit1(
+ struct radeon_compiler * c, struct rc_instruction * after,
+- rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
+- struct rc_src_register SrcReg)
++ rc_opcode Opcode, struct rc_sub_instruction * base,
++ struct rc_dst_register DstReg, struct rc_src_register SrcReg)
+ {
+ struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
+
++ if (base) {
++ memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
++ }
++
+ fpi->U.I.Opcode = Opcode;
+- fpi->U.I.SaturateMode = Saturate;
+ fpi->U.I.DstReg = DstReg;
+ fpi->U.I.SrcReg[0] = SrcReg;
+ return fpi;
+@@ -55,13 +58,17 @@ static struct rc_instruction *emit1(
+
+ static struct rc_instruction *emit2(
+ struct radeon_compiler * c, struct rc_instruction * after,
+- rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
++ rc_opcode Opcode, struct rc_sub_instruction * base,
++ struct rc_dst_register DstReg,
+ struct rc_src_register SrcReg0, struct rc_src_register SrcReg1)
+ {
+ struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
+
++ if (base) {
++ memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
++ }
++
+ fpi->U.I.Opcode = Opcode;
+- fpi->U.I.SaturateMode = Saturate;
+ fpi->U.I.DstReg = DstReg;
+ fpi->U.I.SrcReg[0] = SrcReg0;
+ fpi->U.I.SrcReg[1] = SrcReg1;
+@@ -70,14 +77,18 @@ static struct rc_instruction *emit2(
+
+ static struct rc_instruction *emit3(
+ struct radeon_compiler * c, struct rc_instruction * after,
+- rc_opcode Opcode, rc_saturate_mode Saturate, struct rc_dst_register DstReg,
++ rc_opcode Opcode, struct rc_sub_instruction * base,
++ struct rc_dst_register DstReg,
+ struct rc_src_register SrcReg0, struct rc_src_register SrcReg1,
+ struct rc_src_register SrcReg2)
+ {
+ struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
+
++ if (base) {
++ memcpy(&fpi->U.I, base, sizeof(struct rc_sub_instruction));
++ }
++
+ fpi->U.I.Opcode = Opcode;
+- fpi->U.I.SaturateMode = Saturate;
+ fpi->U.I.DstReg = DstReg;
+ fpi->U.I.SrcReg[0] = SrcReg0;
+ fpi->U.I.SrcReg[1] = SrcReg1;
+@@ -221,7 +232,7 @@ static void transform_ABS(struct radeon_compiler* c,
+ struct rc_src_register src = inst->U.I.SrcReg[0];
+ src.Abs = 1;
+ src.Negate = RC_MASK_NONE;
+- emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, src);
++ emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I, inst->U.I.DstReg, src);
+ rc_remove_instruction(inst);
+ }
+
+@@ -240,7 +251,7 @@ static void transform_CEIL(struct radeon_compiler* c,
+
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+ emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, negate(inst->U.I.SrcReg[0]));
+- emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
+ inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index));
+ rc_remove_instruction(inst);
+ }
+@@ -256,7 +267,7 @@ static void transform_CLAMP(struct radeon_compiler *c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+ emit2(c, inst->Prev, RC_OPCODE_MIN, 0, dst,
+ inst->U.I.SrcReg[0], inst->U.I.SrcReg[2]);
+- emit2(c, inst->Prev, RC_OPCODE_MAX, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit2(c, inst->Prev, RC_OPCODE_MAX, &inst->U.I, inst->U.I.DstReg,
+ srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1]);
+ rc_remove_instruction(inst);
+ }
+@@ -272,7 +283,7 @@ static void transform_DP2(struct radeon_compiler* c,
+ src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
+ src1.Swizzle &= ~(63 << (3 * 2));
+ src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
+- emit2(c, inst->Prev, RC_OPCODE_DP3, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
++ emit2(c, inst->Prev, RC_OPCODE_DP3, &inst->U.I, inst->U.I.DstReg, src0, src1);
+ rc_remove_instruction(inst);
+ }
+
+@@ -283,7 +294,7 @@ static void transform_DPH(struct radeon_compiler* c,
+ src0.Negate &= ~RC_MASK_W;
+ src0.Swizzle &= ~(7 << (3 * 3));
+ src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
+- emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
++ emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
+ rc_remove_instruction(inst);
+ }
+
+@@ -294,7 +305,7 @@ static void transform_DPH(struct radeon_compiler* c,
+ static void transform_DST(struct radeon_compiler* c,
+ struct rc_instruction* inst)
+ {
+- emit2(c, inst->Prev, RC_OPCODE_MUL, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit2(c, inst->Prev, RC_OPCODE_MUL, &inst->U.I, inst->U.I.DstReg,
+ swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
+ swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
+ rc_remove_instruction(inst);
+@@ -305,7 +316,7 @@ static void transform_FLR(struct radeon_compiler* c,
+ {
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+ emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, inst->U.I.SrcReg[0]);
+- emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit2(c, inst->Prev, RC_OPCODE_ADD, &inst->U.I, inst->U.I.DstReg,
+ inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
+ rc_remove_instruction(inst);
+ }
+@@ -379,14 +390,14 @@ static void transform_LIT(struct radeon_compiler* c,
+ swizzle_wwww(srctemp));
+
+ /* tmp.z = (tmp.x > 0) ? tmp.w : 0.0 */
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I,
+ dstregtmpmask(temp, RC_MASK_Z),
+ negate(swizzle_xxxx(srctemp)),
+ swizzle_wwww(srctemp),
+ builtin_zero);
+
+ /* tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0 */
+- emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode,
++ emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I,
+ dstregtmpmask(temp, RC_MASK_XYW),
+ swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
+
+@@ -401,7 +412,7 @@ static void transform_LRP(struct radeon_compiler* c,
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
+ dst,
+ inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
+- emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
++ emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I,
+ inst->U.I.DstReg,
+ inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[2]);
+
+@@ -418,7 +429,7 @@ static void transform_POW(struct radeon_compiler* c,
+
+ emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, swizzle_xxxx(inst->U.I.SrcReg[0]));
+ emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, swizzle_xxxx(inst->U.I.SrcReg[1]));
+- emit1(c, inst->Prev, RC_OPCODE_EX2, inst->U.I.SaturateMode, inst->U.I.DstReg, tempsrc);
++ emit1(c, inst->Prev, RC_OPCODE_EX2, &inst->U.I, inst->U.I.DstReg, tempsrc);
+
+ rc_remove_instruction(inst);
+ }
+@@ -472,7 +483,7 @@ static void transform_SEQ(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_zero, builtin_one);
+
+ rc_remove_instruction(inst);
+@@ -481,7 +492,7 @@ static void transform_SEQ(struct radeon_compiler* c,
+ static void transform_SFL(struct radeon_compiler* c,
+ struct rc_instruction* inst)
+ {
+- emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, builtin_zero);
++ emit1(c, inst->Prev, RC_OPCODE_MOV, &inst->U.I, inst->U.I.DstReg, builtin_zero);
+ rc_remove_instruction(inst);
+ }
+
+@@ -491,7 +502,7 @@ static void transform_SGE(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
+
+ rc_remove_instruction(inst);
+@@ -503,7 +514,7 @@ static void transform_SGT(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
+
+ rc_remove_instruction(inst);
+@@ -515,7 +526,7 @@ static void transform_SLE(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
+
+ rc_remove_instruction(inst);
+@@ -527,7 +538,7 @@ static void transform_SLT(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
+
+ rc_remove_instruction(inst);
+@@ -539,7 +550,7 @@ static void transform_SNE(struct radeon_compiler* c,
+ struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+
+ emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+- emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_CMP, &inst->U.I, inst->U.I.DstReg,
+ negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_one, builtin_zero);
+
+ rc_remove_instruction(inst);
+@@ -604,7 +615,7 @@ static void transform_XPD(struct radeon_compiler* c,
+ emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dst,
+ swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
+ swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
+- emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit3(c, inst->Prev, RC_OPCODE_MAD, &inst->U.I, inst->U.I.DstReg,
+ swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
+ swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
+ negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
+@@ -719,7 +730,7 @@ static void transform_r300_vertex_DP3(struct radeon_compiler* c,
+ src1.Negate &= ~RC_MASK_W;
+ src1.Swizzle &= ~(7 << (3 * 3));
+ src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
+- emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
++ emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, src1);
+ rc_remove_instruction(inst);
+ }
+
+@@ -1043,22 +1054,22 @@ static void r300_transform_SIN_COS_SCS(struct radeon_compiler *c,
+ unsigned srctmp)
+ {
+ if (inst->U.I.Opcode == RC_OPCODE_COS) {
+- emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, inst->U.I.DstReg,
++ emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, inst->U.I.DstReg,
+ srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
+ } else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
+- emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode,
++ emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I,
+ inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
+ } else if (inst->U.I.Opcode == RC_OPCODE_SCS) {
+ struct rc_dst_register moddst = inst->U.I.DstReg;
+
+ if (inst->U.I.DstReg.WriteMask & RC_MASK_X) {
+ moddst.WriteMask = RC_MASK_X;
+- emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, moddst,
++ emit1(c, inst->Prev, RC_OPCODE_COS, &inst->U.I, moddst,
+ srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
+ }
+ if (inst->U.I.DstReg.WriteMask & RC_MASK_Y) {
+ moddst.WriteMask = RC_MASK_Y;
+- emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode, moddst,
++ emit1(c, inst->Prev, RC_OPCODE_SIN, &inst->U.I, moddst,
+ srcregswz(RC_FILE_TEMPORARY, srctmp, RC_SWIZZLE_WWWW));
+ }
+ }
diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c
index d132638..920612b 100644
--- a/src/gallium/drivers/r300/r300_blit.c
struct util_slab_mempool pool_transfers;
+diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
+index 3897e99..e4afe78 100644
+--- a/src/gallium/drivers/r300/r300_emit.c
++++ b/src/gallium/drivers/r300/r300_emit.c
+@@ -1030,20 +1030,18 @@ void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
+ R300_PVS_VF_MAX_VTX_NUM(12) |
+ (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
+
+- /* Emit flow control instructions. */
+- if (code->num_fc_ops) {
+-
+- OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
+- if (r300screen->caps.is_r500) {
+- OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
+- OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
+- } else {
+- OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
+- OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
+- }
+- OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
+- OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
++ /* Emit flow control instructions. Even if there are no fc instructions,
++ * we still need to write the registers to make sure they are cleared. */
++ OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
++ if (r300screen->caps.is_r500) {
++ OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
++ OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
++ } else {
++ OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
++ OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
+ }
++ OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
++ OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
+
+ END_CS;
+ }
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index 83cad42..1542648 100644
--- a/src/gallium/drivers/r300/r300_render.c
default:;
}
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
-index 2bc7036..c43352a 100644
+index 2bc7036..8a656e6 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1048,6 +1048,10 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
}
return vs;
+@@ -1794,9 +1802,8 @@ static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
+ if (r300->screen->caps.has_tcl) {
+ unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2;
+ r300_mark_atom_dirty(r300, &r300->vs_state);
+- r300->vs_state.size =
+- vs->code.length + 9 +
+- (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0);
++ r300->vs_state.size = vs->code.length + 9 +
++ (R300_VS_MAX_FC_OPS * fc_op_dwords + 4);
+
+ r300_mark_atom_dirty(r300, &r300->vs_constants);
+ r300->vs_constants.size =
diff --git a/src/gallium/drivers/r300/r300_vs.c b/src/gallium/drivers/r300/r300_vs.c
index 1eef071..4faf2b5 100644
--- a/src/gallium/drivers/r300/r300_vs.c
int nr = base_mrf;
int reg_width = c->dispatch_width / 8;
+diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
+index 7a1b91f..8bf1d3d 100644
+--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
++++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
+@@ -115,6 +115,8 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
+ intel_miptree_set_image_offset(mt, level, q, x, y);
+ x += pack_x_pitch;
+ }
++ if (x > mt->total_width)
++ mt->total_width = x;
+
+ x = 0;
+ y += pack_y_pitch;
+@@ -135,10 +137,9 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
+ pack_x_nr <<= 1;
+ }
+ } else {
++ pack_x_nr <<= 1;
+ if (pack_x_pitch > 4) {
+ pack_x_pitch >>= 1;
+- pack_x_nr <<= 1;
+- assert(pack_x_pitch * pack_x_nr <= mt->total_width);
+ }
+
+ if (pack_y_pitch > 2) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 51d3a46..97ae489 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
intel_miptree_copy_teximage(intel, intelImage, intelObj->mt);
}
}
+diff --git a/src/mesa/drivers/windows/gdi/wmesa.c b/src/mesa/drivers/windows/gdi/wmesa.c
+index 40aa56e..93da05f 100644
+--- a/src/mesa/drivers/windows/gdi/wmesa.c
++++ b/src/mesa/drivers/windows/gdi/wmesa.c
+@@ -243,39 +243,9 @@ static void wmesa_flush(struct gl_context *ctx)
+ /***** CLEAR Functions *****/
+ /**********************************************************************/
+
+-/* If we do not implement these, Mesa clears the buffers via the pixel
+- * span writing interface, which is very slow for a clear operation.
+- */
+-
+-/*
+- * Set the color used to clear the color buffer.
+- */
+-static void clear_color(struct gl_context *ctx,
+- const union gl_color_union color)
+-{
+- WMesaContext pwc = wmesa_context(ctx);
+- GLubyte col[3];
+-
+- UNCLAMPED_FLOAT_TO_UBYTE(col[0], color.f[0]);
+- UNCLAMPED_FLOAT_TO_UBYTE(col[1], color.f[1]);
+- UNCLAMPED_FLOAT_TO_UBYTE(col[2], color.f[2]);
+- pwc->clearColorRef = RGB(col[0], col[1], col[2]);
+- DeleteObject(pwc->clearPen);
+- DeleteObject(pwc->clearBrush);
+- pwc->clearPen = CreatePen(PS_SOLID, 1, pwc->clearColorRef);
+- pwc->clearBrush = CreateSolidBrush(pwc->clearColorRef);
+-}
+-
+-
+ /*
+- * Clear the specified region of the color buffer using the clear color
+- * or index as specified by one of the two functions above.
+- *
+- * This procedure clears either the front and/or the back COLOR buffers.
+- * Only the "left" buffer is cleared since we are not stereo.
+- * Clearing of the other non-color buffers is left to the swrast.
++ * Clear the color/depth/stencil buffers.
+ */
+-
+ static void clear(struct gl_context *ctx, GLbitfield mask)
+ {
+ #define FLIP(Y) (ctx->DrawBuffer->Height - (Y) - 1)
+@@ -298,6 +268,20 @@ static void clear(struct gl_context *ctx, GLbitfield mask)
+ return;
+ }
+
++ if (mask & BUFFER_BITS_COLOR) {
++ /* setup the clearing color */
++ const union gl_color_union color = ctx->Color.ClearColor;
++ GLubyte col[3];
++ UNCLAMPED_FLOAT_TO_UBYTE(col[0], color.f[0]);
++ UNCLAMPED_FLOAT_TO_UBYTE(col[1], color.f[1]);
++ UNCLAMPED_FLOAT_TO_UBYTE(col[2], color.f[2]);
++ pwc->clearColorRef = RGB(col[0], col[1], col[2]);
++ DeleteObject(pwc->clearPen);
++ DeleteObject(pwc->clearBrush);
++ pwc->clearPen = CreatePen(PS_SOLID, 1, pwc->clearColorRef);
++ pwc->clearBrush = CreateSolidBrush(pwc->clearColorRef);
++ }
++
+ /* Back buffer */
+ if (mask & BUFFER_BIT_BACK_LEFT) {
+
+@@ -940,54 +924,6 @@ wmesa_renderbuffer_storage(struct gl_context *ctx,
+
+
+ /**
+- * Plug in the Get/PutRow/Values functions for a renderbuffer depending
+- * on if we're drawing to the front or back color buffer.
+- */
+-static void
+-wmesa_set_renderbuffer_funcs(struct gl_renderbuffer *rb, int pixelformat,
+- int cColorBits, int double_buffer)
+-{
+- if (double_buffer) {
+- /* back buffer */
+- /* Picking the correct span functions is important because
+- * the DIB was allocated with the indicated depth. */
+- switch(pixelformat) {
+- case PF_5R6G5B:
+- rb->PutRow = write_rgba_span_16;
+- rb->PutValues = write_rgba_pixels_16;
+- rb->GetRow = read_rgba_span_16;
+- rb->GetValues = read_rgba_pixels_16;
+- break;
+- case PF_8R8G8B:
+- if (cColorBits == 24)
+- {
+- rb->PutRow = write_rgba_span_24;
+- rb->PutValues = write_rgba_pixels_24;
+- rb->GetRow = read_rgba_span_24;
+- rb->GetValues = read_rgba_pixels_24;
+- }
+- else
+- {
+- rb->PutRow = write_rgba_span_32;
+- rb->PutValues = write_rgba_pixels_32;
+- rb->GetRow = read_rgba_span_32;
+- rb->GetValues = read_rgba_pixels_32;
+- }
+- break;
+- default:
+- break;
+- }
+- }
+- else {
+- /* front buffer (actual Windows window) */
+- rb->PutRow = write_rgba_span_front;
+- rb->PutValues = write_rgba_pixels_front;
+- rb->GetRow = read_rgba_span_front;
+- rb->GetValues = read_rgba_pixels_front;
+- }
+-}
+-
+-/**
+ * Called by ctx->Driver.ResizeBuffers()
+ * Resize the front/back colorbuffers to match the latest window size.
+ */
+@@ -1143,7 +1079,6 @@ WMesaContext WMesaCreateContext(HDC hDC,
+ functions.GetBufferSize = wmesa_get_buffer_size;
+ functions.Flush = wmesa_flush;
+ functions.Clear = clear;
+- functions.ClearColor = clear_color;
+ functions.ResizeBuffers = wmesa_resize_buffers;
+ functions.Viewport = wmesa_viewport;
+
+@@ -1275,11 +1210,9 @@ void WMesaMakeCurrent(WMesaContext c, HDC hdc)
+ if (visual->doubleBufferMode == 1) {
+ rb = wmesa_new_renderbuffer();
+ _mesa_add_renderbuffer(&pwfb->Base, BUFFER_BACK_LEFT, rb);
+- wmesa_set_renderbuffer_funcs(rb, pwfb->pixelformat, pwfb->cColorBits, 1);
+ }
+ rb = wmesa_new_renderbuffer();
+ _mesa_add_renderbuffer(&pwfb->Base, BUFFER_FRONT_LEFT, rb);
+- wmesa_set_renderbuffer_funcs(rb, pwfb->pixelformat, pwfb->cColorBits, 0);
+
+ /* Let Mesa own the Depth, Stencil, and Accum buffers */
+ _swrast_add_soft_renderbuffers(&pwfb->Base,
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 5b3c246..f3a0d10 100644
--- a/src/mesa/main/readpix.c
projects / packages / Mesa.git / commitdiff