]> git.pld-linux.org Git - packages/crossavr-libc.git/blame - 999-avr-libc-new-headers.patch
projects / packages / crossavr-libc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
- synchronized patches with official AVR toolchain 3.4.1.830
[packages/crossavr-libc.git] / 999-avr-libc-new-headers.patch
CommitLineData
9fe267c2
PZ		 1diff -urN avr-libc-1.8.0.orig/include/avr/builtins.h avr-libc-1.8.0/include/avr/builtins.h
2--- avr-libc-1.8.0.orig/include/avr/builtins.h 2013-01-18 09:49:50.000000000 +0100
3+++ avr-libc-1.8.0/include/avr/builtins.h 2013-01-18 09:50:25.000000000 +0100
4@@ -1,4 +1,5 @@
5-/* Copyright (c) 2008 Anatoly Sokolv
6+/* Copyright (c) 2008 Anatoly Sokolov
7+ Copyright (c) 2010 Joerg Wunsch
8 All rights reserved.
9
10 Redistribution and use in source and binary forms, with or without
11@@ -28,74 +29,85 @@
12 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
13 POSSIBILITY OF SUCH DAMAGE. */
14
15-/* $Id$ */
16+/* $Id: builtins.h.in 2103 2010-03-17 05:16:10Z joerg_wunsch $ */
17
18 /*
19- avr/builtins.h -
20+ avr/builtins.h - Intrinsic functions built into the compiler
21 */
22
23 #ifndef _AVR_BUILTINS_H_
24 #define _AVR_BUILTINS_H_
25
26+#ifndef __HAS_DELAY_CYCLES
27+#define __HAS_DELAY_CYCLES 1
28+#endif
29+
30 /** \file */
31 /** \defgroup avr_builtins <avr/builtins.h>: GCC builtins
32 \code #include <avr/builtins.h> \endcode
33
34- This header file declares avr builtins. */
35+ This header file declares AVR builtins.
36+ All the functions documented here are built into the
37+ compiler, and cause it to emit the corresponding assembly
38+ code instructions.
39+*/
40
41-/**
42+/**
43 \ingroup avr_builtins
44
45 Enables interrupts by setting the global interrupt mask. */
46 extern void __builtin_avr_sei(void);
47
48-/**
49+/**
50 \ingroup avr_builtins
51
52 Disables all interrupts by clearing the global interrupt mask. */
53 extern void __builtin_avr_cli(void);
54
55-/**
56+/**
57 \ingroup avr_builtins
58
59- TODO. */
60+ Emits a \c SLEEP instruction. */
61
62 extern void __builtin_avr_sleep(void);
63
64-/**
65+/**
66 \ingroup avr_builtins
67
68- TODO. */
69+ Emits a WDR (watchdog reset) instruction. */
70 extern void __builtin_avr_wdr(void);
71
72-/**
73+/**
74 \ingroup avr_builtins
75
76- TODO. */
77+ Emits a SWAP (nibble swap) instruction on __b. */
78 extern unsigned char __builtin_avr_swap(unsigned char __b);
79
80-/**
81+/**
82 \ingroup avr_builtins
83
84- TODO. */
85+ Emits an FMUL (fractional multiply unsigned) instruction. */
86 extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b);
87
88-/**
89+/**
90 \ingroup avr_builtins
91
92- TODO. */
93+ Emits an FMUL (fractional multiply signed) instruction. */
94 extern int __builtin_avr_fmuls(char __a, char __b);
95
96-/**
97+/**
98 \ingroup avr_builtins
99
100- TODO. */
101+ Emits an FMUL (fractional multiply signed with unsigned) instruction. */
102 extern int __builtin_avr_fmulsu(char __a, unsigned char __b);
103
104-/**
105+#if __HAS_DELAY_CYCLES || defined(__DOXYGEN__)
106+/**
107 \ingroup avr_builtins
108
109- TODO. */
110+ Emits a sequence of instructions causing the CPU to spend
111+ \c __n cycles on it. */
112 extern void __builtin_avr_delay_cycles(unsigned long __n);
113+#endif
114
115-#endif /* _AVR_BUILTINS_H_ */
116\ Brak znaku nowej linii na końcu pliku
117+#endif /* _AVR_BUILTINS_H_ */
118diff -urN avr-libc-1.8.0.orig/include/avr/eeprom.h avr-libc-1.8.0/include/avr/eeprom.h
119--- avr-libc-1.8.0.orig/include/avr/eeprom.h 2013-01-18 09:49:50.000000000 +0100
120+++ avr-libc-1.8.0/include/avr/eeprom.h 2013-01-18 09:50:25.000000000 +0100
121@@ -107,9 +107,13 @@
122 # define _EEPROM_SUFFIX _m1284p
123 #elif defined (__AVR_ATmega128RFA1__)
124 # define _EEPROM_SUFFIX _m128rfa1
125+#elif defined (__AVR_ATmega128RFA2__)
126+# define _EEPROM_SUFFIX _m128rfa2
127 #elif defined (__AVR_ATmega128RFR2__)
128 # define _EEPROM_SUFFIX _m128rfr2
129 #elif defined (__AVR_ATmega256RFA2__)
130+# define _EEPROM_SUFFIX _m256rfa2
131+#elif defined (__AVR_ATmega256RFR2__)
132 # define _EEPROM_SUFFIX _m256rfr2
133 #elif defined (__AVR_ATmega2560__)
134 # define _EEPROM_SUFFIX _m2560
135@@ -133,6 +137,8 @@
136 # define _EEPROM_SUFFIX _usb1286
137 #elif defined (__AVR_AT90USB1287__)
138 # define _EEPROM_SUFFIX _usb1287
139+#elif defined (__AVR_ATmega64RFA2__)
140+# define _EEPROM_SUFFIX _m64rfa2
141 #elif defined (__AVR_ATmega64RFR2__)
142 # define _EEPROM_SUFFIX _m64rfr2
143 #elif defined (__AVR_ATmega64__)
144@@ -281,6 +287,8 @@
145 # define _EEPROM_SUFFIX _m16hvb
146 #elif defined (__AVR_ATmega16HVBREVB__)
147 # define _EEPROM_SUFFIX _m16hvbrevb
148+#elif defined (__AVR_ATmega26HVG__)
149+# define _EEPROM_SUFFIX _m26hvg
150 #elif defined (__AVR_ATmega8__)
151 # define _EEPROM_SUFFIX _m8
152 #elif defined (__AVR_ATmega8A__)
153@@ -289,6 +297,8 @@
154 # define _EEPROM_SUFFIX _m48
155 #elif defined (__AVR_ATmega48A__)
156 # define _EEPROM_SUFFIX _m48a
157+#elif defined (__AVR_ATmega48HVF__)
158+# define _EEPROM_SUFFIX _m48hvf
159 #elif defined (__AVR_ATmega48PA__)
160 # define _EEPROM_SUFFIX _m48pa
161 #elif defined (__AVR_ATmega48P__)
162@@ -357,6 +367,8 @@
163 # define _EEPROM_SUFFIX _tn84
164 #elif defined (__AVR_ATtiny84A__)
165 # define _EEPROM_SUFFIX _tn84a
166+#elif defined (__AVR_ATtiny841__)
167+# define _EEPROM_SUFFIX _tn841
168 #elif defined (__AVR_ATtiny261__)
169 # define _EEPROM_SUFFIX _tn261
170 #elif defined (__AVR_ATtiny261A__)
171@@ -401,12 +413,10 @@
172 # define _EEPROM_SUFFIX _x32c4
173 #elif defined (__AVR_ATxmega32D4__)
174 # define _EEPROM_SUFFIX _x32d4
175-#elif defined (__AVR_ATxmega8E5__)
176-#define _EEPROM_SUFFIX _x8e5
177-#elif defined (__AVR_ATxmega16E5__)
178-#define _EEPROM_SUFFIX _x16e5
179 #elif defined (__AVR_ATxmega32E5__)
180 # define _EEPROM_SUFFIX _x32e5
181+#elif defined (__AVR_ATxmega32X1__)
182+# define _EEPROM_SUFFIX _x32x1
183 #elif defined (__AVR_ATxmega64A1__)
184 # define _EEPROM_SUFFIX _x64a1
185 #elif defined (__AVR_ATxmega64A1U__)
186@@ -483,8 +493,12 @@
187 # define _EEPROM_SUFFIX _a6289
188 #elif defined (__AVR_ATA5790__)
189 # define _EEPROM_SUFFIX _a5790
190+#elif defined (__AVR_ATA5790N__)
191+# define _EEPROM_SUFFIX _a5790n
192 #elif defined (__AVR_ATA5795__)
193 # define _EEPROM_SUFFIX _a5795
194+#elif defined (__AVR_ATA5831__)
195+# define _EEPROM_SUFFIX _a5831
196 /* avr1: the following only supported for assembler programs */
197 #elif defined (__AVR_ATtiny28__)
198 # define _EEPROM_SUFFIX _tn28
199diff -urN avr-libc-1.8.0.orig/include/avr/io90pwm161.h avr-libc-1.8.0/include/avr/io90pwm161.h
200--- avr-libc-1.8.0.orig/include/avr/io90pwm161.h 1970-01-01 01:00:00.000000000 +0100
201+++ avr-libc-1.8.0/include/avr/io90pwm161.h 2013-01-18 09:50:25.000000000 +0100
202@@ -0,0 +1,865 @@
203+/*****************************************************************************
204+ *
205+ * Copyright (C) 2012 Atmel Corporation
206+ * All rights reserved.
207+ *
208+ * Redistribution and use in source and binary forms, with or without
209+ * modification, are permitted provided that the following conditions are met:
210+ *
211+ * * Redistributions of source code must retain the above copyright
212+ * notice, this list of conditions and the following disclaimer.
213+ *
214+ * * Redistributions in binary form must reproduce the above copyright
215+ * notice, this list of conditions and the following disclaimer in
216+ * the documentation and/or other materials provided with the
217+ * distribution.
218+ *
219+ * * Neither the name of the copyright holders nor the names of
220+ * contributors may be used to endorse or promote products derived
221+ * from this software without specific prior written permission.
222+ *
223+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
224+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
225+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
226+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
227+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
228+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
229+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
230+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
231+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
232+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
233+ * POSSIBILITY OF SUCH DAMAGE.
234+ ****************************************************************************/
235+
236+
237+#ifndef _AVR_AT90PWM161_H_INCLUDED
238+#define _AVR_AT90PWM161_H_INCLUDED
239+
240+
241+#ifndef _AVR_IO_H_
242+# error "Include <avr/io.h> instead of this file."
243+#endif
244+
245+#ifndef _AVR_IOXXX_H_
246+# define _AVR_IOXXX_H_ "io90pwm161.h"
247+#else
248+# error "Attempt to include more than one <avr/ioXXX.h> file."
249+#endif
250+
251+/* Registers and associated bit numbers */
252+
253+#define ACSR _SFR_IO8(0x00)
254+#define AC1O 1
255+#define AC2O 2
256+#define AC3O 3
257+#define AC1IF 5
258+#define AC2IF 6
259+#define AC3IF 7
260+
261+#define TIMSK1 _SFR_IO8(0x01)
262+#define TOIE1 0
263+#define ICIE1 5
264+
265+#define TIFR1 _SFR_IO8(0x02)
266+#define TOV1 0
267+#define ICF1 5
268+
269+#define PINB _SFR_IO8(0x03)
270+#define PINB7 7
271+#define PINB6 6
272+#define PINB5 5
273+#define PINB4 4
274+#define PINB3 3
275+#define PINB2 2
276+#define PINB1 1
277+#define PINB0 0
278+
279+#define DDRB _SFR_IO8(0x04)
280+#define DDRB7 7
281+#define DDRB6 6
282+#define DDRB5 5
283+#define DDRB4 4
284+#define DDRB3 3
285+#define DDRB2 2
286+#define DDRB1 1
287+#define DDRB0 0
288+
289+#define PORTB _SFR_IO8(0x05)
290+#define PORTB7 7
291+#define PORTB6 6
292+#define PORTB5 5
293+#define PORTB4 4
294+#define PORTB3 3
295+#define PORTB2 2
296+#define PORTB1 1
297+#define PORTB0 0
298+
299+#define ADCSRA _SFR_IO8(0x06)
300+#define ADPS0 0
301+#define ADPS1 1
302+#define ADPS2 2
303+#define ADIE 3
304+#define ADIF 4
305+#define ADATE 5
306+#define ADSC 6
307+#define ADEN 7
308+
309+#define ADCSRB _SFR_IO8(0x07)
310+#define ADTS0 0
311+#define ADTS1 1
312+#define ADTS2 2
313+#define ADTS3 3
314+#define ADSSEN 4
315+#define ADNCDIS 6
316+#define ADHSM 7
317+
318+#define ADMUX _SFR_IO8(0x08)
319+#define MUX0 0
320+#define MUX1 1
321+#define MUX2 2
322+#define MUX3 3
323+#define ADLAR 5
324+#define REFS0 6
325+#define REFS1 7
326+
327+#define PIND _SFR_IO8(0x09)
328+#define PIND7 7
329+#define PIND6 6
330+#define PIND5 5
331+#define PIND4 4
332+#define PIND3 3
333+#define PIND2 2
334+#define PIND1 1
335+#define PIND0 0
336+
337+#define DDRD _SFR_IO8(0x0A)
338+#define DDRD7 7
339+#define DDRD6 6
340+#define DDRD5 5
341+#define DDRD4 4
342+#define DDRD3 3
343+#define DDRD2 2
344+#define DDRD1 1
345+#define DDRD0 0
346+
347+#define PORTD _SFR_IO8(0x0B)
348+#define PORTD7 7
349+#define PORTD6 6
350+#define PORTD5 5
351+#define PORTD4 4
352+#define PORTD3 3
353+#define PORTD2 2
354+#define PORTD1 1
355+#define PORTD0 0
356+
357+#define PINE _SFR_IO8(0x0C)
358+#define PINE7 7
359+#define PINE6 6
360+#define PINE5 5
361+#define PINE4 4
362+#define PINE3 3
363+#define PINE2 2
364+#define PINE1 1
365+#define PINE0 0
366+
367+#define DDRE _SFR_IO8(0x0D)
368+#define DDRE7 7
369+#define DDRE6 6
370+#define DDRE5 5
371+#define DDRE4 4
372+#define DDRE3 3
373+#define DDRE2 2
374+#define DDRE1 1
375+#define DDRE0 0
376+
377+#define PORTE _SFR_IO8(0x0E)
378+#define PORTE7 7
379+#define PORTE6 6
380+#define PORTE5 5
381+#define PORTE4 4
382+#define PORTE3 3
383+#define PORTE2 2
384+#define PORTE1 1
385+#define PORTE0 0
386+
387+#define PIM0 _SFR_IO8(0x0F)
388+#define PEOPE0 0
389+#define PEOEPE0 1
390+#define PEVE0A 3
391+#define PEVE0B 4
392+
393+#define PIFR0 _SFR_IO8(0x10)
394+#define PEOP0 0
395+#define PRN00 1
396+#define PRN01 2
397+#define PEV0A 3
398+#define PEV0B 4
399+#define POAC0A 6
400+#define POAC0B 7
401+
402+#define PCNF0 _SFR_IO8(0x11)
403+#define PCLKSEL0 1
404+#define POP0 2
405+#define PMODE00 3
406+#define PMODE01 4
407+#define PLOCK0 5
408+#define PALOCK0 6
409+#define PFIFTY0 7
410+
411+#define PCTL0 _SFR_IO8(0x12)
412+#define PRUN0 0
413+#define PCCYC0 1
414+#define PAOC0A 3
415+#define PAOC0B 4
416+#define PBFM00 2
417+#define PBFM01 5
418+#define PPRE00 6
419+#define PPRE01 7
420+
421+#define PIM2 _SFR_IO8(0x13)
422+#define PEOPE2 0
423+#define PEOEPE2 1
424+#define PEVE2A 3
425+#define PEVE2B 4
426+#define PSEIE2 5
427+
428+#define PIFR2 _SFR_IO8(0x14)
429+#define PEOP2 0
430+#define PRN20 1
431+#define PRN21 2
432+#define PEV2A 3
433+#define PEV2B 4
434+#define PSEI2 5
435+#define POAC2A 6
436+#define POAC2B 7
437+
438+#define PCNF2 _SFR_IO8(0x15)
439+#define POME2 0
440+#define PCLKSEL2 1
441+#define POP2 2
442+#define PMODE20 3
443+#define PMODE21 4
444+#define PLOCK2 5
445+#define PALOCK2 6
446+#define PFIFTY2 7
447+
448+#define PCTL2 _SFR_IO8(0x16)
449+#define PRUN2 0
450+#define PCCYC2 1
451+#define PARUN2 2
452+#define PAOC2A 3
453+#define PAOC2B 4
454+#define PBFM2 5
455+#define PPRE20 6
456+#define PPRE21 7
457+
458+#define SPCR _SFR_IO8(0x17)
459+#define SPR0 0
460+#define SPR1 1
461+#define CPHA 2
462+#define CPOL 3
463+#define MSTR 4
464+#define DORD 5
465+#define SPE 6
466+#define SPIE 7
467+
468+#define SPSR _SFR_IO8(0x18)
469+#define SPI2X 0
470+#define WCOL 6
471+#define SPIF 7
472+
473+#define GPIOR0 _SFR_IO8(0x19)
474+#define GPIOR00 0
475+#define GPIOR01 1
476+#define GPIOR02 2
477+#define GPIOR03 3
478+#define GPIOR04 4
479+#define GPIOR05 5
480+#define GPIOR06 6
481+#define GPIOR07 7
482+
483+#define GPIOR1 _SFR_IO8(0x1A)
484+#define GPIOR10 0
485+#define GPIOR11 1
486+#define GPIOR12 2
487+#define GPIOR13 3
488+#define GPIOR14 4
489+#define GPIOR15 5
490+#define GPIOR16 6
491+#define GPIOR17 7
492+
493+#define GPIOR2 _SFR_IO8(0x1B)
494+#define GPIOR20 0
495+#define GPIOR21 1
496+#define GPIOR22 2
497+#define GPIOR23 3
498+#define GPIOR24 4
499+#define GPIOR25 5
500+#define GPIOR26 6
501+#define GPIOR27 7
502+
503+#define EECR _SFR_IO8(0x1C)
504+#define EERE 0
505+#define EEWE 1
506+#define EEMWE 2
507+#define EERIE 3
508+#define EEPM0 4
509+#define EEPM1 5
510+#define EEPAGE 6
511+#define NVMBSY 7
512+
513+#define EEDR _SFR_IO8(0x1D)
514+
515+/* Combine EEARL and EEARH */
516+#define EEAR _SFR_IO16(0x1E)
517+
518+#define EEARL _SFR_IO8(0x1E)
519+#define EEARH _SFR_IO8(0x1F)
520+
521+#define EIFR _SFR_IO8(0x20)
522+#define INTF0 0
523+#define INTF1 1
524+#define INTF2 2
525+
526+#define EIMSK _SFR_IO8(0x21)
527+#define INT0 0
528+#define INT1 1
529+#define INT2 2
530+
531+/* Combine OCR0SBL and OCR0SBH */
532+#define OCR0SB _SFR_IO16(0x22)
533+
534+#define OCR0SBL _SFR_IO8(0x22)
535+#define OCR0SBH _SFR_IO8(0x23)
536+
537+/* Combine OCR0RBL and OCR0RBH */
538+#define OCR0RB _SFR_IO16(0x24)
539+
540+#define OCR0RBL _SFR_IO8(0x24)
541+#define OCR0RBH _SFR_IO8(0x25)
542+
543+/* Combine OCR2SBL and OCR2SBH */
544+#define OCR2SB _SFR_IO16(0x26)
545+
546+#define OCR2SBL _SFR_IO8(0x26)
547+#define OCR2SBH _SFR_IO8(0x27)
548+
549+/* Combine OCR2RBL and OCR2RBH */
550+#define OCR2RB _SFR_IO16(0x28)
551+
552+#define OCR2RBL _SFR_IO8(0x28)
553+#define OCR2RBH _SFR_IO8(0x29)
554+
555+/* Combine OCR0RAL and OCR0RAH */
556+#define OCR0RA _SFR_IO16(0x2A)
557+
558+#define OCR0RAL _SFR_IO8(0x2A)
559+#define OCR0RAH _SFR_IO8(0x2B)
560+
561+/* Combine ADCL and ADCH */
562+#ifndef __ASSEMBLER__
563+#define ADC _SFR_IO16(0x2C)
564+#endif
565+#define ADCW _SFR_IO16(0x2C)
566+
567+#define ADCL _SFR_IO8(0x2C)
568+#define ADCH _SFR_IO8(0x2D)
569+
570+/* Combine OCR2RAL and OCR2RAH */
571+#define OCR2RA _SFR_IO16(0x2E)
572+
573+#define OCR2RAL _SFR_IO8(0x2E)
574+#define OCR2RAH _SFR_IO8(0x2F)
575+
576+/* Reserved [0x30..0x32] */
577+
578+#define SMCR _SFR_IO8(0x33)
579+#define SE 0
580+#define SM0 1
581+#define SM1 2
582+#define SM2 3
583+
584+#define MCUSR _SFR_IO8(0x34)
585+#define PORF 0
586+#define EXTRF 1
587+#define BORF 2
588+#define WDRF 3
589+
590+#define MCUCR _SFR_IO8(0x35)
591+#define IVCE 0
592+#define IVSEL 1
593+#define CKRC81 2
594+#define RSTDIS 3
595+#define PUD 4
596+
597+#define SPDR _SFR_IO8(0x36)
598+
599+#define SPMCSR _SFR_IO8(0x37)
600+#define SPMEN 0
601+#define PGERS 1
602+#define PGWRT 2
603+#define BLBSET 3
604+#define RWWSRE 4
605+#define SIGRD 5
606+#define RWWSB 6
607+#define SPMIE 7
608+
609+#define DACL _SFR_IO8(0x38)
610+#define DACL0 0
611+#define DACL1 1
612+#define DACL2 2
613+#define DACL3 3
614+#define DACL4 4
615+#define DACL5 5
616+#define DACL6 6
617+#define DACL7 7
618+
619+#define DACH _SFR_IO8(0x39)
620+#define DACH0 0
621+#define DACH1 1
622+#define DACH2 2
623+#define DACH3 3
624+#define DACH4 4
625+#define DACH5 5
626+#define DACH6 6
627+#define DACH7 7
628+
629+/* Combine TCNT1L and TCNT1H */
630+#define TCNT1 _SFR_IO16(0x3A)
631+
632+#define TCNT1L _SFR_IO8(0x3A)
633+#define TCNT1H _SFR_IO8(0x3B)
634+
635+/* Reserved [0x3C] */
636+
637+/* SP [0x3D..0x3E] */
638+
639+/* SREG [0x3F] */
640+
641+/* Combine OCR0SAL and OCR0SAH */
642+#define OCR0SA _SFR_MEM16(0x60)
643+
644+#define OCR0SAL _SFR_MEM8(0x60)
645+#define OCR0SAH _SFR_MEM8(0x61)
646+
647+#define PFRC0A _SFR_MEM8(0x62)
648+#define PRFM0A0 0
649+#define PRFM0A1 1
650+#define PRFM0A2 2
651+#define PRFM0A3 3
652+#define PFLTE0A 4
653+#define PELEV0A 5
654+#define PISEL0A 6
655+#define PCAE0A 7
656+
657+#define PFRC0B _SFR_MEM8(0x63)
658+#define PRFM0B0 0
659+#define PRFM0B1 1
660+#define PRFM0B2 2
661+#define PRFM0B3 3
662+#define PFLTE0B 4
663+#define PELEV0B 5
664+#define PISEL0B 6
665+#define PCAE0B 7
666+
667+/* Combine OCR2SAL and OCR2SAH */
668+#define OCR2SA _SFR_MEM16(0x64)
669+
670+#define OCR2SAL _SFR_MEM8(0x64)
671+#define OCR2SAH _SFR_MEM8(0x65)
672+
673+#define PFRC2A _SFR_MEM8(0x66)
674+#define PRFM2A0 0
675+#define PRFM2A1 1
676+#define PRFM2A2 2
677+#define PRFM2A3 3
678+#define PFLTE2A 4
679+#define PELEV2A 5
680+#define PISEL2A 6
681+#define PCAE2A 7
682+
683+#define PFRC2B _SFR_MEM8(0x67)
684+#define PRFM2B0 0
685+#define PRFM2B1 1
686+#define PRFM2B2 2
687+#define PRFM2B3 3
688+#define PFLTE2B 4
689+#define PELEV2B 5
690+#define PISEL2B 6
691+#define PCAE2B 7
692+
693+/* Combine PICR0L and PICR0H */
694+#define PICR0 _SFR_MEM16(0x68)
695+
696+#define PICR0L _SFR_MEM8(0x68)
697+#define PICR0H _SFR_MEM8(0x69)
698+
699+#define PSOC0 _SFR_MEM8(0x6A)
700+#define POEN0A 0
701+#define POEN0B 2
702+#define PSYNC00 4
703+#define PSYNC01 5
704+#define PISEL0B1 6
705+#define PISEL0A1 7
706+
707+/* Reserved [0x6B] */
708+
709+#define PICR2L _SFR_MEM8(0x6C)
710+
711+#define PICR2H _SFR_MEM8(0x6D)
712+#define PICR28 0
713+#define PICR29 1
714+#define PICR210 2
715+#define PICR211 3
716+#define PCST2 7
717+
718+#define PSOC2 _SFR_MEM8(0x6E)
719+#define POEN2A 0
720+#define POEN2C 1
721+#define POEN2B 2
722+#define POEN2D 3
723+#define PSYNC20 4
724+#define PSYNC21 5
725+#define POS22 6
726+#define POS23 7
727+
728+#define POM2 _SFR_MEM8(0x6F)
729+#define POMV2A0 0
730+#define POMV2A1 1
731+#define POMV2A2 2
732+#define POMV2A3 3
733+#define POMV2B0 4
734+#define POMV2B1 5
735+#define POMV2B2 6
736+#define POMV2B3 7
737+
738+#define PCNFE2 _SFR_MEM8(0x70)
739+#define PISEL2B1 0
740+#define PISEL2A1 1
741+#define PELEV2B1 2
742+#define PELEV2A1 3
743+#define PBFM21 4
744+#define PASDLK20 5
745+#define PASDLK21 6
746+#define PASDLK22 7
747+
748+#define PASDLY2 _SFR_MEM8(0x71)
749+
750+/* Reserved [0x72..0x75] */
751+
752+#define DACON _SFR_MEM8(0x76)
753+#define DAEN 0
754+#define DALA 2
755+#define DATS0 4
756+#define DATS1 5
757+#define DATS2 6
758+#define DAATE 7
759+
760+#define DIDR0 _SFR_MEM8(0x77)
761+#define ADC0D 0
762+#define ADC1D 1
763+#define ADC2D 2
764+#define ADC3D 3
765+#define ADC4D 4
766+#define ADC5D 5
767+#define ADC6D 6
768+#define ADC7D 7
769+
770+#define DIDR1 _SFR_MEM8(0x78)
771+#define ADC9D 0
772+#define ADC10D 1
773+#define AMP0POSD 2
774+#define ACMP1MD 3
775+
776+#define AMP0CSR _SFR_MEM8(0x79)
777+#define AMP0TS0 0
778+#define AMP0TS1 1
779+#define AMP0GS 3
780+#define AMP0G0 4
781+#define AMP0G1 5
782+#define AMP0IS 6
783+#define AMP0EN 7
784+
785+#define AC1ECON _SFR_MEM8(0x7A)
786+#define AC1H0 0
787+#define AC1H1 1
788+#define AC1H2 2
789+#define AC1ICE 3
790+#define AC1OE 4
791+#define AC1OI 5
792+
793+#define AC2ECON _SFR_MEM8(0x7B)
794+#define AC2H0 0
795+#define AC2H1 1
796+#define AC2H2 2
797+#define AC2OE 4
798+#define AC2OI 5
799+
800+#define AC3ECON _SFR_MEM8(0x7C)
801+#define AC3H0 0
802+#define AC3H1 1
803+#define AC3H2 2
804+#define AC3OE 4
805+#define AC3OI 5
806+
807+#define AC1CON _SFR_MEM8(0x7D)
808+#define AC1M0 0
809+#define AC1M1 1
810+#define AC1M2 2
811+#define AC1IS0 4
812+#define AC1IS1 5
813+#define AC1IE 6
814+#define AC1EN 7
815+
816+#define AC2CON _SFR_MEM8(0x7E)
817+#define AC2M0 0
818+#define AC2M1 1
819+#define AC2M2 2
820+#define AC2IS0 4
821+#define AC2IS1 5
822+#define AC2IE 6
823+#define AC2EN 7
824+
825+#define AC3CON _SFR_MEM8(0x7F)
826+#define AC3M0 0
827+#define AC3M1 1
828+#define AC3M2 2
829+#define AC3OEA 3
830+#define AC3IS0 4
831+#define AC3IS1 5
832+#define AC3IE 6
833+#define AC3EN 7
834+
835+#define BGCRR _SFR_MEM8(0x80)
836+#define BGCR0 0
837+#define BGCR1 1
838+#define BGCR2 2
839+#define BGCR3 3
840+
841+#define BGCCR _SFR_MEM8(0x81)
842+#define BGCC0 0
843+#define BGCC1 1
844+#define BGCC2 2
845+#define BGCC3 3
846+
847+#define WDTCSR _SFR_MEM8(0x82)
848+#define WDE 3
849+#define WDCE 4
850+#define WDP0 0
851+#define WDP1 1
852+#define WDP2 2
853+#define WDP3 5
854+#define WDIE 6
855+#define WDIF 7
856+
857+#define CLKPR _SFR_MEM8(0x83)
858+#define CLKPS0 0
859+#define CLKPS1 1
860+#define CLKPS2 2
861+#define CLKPS3 3
862+#define CLKPCE 7
863+
864+#define CLKCSR _SFR_MEM8(0x84)
865+#define CLKC0 0
866+#define CLKC1 1
867+#define CLKC2 2
868+#define CLKC3 3
869+#define CLKRDY 4
870+#define CLKCCE 7
871+
872+#define CLKSELR _SFR_MEM8(0x85)
873+#define CKSEL0 0
874+#define CKSEL1 1
875+#define CKSEL2 2
876+#define CKSEL3 3
877+#define CSUT0 4
878+#define CSUT1 5
879+#define COUT 6
880+
881+#define PRR _SFR_MEM8(0x86)
882+#define PRADC 0
883+#define PRSPI 2
884+#define PRTIM1 4
885+#define PRPSCR 5
886+#define PRPSC2 7
887+
888+#define PLLCSR _SFR_MEM8(0x87)
889+#define PLOCK 0
890+#define PLLE 1
891+#define PLLF0 2
892+#define PLLF1 3
893+#define PLLF2 4
894+#define PLLF3 5
895+
896+#define OSCCAL _SFR_MEM8(0x88)
897+
898+#define EICRA _SFR_MEM8(0x89)
899+#define ISC00 0
900+#define ISC01 1
901+#define ISC10 2
902+#define ISC11 3
903+#define ISC20 4
904+#define ISC21 5
905+
906+#define TCCR1B _SFR_MEM8(0x8A)
907+#define CS10 0
908+#define CS11 1
909+#define CS12 2
910+#define WGM13 4
911+#define ICES1 6
912+#define ICNC1 7
913+
914+/* Reserved [0x8B] */
915+
916+/* Combine ICR1L and ICR1H */
917+#define ICR1 _SFR_MEM16(0x8C)
918+
919+#define ICR1L _SFR_MEM8(0x8C)
920+#define ICR1H _SFR_MEM8(0x8D)
921+
922+
923+
924+/* Interrupt vectors */
925+/* Vector 0 is the reset vector */
926+/* PSC2 Capture Event */
927+#define PSC2_CAPT_vect _VECTOR(1)
928+#define PSC2_CAPT_vect_num 1
929+
930+/* PSC2 End Cycle */
931+#define PSC2_EC_vect _VECTOR(2)
932+#define PSC2_EC_vect_num 2
933+
934+/* PSC2 End Of Enhanced Cycle */
935+#define PSC2_EEC_vect _VECTOR(3)
936+#define PSC2_EEC_vect_num 3
937+
938+/* PSC0 Capture Event */
939+#define PSC0_CAPT_vect _VECTOR(4)
940+#define PSC0_CAPT_vect_num 4
941+
942+/* PSC0 End Cycle */
943+#define PSC0_EC_vect _VECTOR(5)
944+#define PSC0_EC_vect_num 5
945+
946+/* PSC0 End Of Enhanced Cycle */
947+#define PSC0_EEC_vect _VECTOR(6)
948+#define PSC0_EEC_vect_num 6
949+
950+/* Analog Comparator 1 */
951+#define ANALOG_COMP_1_vect _VECTOR(7)
952+#define ANALOG_COMP_1_vect_num 7
953+
954+/* Analog Comparator 2 */
955+#define ANALOG_COMP_2_vect _VECTOR(8)
956+#define ANALOG_COMP_2_vect_num 8
957+
958+/* Analog Comparator 3 */
959+#define ANALOG_COMP_3_vect _VECTOR(9)
960+#define ANALOG_COMP_3_vect_num 9
961+
962+/* External Interrupt Request 0 */
963+#define INT0_vect _VECTOR(10)
964+#define INT0_vect_num 10
965+
966+/* Timer/Counter1 Capture Event */
967+#define TIMER1_CAPT_vect _VECTOR(11)
968+#define TIMER1_CAPT_vect_num 11
969+
970+/* Timer/Counter1 Overflow */
971+#define TIMER1_OVF_vect _VECTOR(12)
972+#define TIMER1_OVF_vect_num 12
973+
974+/* ADC Conversion Complete */
975+#define ADC_vect _VECTOR(13)
976+#define ADC_vect_num 13
977+
978+/* External Interrupt Request 1 */
979+#define INT1_vect _VECTOR(14)
980+#define INT1_vect_num 14
981+
982+/* SPI Serial Transfer Complet */
983+#define SPI__STC_vect _VECTOR(15)
984+#define SPI__STC_vect_num 15
985+
986+/* External Interrupt Request 2 */
987+#define INT2_vect _VECTOR(16)
988+#define INT2_vect_num 16
989+
990+/* Watchdog Timeout Interrupt */
991+#define WDT_vect _VECTOR(17)
992+#define WDT_vect_num 17
993+
994+/* EEPROM Ready */
995+#define EE_READY_vect _VECTOR(18)
996+#define EE_READY_vect_num 18
997+
998+/* Store Program Memory Read */
999+#define SPM_READY_vect _VECTOR(19)
1000+#define SPM_READY_vect_num 19
1001+
1002+#define _VECTORS_SIZE 80
1003+
1004+
1005+/* Constants */
1006+
1007+#define SPM_PAGESIZE 128
1008+#define FLASHEND 0x3FFF
1009+#define RAMSTART 0x0100
1010+#define RAMSIZE 1024
1011+#define RAMEND 0x04FF
1012+#define E2START 0
1013+#define E2SIZE 512
1014+#define E2PAGESIZE 4
1015+#define E2END 0x01FF
1016+#define XRAMEND RAMEND
1017+
1018+
1019+/* Fuses */
1020+
1021+#define FUSE_MEMORY_SIZE 3
1022+
1023+/* Low Fuse Byte */
1024+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
1025+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
1026+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
1027+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
1028+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
1029+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
1030+#define FUSE_CKOUT (unsigned char)~_BV(6)
1031+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
1032+
1033+/* High Fuse Byte */
1034+#define FUSE_BOOTRST (unsigned char)~_BV(0)
1035+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
1036+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
1037+#define FUSE_EESAVE (unsigned char)~_BV(3)
1038+#define FUSE_WDTON (unsigned char)~_BV(4)
1039+#define FUSE_SPIEN (unsigned char)~_BV(5)
1040+#define FUSE_DWEN (unsigned char)~_BV(6)
1041+#define FUSE_RSTDISBL (unsigned char)~_BV(7)
1042+
1043+/* Extended Fuse Byte */
1044+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
1045+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
1046+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
1047+#define FUSE_PSCINRB (unsigned char)~_BV(3)
1048+#define FUSE_PSCRV (unsigned char)~_BV(4)
1049+#define FUSE_PSC0RB (unsigned char)~_BV(5)
1050+#define FUSE_PSC2RBA (unsigned char)~_BV(6)
1051+#define FUSE_PSC2RB (unsigned char)~_BV(7)
1052+
1053+
1054+/* Lock Bits */
1055+#define __LOCK_BITS_EXIST
1056+#define __BOOT_LOCK_BITS_0_EXIST
1057+#define __BOOT_LOCK_BITS_1_EXIST
1058+
1059+
1060+/* Signature */
1061+#define SIGNATURE_0 0x1E
1062+#define SIGNATURE_1 0x94
1063+#define SIGNATURE_2 0x8B
1064+
1065+
1066+#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */
1067+
1068diff -urN avr-libc-1.8.0.orig/include/avr/ioa5272.h avr-libc-1.8.0/include/avr/ioa5272.h
1069--- avr-libc-1.8.0.orig/include/avr/ioa5272.h 1970-01-01 01:00:00.000000000 +0100
1070+++ avr-libc-1.8.0/include/avr/ioa5272.h 2013-01-18 09:50:25.000000000 +0100
1071@@ -0,0 +1,736 @@
1072+/*****************************************************************************
1073+ *
1074+ * Copyright (C) 2012 Atmel Corporation
1075+ * All rights reserved.
1076+ *
1077+ * Redistribution and use in source and binary forms, with or without
1078+ * modification, are permitted provided that the following conditions are met:
1079+ *
1080+ * * Redistributions of source code must retain the above copyright
1081+ * notice, this list of conditions and the following disclaimer.
1082+ *
1083+ * * Redistributions in binary form must reproduce the above copyright
1084+ * notice, this list of conditions and the following disclaimer in
1085+ * the documentation and/or other materials provided with the
1086+ * distribution.
1087+ *
1088+ * * Neither the name of the copyright holders nor the names of
1089+ * contributors may be used to endorse or promote products derived
1090+ * from this software without specific prior written permission.
1091+ *
1092+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1093+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1094+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1095+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
1096+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1097+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1098+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1099+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1100+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1101+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1102+ * POSSIBILITY OF SUCH DAMAGE.
1103+ ****************************************************************************/
1104+
1105+
1106+#ifndef _AVR_ATA5272_H_INCLUDED
1107+#define _AVR_ATA5272_H_INCLUDED
1108+
1109+
1110+#ifndef _AVR_IO_H_
1111+# error "Include <avr/io.h> instead of this file."
1112+#endif
1113+
1114+#ifndef _AVR_IOXXX_H_
1115+# define _AVR_IOXXX_H_ "ioa5272.h"
1116+#else
1117+# error "Attempt to include more than one <avr/ioXXX.h> file."
1118+#endif
1119+
1120+/* Registers and associated bit numbers */
1121+
1122+#define PINA _SFR_IO8(0x00)
1123+#define PINA7 7
1124+#define PINA6 6
1125+#define PINA5 5
1126+#define PINA4 4
1127+#define PINA3 3
1128+#define PINA2 2
1129+#define PINA1 1
1130+#define PINA0 0
1131+
1132+#define DDRA _SFR_IO8(0x01)
1133+#define DDRA7 7
1134+#define DDRA6 6
1135+#define DDRA5 5
1136+#define DDRA4 4
1137+#define DDRA3 3
1138+#define DDRA2 2
1139+#define DDRA1 1
1140+#define DDRA0 0
1141+
1142+#define PORTA _SFR_IO8(0x02)
1143+#define PORTA7 7
1144+#define PORTA6 6
1145+#define PORTA5 5
1146+#define PORTA4 4
1147+#define PORTA3 3
1148+#define PORTA2 2
1149+#define PORTA1 1
1150+#define PORTA0 0
1151+
1152+#define PINB _SFR_IO8(0x03)
1153+#define PINB7 7
1154+#define PINB6 6
1155+#define PINB5 5
1156+#define PINB4 4
1157+#define PINB3 3
1158+#define PINB2 2
1159+#define PINB1 1
1160+#define PINB0 0
1161+
1162+#define DDRB _SFR_IO8(0x04)
1163+#define DDRB7 7
1164+#define DDRB6 6
1165+#define DDRB5 5
1166+#define DDRB4 4
1167+#define DDRB3 3
1168+#define DDRB2 2
1169+#define DDRB1 1
1170+#define DDRB0 0
1171+
1172+#define PORTB _SFR_IO8(0x05)
1173+#define PORTB7 7
1174+#define PORTB6 6
1175+#define PORTB5 5
1176+#define PORTB4 4
1177+#define PORTB3 3
1178+#define PORTB2 2
1179+#define PORTB1 1
1180+#define PORTB0 0
1181+
1182+/* Reserved [0x06..0x11] */
1183+
1184+#define PORTCR _SFR_IO8(0x12)
1185+
1186+/* Reserved [0x13..0x14] */
1187+
1188+#define TIFR0 _SFR_IO8(0x15)
1189+#define TOV0 0
1190+#define OCF0A 1
1191+
1192+#define TIFR1 _SFR_IO8(0x16)
1193+#define TOV1 0
1194+#define OCF1A 1
1195+#define OCF1B 2
1196+#define ICF1 5
1197+
1198+/* Reserved [0x17..0x1A] */
1199+
1200+#define PCIFR _SFR_IO8(0x1B)
1201+#define PCIF0 0
1202+#define PCIF1 1
1203+
1204+#define EIFR _SFR_IO8(0x1C)
1205+#define INTF0 0
1206+#define INTF1 1
1207+
1208+#define EIMSK _SFR_IO8(0x1D)
1209+#define INT0 0
1210+#define INT1 1
1211+
1212+#define GPIOR0 _SFR_IO8(0x1E)
1213+
1214+#define EECR _SFR_IO8(0x1F)
1215+#define EERE 0
1216+#define EEPE 1
1217+#define EEMPE 2
1218+#define EERIE 3
1219+#define EEPM0 4
1220+#define EEPM1 5
1221+
1222+#define EEDR _SFR_IO8(0x20)
1223+
1224+/* Combine EEARL and EEARH */
1225+#define EEAR _SFR_IO16(0x21)
1226+
1227+#define EEARL _SFR_IO8(0x21)
1228+#define EEARH _SFR_IO8(0x22)
1229+
1230+#define GTCCR _SFR_IO8(0x23)
1231+#define PSR1 0
1232+#define PSR0 1
1233+#define TSM 7
1234+
1235+/* Reserved [0x24] */
1236+
1237+#define TCCR0A _SFR_IO8(0x25)
1238+#define WGM00 0
1239+#define WGM01 1
1240+#define COM0A0 6
1241+#define COM0A1 7
1242+
1243+#define TCCR0B _SFR_IO8(0x26)
1244+#define CS00 0
1245+#define CS01 1
1246+#define CS02 2
1247+#define FOC0A 7
1248+
1249+#define TCNT2 _SFR_IO8(0x27)
1250+
1251+#define OCR0A _SFR_IO8(0x28)
1252+
1253+/* Reserved [0x29] */
1254+
1255+#define GPIOR1 _SFR_IO8(0x2A)
1256+
1257+#define GPIOR2 _SFR_IO8(0x2B)
1258+
1259+#define SPCR _SFR_IO8(0x2C)
1260+#define SPR0 0
1261+#define SPR1 1
1262+#define CPHA 2
1263+#define CPOL 3
1264+#define MSTR 4
1265+#define DORD 5
1266+#define SPE 6
1267+#define SPIE 7
1268+
1269+#define SPSR _SFR_IO8(0x2D)
1270+#define SPI2X 0
1271+#define WCOL 6
1272+#define SPIF 7
1273+
1274+#define SPDR _SFR_IO8(0x2E)
1275+
1276+/* Reserved [0x2F] */
1277+
1278+#define ACSR _SFR_IO8(0x30)
1279+#define ACIS0 0
1280+#define ACIS1 1
1281+#define ACIC 2
1282+#define ACIE 3
1283+#define ACI 4
1284+#define ACO 5
1285+#define ACIRS 6
1286+#define ACD 7
1287+
1288+#define DWDR _SFR_IO8(0x31)
1289+
1290+/* Reserved [0x32] */
1291+
1292+#define MCUSR _SFR_IO8(0x33)
1293+#define SE 0
1294+#define SM0 1
1295+#define SM1 2
1296+#define PORF 0
1297+#define EXTRF 1
1298+#define BORF 2
1299+#define WDRF 3
1300+
1301+/* Reserved [0x34] */
1302+
1303+#define MCUCR _SFR_IO8(0x35)
1304+#define PUD 4
1305+#define BODS 5
1306+#define BODSE 6
1307+
1308+/* Reserved [0x36] */
1309+
1310+#define SPMCSR _SFR_IO8(0x37)
1311+#define SPMEN 0
1312+#define PGERS 1
1313+#define PGWRT 2
1314+#define RFLB 3
1315+#define CTPB 4
1316+#define SIGRD 5
1317+#define RWWSB 6
1318+
1319+/* Reserved [0x38..0x3C] */
1320+
1321+/* SP [0x3D..0x3E] */
1322+
1323+/* SREG [0x3F] */
1324+
1325+#define WDTCR _SFR_MEM8(0x60)
1326+#define WDE 3
1327+#define WDCE 4
1328+#define WDP0 0
1329+#define WDP1 1
1330+#define WDP2 2
1331+#define WDP3 5
1332+#define WDIE 6
1333+#define WDIF 7
1334+
1335+#define CLKPR _SFR_MEM8(0x61)
1336+#define CLKPS0 0
1337+#define CLKPS1 1
1338+#define CLKPS2 2
1339+#define CLKPS3 3
1340+#define CLKPCE 7
1341+
1342+#define CLKCSR _SFR_MEM8(0x62)
1343+#define CLKC0 0
1344+#define CLKC1 1
1345+#define CLKC2 2
1346+#define CLKC3 3
1347+#define CLKRDY 4
1348+#define CLKCCE 7
1349+
1350+#define CLKSELR _SFR_MEM8(0x63)
1351+#define CSEL0 0
1352+#define CSEL1 1
1353+#define CSEL2 2
1354+#define CSEL3 3
1355+#define CSUT0 4
1356+#define CSUT1 5
1357+#define COUT 6
1358+
1359+#define PRR _SFR_MEM8(0x64)
1360+#define PRADC 0
1361+#define PRUSI 1
1362+#define PRTIM0 2
1363+#define PRTIM1 3
1364+#define PRSPI 4
1365+#define PRLIN 5
1366+
1367+/* Reserved [0x65] */
1368+
1369+#define OSCCAL _SFR_MEM8(0x66)
1370+
1371+/* Reserved [0x67] */
1372+
1373+#define PCICR _SFR_MEM8(0x68)
1374+#define PCIE0 0
1375+#define PCIE1 1
1376+
1377+#define EICRA _SFR_MEM8(0x69)
1378+#define ISC00 0
1379+#define ISC01 1
1380+#define ISC10 2
1381+#define ISC11 3
1382+
1383+/* Reserved [0x6A] */
1384+
1385+#define PCMSK0 _SFR_MEM8(0x6B)
1386+#define PCINT0 0
1387+#define PCINT1 1
1388+#define PCINT2 2
1389+#define PCINT3 3
1390+#define PCINT4 4
1391+#define PCINT5 5
1392+#define PCINT6 6
1393+#define PCINT7 7
1394+
1395+#define PCMSK1 _SFR_MEM8(0x6C)
1396+#define PCINT8 0
1397+#define PCINT9 1
1398+#define PCINT10 2
1399+#define PCINT11 3
1400+#define PCINT12 4
1401+#define PCINT13 5
1402+#define PCINT14 6
1403+#define PCINT15 7
1404+
1405+/* Reserved [0x6D] */
1406+
1407+#define TIMSK0 _SFR_MEM8(0x6E)
1408+#define TOIE0 0
1409+#define OCIE0A 1
1410+
1411+#define TIMSK1 _SFR_MEM8(0x6F)
1412+#define TOIE1 0
1413+#define OCIE1A 1
1414+#define OCIE1B 2
1415+#define ICIE1 5
1416+
1417+/* Reserved [0x70..0x76] */
1418+
1419+#define AMISCR _SFR_MEM8(0x77)
1420+#define XREFEN 1
1421+#define AREFEN 2
1422+#define ISRCEN 0
1423+
1424+/* Combine ADCL and ADCH */
1425+#ifndef __ASSEMBLER__
1426+#define ADC _SFR_MEM16(0x78)
1427+#endif
1428+#define ADCW _SFR_MEM16(0x78)
1429+
1430+#define ADCL _SFR_MEM8(0x78)
1431+#define ADCH _SFR_MEM8(0x79)
1432+
1433+#define ADCSRA _SFR_MEM8(0x7A)
1434+#define ADPS0 0
1435+#define ADPS1 1
1436+#define ADPS2 2
1437+#define ADIE 3
1438+#define ADIF 4
1439+#define ADATE 5
1440+#define ADSC 6
1441+#define ADEN 7
1442+
1443+#define ADCSRB _SFR_MEM8(0x7B)
1444+#define ADTS0 0
1445+#define ADTS1 1
1446+#define ADTS2 2
1447+#define BIN 7
1448+#define ACIR0 4
1449+#define ACIR1 5
1450+#define ACME 6
1451+
1452+#define ADMUX _SFR_MEM8(0x7C)
1453+#define MUX0 0
1454+#define MUX1 1
1455+#define MUX2 2
1456+#define MUX3 3
1457+#define MUX4 4
1458+#define ADLAR 5
1459+#define REFS0 6
1460+#define REFS1 7
1461+
1462+/* Reserved [0x7D] */
1463+
1464+#define DIDR0 _SFR_MEM8(0x7E)
1465+#define ADC0D 0
1466+#define ADC1D 1
1467+#define ADC2D 2
1468+#define ADC3D 3
1469+#define ADC4D 4
1470+#define ADC5D 5
1471+#define ADC6D 6
1472+#define ADC7D 7
1473+
1474+#define DIDR1 _SFR_MEM8(0x7F)
1475+#define ADC8D 0
1476+#define ADC9D 1
1477+#define ADC10D 2
1478+
1479+#define TCCR1A _SFR_MEM8(0x80)
1480+#define WGM10 0
1481+#define WGM11 1
1482+#define COM1B0 4
1483+#define COM1B1 5
1484+#define COM1A0 6
1485+#define COM1A1 7
1486+
1487+#define TCCR1B _SFR_MEM8(0x81)
1488+#define CS10 0
1489+#define CS11 1
1490+#define CS12 2
1491+#define WGM12 3
1492+#define WGM13 4
1493+#define ICES1 6
1494+#define ICNC1 7
1495+
1496+#define TCCR1C _SFR_MEM8(0x82)
1497+#define FOC1B 6
1498+#define FOC1A 7
1499+
1500+#define TCCR1D _SFR_MEM8(0x83)
1501+#define OC1AU 0
1502+#define OC1AV 1
1503+#define OC1AW 2
1504+#define OC1AX 3
1505+#define OC1BU 4
1506+#define OC1BV 5
1507+#define OC1BW 6
1508+#define OC1BX 7
1509+
1510+/* Combine TCNT1L and TCNT1H */
1511+#define TCNT1 _SFR_MEM16(0x84)
1512+
1513+#define TCNT1L _SFR_MEM8(0x84)
1514+#define TCNT1H _SFR_MEM8(0x85)
1515+
1516+/* Combine ICR1L and ICR1H */
1517+#define ICR1 _SFR_MEM16(0x86)
1518+
1519+#define ICR1L _SFR_MEM8(0x86)
1520+#define ICR1H _SFR_MEM8(0x87)
1521+
1522+/* Combine OCR1AL and OCR1AH */
1523+#define OCR1A _SFR_MEM16(0x88)
1524+
1525+#define OCR1AL _SFR_MEM8(0x88)
1526+#define OCR1AH _SFR_MEM8(0x89)
1527+
1528+/* Combine OCR1BL and OCR1BH */
1529+#define OCR1B _SFR_MEM16(0x8A)
1530+
1531+#define OCR1BL _SFR_MEM8(0x8A)
1532+#define OCR1BH _SFR_MEM8(0x8B)
1533+
1534+/* Reserved [0x8C..0xB5] */
1535+
1536+#define ASSR _SFR_MEM8(0xB6)
1537+#define TCR0BUB 0
1538+#define TCR0AUB 1
1539+#define OCR0AUB 3
1540+#define TCN0UB 4
1541+#define AS0 5
1542+#define EXCLK 6
1543+
1544+/* Reserved [0xB7] */
1545+
1546+#define USICR _SFR_MEM8(0xB8)
1547+#define USITC 0
1548+#define USICLK 1
1549+#define USICS0 2
1550+#define USICS1 3
1551+#define USIWM0 4
1552+#define USIWM1 5
1553+#define USIOIE 6
1554+#define USISIE 7
1555+
1556+#define USISR _SFR_MEM8(0xB9)
1557+#define USICNT0 0
1558+#define USICNT1 1
1559+#define USICNT2 2
1560+#define USICNT3 3
1561+#define USIDC 4
1562+#define USIPF 5
1563+#define USIOIF 6
1564+#define USISIF 7
1565+
1566+#define USIDR _SFR_MEM8(0xBA)
1567+
1568+#define USIBR _SFR_MEM8(0xBB)
1569+
1570+#define USIPP _SFR_MEM8(0xBC)
1571+
1572+/* Reserved [0xBD..0xC7] */
1573+
1574+#define LINCR _SFR_MEM8(0xC8)
1575+#define LCMD0 0
1576+#define LCMD1 1
1577+#define LCMD2 2
1578+#define LENA 3
1579+#define LCONF0 4
1580+#define LCONF1 5
1581+#define LIN13 6
1582+#define LSWRES 7
1583+
1584+#define LINSIR _SFR_MEM8(0xC9)
1585+#define LRXOK 0
1586+#define LTXOK 1
1587+#define LIDOK 2
1588+#define LERR 3
1589+#define LBUSY 4
1590+#define LIDST0 5
1591+#define LIDST1 6
1592+#define LIDST2 7
1593+
1594+#define LINENIR _SFR_MEM8(0xCA)
1595+#define LENRXOK 0
1596+#define LENTXOK 1
1597+#define LENIDOK 2
1598+#define LENERR 3
1599+
1600+#define LINERR _SFR_MEM8(0xCB)
1601+#define LBERR 0
1602+#define LCERR 1
1603+#define LPERR 2
1604+#define LSERR 3
1605+#define LFERR 4
1606+#define LOVERR 5
1607+#define LTOERR 6
1608+#define LABORT 7
1609+
1610+#define LINBTR _SFR_MEM8(0xCC)
1611+#define LBT0 0
1612+#define LBT1 1
1613+#define LBT2 2
1614+#define LBT3 3
1615+#define LBT4 4
1616+#define LBT5 5
1617+#define LDISR 7
1618+
1619+#define LINBRRL _SFR_MEM8(0xCD)
1620+#define LDIV0 0
1621+#define LDIV1 1
1622+#define LDIV2 2
1623+#define LDIV3 3
1624+#define LDIV4 4
1625+#define LDIV5 5
1626+#define LDIV6 6
1627+#define LDIV7 7
1628+
1629+#define LINBRRH _SFR_MEM8(0xCE)
1630+#define LDIV8 0
1631+#define LDIV9 1
1632+#define LDIV10 2
1633+#define LDIV11 3
1634+
1635+#define LINDLR _SFR_MEM8(0xCF)
1636+#define LRXDL0 0
1637+#define LRXDL1 1
1638+#define LRXDL2 2
1639+#define LRXDL3 3
1640+#define LTXDL0 4
1641+#define LTXDL1 5
1642+#define LTXDL2 6
1643+#define LTXDL3 7
1644+
1645+#define LINIDR _SFR_MEM8(0xD0)
1646+#define LID0 0
1647+#define LID1 1
1648+#define LID2 2
1649+#define LID3 3
1650+#define LID4 4
1651+#define LID5 5
1652+#define LP0 6
1653+#define LP1 7
1654+
1655+#define LINSEL _SFR_MEM8(0xD1)
1656+#define LINDX0 0
1657+#define LINDX1 1
1658+#define LINDX2 2
1659+#define LAINC 3
1660+
1661+#define LINDAT _SFR_MEM8(0xD2)
1662+#define LDATA0 0
1663+#define LDATA1 1
1664+#define LDATA2 2
1665+#define LDATA3 3
1666+#define LDATA4 4
1667+#define LDATA5 5
1668+#define LDATA6 6
1669+#define LDATA7 7
1670+
1671+
1672+
1673+/* Interrupt vectors */
1674+/* Vector 0 is the reset vector */
1675+/* External Interrupt Request 0 */
1676+#define INT0_vect _VECTOR(1)
1677+#define INT0_vect_num 1
1678+
1679+/* External Interrupt Request 1 */
1680+#define INT1_vect _VECTOR(2)
1681+#define INT1_vect_num 2
1682+
1683+/* Pin Change Interrupt Request 0 */
1684+#define PCINT0_vect _VECTOR(3)
1685+#define PCINT0_vect_num 3
1686+
1687+/* Pin Change Interrupt Request 1 */
1688+#define PCINT1_vect _VECTOR(4)
1689+#define PCINT1_vect_num 4
1690+
1691+/* Watchdog Time-Out Interrupt */
1692+#define WDT_vect _VECTOR(5)
1693+#define WDT_vect_num 5
1694+
1695+/* Timer/Counter1 Capture Event */
1696+#define TIMER1_CAPT_vect _VECTOR(6)
1697+#define TIMER1_CAPT_vect_num 6
1698+
1699+/* Timer/Counter1 Compare Match 1A */
1700+#define TIMER1_COMPA_vect _VECTOR(7)
1701+#define TIMER1_COMPA_vect_num 7
1702+
1703+/* Timer/Counter1 Compare Match 1B */
1704+#define TIMER1_COMPB_vect _VECTOR(8)
1705+#define TIMER1_COMPB_vect_num 8
1706+
1707+/* Timer/Counter1 Overflow */
1708+#define TIMER1_OVF_vect _VECTOR(9)
1709+#define TIMER1_OVF_vect_num 9
1710+
1711+/* Timer/Counter0 Compare Match 0A */
1712+#define TIMER0_COMPA_vect _VECTOR(10)
1713+#define TIMER0_COMPA_vect_num 10
1714+
1715+/* Timer/Counter0 Overflow */
1716+#define TIMER0_OVF_vect _VECTOR(11)
1717+#define TIMER0_OVF_vect_num 11
1718+
1719+/* LIN Transfer Complete */
1720+#define LIN_TC_vect _VECTOR(12)
1721+#define LIN_TC_vect_num 12
1722+
1723+/* LIN Error */
1724+#define LIN_ERR_vect _VECTOR(13)
1725+#define LIN_ERR_vect_num 13
1726+
1727+/* SPI Serial Transfer Complete */
1728+#define SPI_STC_vect _VECTOR(14)
1729+#define SPI_STC_vect_num 14
1730+
1731+/* ADC Conversion Complete */
1732+#define ADC_vect _VECTOR(15)
1733+#define ADC_vect_num 15
1734+
1735+/* EEPROM Ready */
1736+#define EE_RDY_vect _VECTOR(16)
1737+#define EE_RDY_vect_num 16
1738+
1739+/* Analog Comparator */
1740+#define ANA_COMP_vect _VECTOR(34)
1741+#define ANA_COMP_vect_num 34
1742+
1743+/* USI Start */
1744+#define USI_START_vect _VECTOR(36)
1745+#define USI_START_vect_num 36
1746+
1747+/* USI Overflow */
1748+#define USI_OVF_vect _VECTOR(19)
1749+#define USI_OVF_vect_num 19
1750+
1751+#define _VECTORS_SIZE 40
1752+
1753+
1754+/* Constants */
1755+
1756+#define SPM_PAGESIZE 128
1757+#define FLASHEND 0x1FFF
1758+#define RAMSTART 0x0100
1759+#define RAMSIZE 512
1760+#define RAMEND 0x02FF
1761+#define E2START 0
1762+#define E2SIZE 512
1763+#define E2PAGESIZE 4
1764+#define E2END 0x01FF
1765+#define XRAMEND RAMEND
1766+
1767+
1768+/* Fuses */
1769+
1770+#define FUSE_MEMORY_SIZE 3
1771+
1772+/* Low Fuse Byte */
1773+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
1774+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
1775+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
1776+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
1777+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
1778+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
1779+#define FUSE_CKOUT (unsigned char)~_BV(6)
1780+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
1781+
1782+/* High Fuse Byte */
1783+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
1784+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
1785+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
1786+#define FUSE_EESAVE (unsigned char)~_BV(3)
1787+#define FUSE_WDTON (unsigned char)~_BV(4)
1788+#define FUSE_SPIEN (unsigned char)~_BV(5)
1789+#define FUSE_DWEN (unsigned char)~_BV(6)
1790+#define FUSE_RSTDISBL (unsigned char)~_BV(7)
1791+
1792+/* Extended Fuse Byte */
1793+#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
1794+
1795+
1796+/* Lock Bits */
1797+#define __LOCK_BITS_EXIST
1798+
1799+
1800+/* Signature */
1801+#define SIGNATURE_0 0x1E
1802+#define SIGNATURE_1 0x93
1803+#define SIGNATURE_2 0x87
1804+
1805+
1806+#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */
1807+
1808diff -urN avr-libc-1.8.0.orig/include/avr/ioa5505.h avr-libc-1.8.0/include/avr/ioa5505.h
1809--- avr-libc-1.8.0.orig/include/avr/ioa5505.h 1970-01-01 01:00:00.000000000 +0100
1810+++ avr-libc-1.8.0/include/avr/ioa5505.h 2013-01-18 09:50:25.000000000 +0100
1811@@ -0,0 +1,736 @@
1812+/*****************************************************************************
1813+ *
1814+ * Copyright (C) 2012 Atmel Corporation
1815+ * All rights reserved.
1816+ *
1817+ * Redistribution and use in source and binary forms, with or without
1818+ * modification, are permitted provided that the following conditions are met:
1819+ *
1820+ * * Redistributions of source code must retain the above copyright
1821+ * notice, this list of conditions and the following disclaimer.
1822+ *
1823+ * * Redistributions in binary form must reproduce the above copyright
1824+ * notice, this list of conditions and the following disclaimer in
1825+ * the documentation and/or other materials provided with the
1826+ * distribution.
1827+ *
1828+ * * Neither the name of the copyright holders nor the names of
1829+ * contributors may be used to endorse or promote products derived
1830+ * from this software without specific prior written permission.
1831+ *
1832+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1833+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1834+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1835+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
1836+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1837+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1838+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1839+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1840+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1841+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1842+ * POSSIBILITY OF SUCH DAMAGE.
1843+ ****************************************************************************/
1844+
1845+
1846+#ifndef _AVR_ATA5505_H_INCLUDED
1847+#define _AVR_ATA5505_H_INCLUDED
1848+
1849+
1850+#ifndef _AVR_IO_H_
1851+# error "Include <avr/io.h> instead of this file."
1852+#endif
1853+
1854+#ifndef _AVR_IOXXX_H_
1855+# define _AVR_IOXXX_H_ "ioa5505.h"
1856+#else
1857+# error "Attempt to include more than one <avr/ioXXX.h> file."
1858+#endif
1859+
1860+/* Registers and associated bit numbers */
1861+
1862+#define PINA _SFR_IO8(0x00)
1863+#define PINA7 7
1864+#define PINA6 6
1865+#define PINA5 5
1866+#define PINA4 4
1867+#define PINA3 3
1868+#define PINA2 2
1869+#define PINA1 1
1870+#define PINA0 0
1871+
1872+#define DDRA _SFR_IO8(0x01)
1873+#define DDRA7 7
1874+#define DDRA6 6
1875+#define DDRA5 5
1876+#define DDRA4 4
1877+#define DDRA3 3
1878+#define DDRA2 2
1879+#define DDRA1 1
1880+#define DDRA0 0
1881+
1882+#define PORTA _SFR_IO8(0x02)
1883+#define PORTA7 7
1884+#define PORTA6 6
1885+#define PORTA5 5
1886+#define PORTA4 4
1887+#define PORTA3 3
1888+#define PORTA2 2
1889+#define PORTA1 1
1890+#define PORTA0 0
1891+
1892+#define PINB _SFR_IO8(0x03)
1893+#define PINB7 7
1894+#define PINB6 6
1895+#define PINB5 5
1896+#define PINB4 4
1897+#define PINB3 3
1898+#define PINB2 2
1899+#define PINB1 1
1900+#define PINB0 0
1901+
1902+#define DDRB _SFR_IO8(0x04)
1903+#define DDRB7 7
1904+#define DDRB6 6
1905+#define DDRB5 5
1906+#define DDRB4 4
1907+#define DDRB3 3
1908+#define DDRB2 2
1909+#define DDRB1 1
1910+#define DDRB0 0
1911+
1912+#define PORTB _SFR_IO8(0x05)
1913+#define PORTB7 7
1914+#define PORTB6 6
1915+#define PORTB5 5
1916+#define PORTB4 4
1917+#define PORTB3 3
1918+#define PORTB2 2
1919+#define PORTB1 1
1920+#define PORTB0 0
1921+
1922+/* Reserved [0x06..0x11] */
1923+
1924+#define PORTCR _SFR_IO8(0x12)
1925+
1926+/* Reserved [0x13..0x14] */
1927+
1928+#define TIFR0 _SFR_IO8(0x15)
1929+#define TOV0 0
1930+#define OCF0A 1
1931+
1932+#define TIFR1 _SFR_IO8(0x16)
1933+#define TOV1 0
1934+#define OCF1A 1
1935+#define OCF1B 2
1936+#define ICF1 5
1937+
1938+/* Reserved [0x17..0x1A] */
1939+
1940+#define PCIFR _SFR_IO8(0x1B)
1941+#define PCIF0 0
1942+#define PCIF1 1
1943+
1944+#define EIFR _SFR_IO8(0x1C)
1945+#define INTF0 0
1946+#define INTF1 1
1947+
1948+#define EIMSK _SFR_IO8(0x1D)
1949+#define INT0 0
1950+#define INT1 1
1951+
1952+#define GPIOR0 _SFR_IO8(0x1E)
1953+
1954+#define EECR _SFR_IO8(0x1F)
1955+#define EERE 0
1956+#define EEPE 1
1957+#define EEMPE 2
1958+#define EERIE 3
1959+#define EEPM0 4
1960+#define EEPM1 5
1961+
1962+#define EEDR _SFR_IO8(0x20)
1963+
1964+/* Combine EEARL and EEARH */
1965+#define EEAR _SFR_IO16(0x21)
1966+
1967+#define EEARL _SFR_IO8(0x21)
1968+#define EEARH _SFR_IO8(0x22)
1969+
1970+#define GTCCR _SFR_IO8(0x23)
1971+#define PSR1 0
1972+#define PSR0 1
1973+#define TSM 7
1974+
1975+/* Reserved [0x24] */
1976+
1977+#define TCCR0A _SFR_IO8(0x25)
1978+#define WGM00 0
1979+#define WGM01 1
1980+#define COM0A0 6
1981+#define COM0A1 7
1982+
1983+#define TCCR0B _SFR_IO8(0x26)
1984+#define CS00 0
1985+#define CS01 1
1986+#define CS02 2
1987+#define FOC0A 7
1988+
1989+#define TCNT2 _SFR_IO8(0x27)
1990+
1991+#define OCR0A _SFR_IO8(0x28)
1992+
1993+/* Reserved [0x29] */
1994+
1995+#define GPIOR1 _SFR_IO8(0x2A)
1996+
1997+#define GPIOR2 _SFR_IO8(0x2B)
1998+
1999+#define SPCR _SFR_IO8(0x2C)
2000+#define SPR0 0
2001+#define SPR1 1
2002+#define CPHA 2
2003+#define CPOL 3
2004+#define MSTR 4
2005+#define DORD 5
2006+#define SPE 6
2007+#define SPIE 7
2008+
2009+#define SPSR _SFR_IO8(0x2D)
2010+#define SPI2X 0
2011+#define WCOL 6
2012+#define SPIF 7
2013+
2014+#define SPDR _SFR_IO8(0x2E)
2015+
2016+/* Reserved [0x2F] */
2017+
2018+#define ACSR _SFR_IO8(0x30)
2019+#define ACIS0 0
2020+#define ACIS1 1
2021+#define ACIC 2
2022+#define ACIE 3
2023+#define ACI 4
2024+#define ACO 5
2025+#define ACIRS 6
2026+#define ACD 7
2027+
2028+#define DWDR _SFR_IO8(0x31)
2029+
2030+/* Reserved [0x32] */
2031+
2032+#define MCUSR _SFR_IO8(0x33)
2033+#define SE 0
2034+#define SM0 1
2035+#define SM1 2
2036+#define PORF 0
2037+#define EXTRF 1
2038+#define BORF 2
2039+#define WDRF 3
2040+
2041+/* Reserved [0x34] */
2042+
2043+#define MCUCR _SFR_IO8(0x35)
2044+#define PUD 4
2045+#define BODS 5
2046+#define BODSE 6
2047+
2048+/* Reserved [0x36] */
2049+
2050+#define SPMCSR _SFR_IO8(0x37)
2051+#define SPMEN 0
2052+#define PGERS 1
2053+#define PGWRT 2
2054+#define RFLB 3
2055+#define CTPB 4
2056+#define SIGRD 5
2057+#define RWWSB 6
2058+
2059+/* Reserved [0x38..0x3C] */
2060+
2061+/* SP [0x3D..0x3E] */
2062+
2063+/* SREG [0x3F] */
2064+
2065+#define WDTCR _SFR_MEM8(0x60)
2066+#define WDE 3
2067+#define WDCE 4
2068+#define WDP0 0
2069+#define WDP1 1
2070+#define WDP2 2
2071+#define WDP3 5
2072+#define WDIE 6
2073+#define WDIF 7
2074+
2075+#define CLKPR _SFR_MEM8(0x61)
2076+#define CLKPS0 0
2077+#define CLKPS1 1
2078+#define CLKPS2 2
2079+#define CLKPS3 3
2080+#define CLKPCE 7
2081+
2082+#define CLKCSR _SFR_MEM8(0x62)
2083+#define CLKC0 0
2084+#define CLKC1 1
2085+#define CLKC2 2
2086+#define CLKC3 3
2087+#define CLKRDY 4
2088+#define CLKCCE 7
2089+
2090+#define CLKSELR _SFR_MEM8(0x63)
2091+#define CSEL0 0
2092+#define CSEL1 1
2093+#define CSEL2 2
2094+#define CSEL3 3
2095+#define CSUT0 4
2096+#define CSUT1 5
2097+#define COUT 6
2098+
2099+#define PRR _SFR_MEM8(0x64)
2100+#define PRADC 0
2101+#define PRUSI 1
2102+#define PRTIM0 2
2103+#define PRTIM1 3
2104+#define PRSPI 4
2105+#define PRLIN 5
2106+
2107+/* Reserved [0x65] */
2108+
2109+#define OSCCAL _SFR_MEM8(0x66)
2110+
2111+/* Reserved [0x67] */
2112+
2113+#define PCICR _SFR_MEM8(0x68)
2114+#define PCIE0 0
2115+#define PCIE1 1
2116+
2117+#define EICRA _SFR_MEM8(0x69)
2118+#define ISC00 0
2119+#define ISC01 1
2120+#define ISC10 2
2121+#define ISC11 3
2122+
2123+/* Reserved [0x6A] */
2124+
2125+#define PCMSK0 _SFR_MEM8(0x6B)
2126+#define PCINT0 0
2127+#define PCINT1 1
2128+#define PCINT2 2
2129+#define PCINT3 3
2130+#define PCINT4 4
2131+#define PCINT5 5
2132+#define PCINT6 6
2133+#define PCINT7 7
2134+
2135+#define PCMSK1 _SFR_MEM8(0x6C)
2136+#define PCINT8 0
2137+#define PCINT9 1
2138+#define PCINT10 2
2139+#define PCINT11 3
2140+#define PCINT12 4
2141+#define PCINT13 5
2142+#define PCINT14 6
2143+#define PCINT15 7
2144+
2145+/* Reserved [0x6D] */
2146+
2147+#define TIMSK0 _SFR_MEM8(0x6E)
2148+#define TOIE0 0
2149+#define OCIE0A 1
2150+
2151+#define TIMSK1 _SFR_MEM8(0x6F)
2152+#define TOIE1 0
2153+#define OCIE1A 1
2154+#define OCIE1B 2
2155+#define ICIE1 5
2156+
2157+/* Reserved [0x70..0x76] */
2158+
2159+#define AMISCR _SFR_MEM8(0x77)
2160+#define XREFEN 1
2161+#define AREFEN 2
2162+#define ISRCEN 0
2163+
2164+/* Combine ADCL and ADCH */
2165+#ifndef __ASSEMBLER__
2166+#define ADC _SFR_MEM16(0x78)
2167+#endif
2168+#define ADCW _SFR_MEM16(0x78)
2169+
2170+#define ADCL _SFR_MEM8(0x78)
2171+#define ADCH _SFR_MEM8(0x79)
2172+
2173+#define ADCSRA _SFR_MEM8(0x7A)
2174+#define ADPS0 0
2175+#define ADPS1 1
2176+#define ADPS2 2
2177+#define ADIE 3
2178+#define ADIF 4
2179+#define ADATE 5
2180+#define ADSC 6
2181+#define ADEN 7
2182+
2183+#define ADCSRB _SFR_MEM8(0x7B)
2184+#define ADTS0 0
2185+#define ADTS1 1
2186+#define ADTS2 2
2187+#define BIN 7
2188+#define ACIR0 4
2189+#define ACIR1 5
2190+#define ACME 6
2191+
2192+#define ADMUX _SFR_MEM8(0x7C)
2193+#define MUX0 0
2194+#define MUX1 1
2195+#define MUX2 2
2196+#define MUX3 3
2197+#define MUX4 4
2198+#define ADLAR 5
2199+#define REFS0 6
2200+#define REFS1 7
2201+
2202+/* Reserved [0x7D] */
2203+
2204+#define DIDR0 _SFR_MEM8(0x7E)
2205+#define ADC0D 0
2206+#define ADC1D 1
2207+#define ADC2D 2
2208+#define ADC3D 3
2209+#define ADC4D 4
2210+#define ADC5D 5
2211+#define ADC6D 6
2212+#define ADC7D 7
2213+
2214+#define DIDR1 _SFR_MEM8(0x7F)
2215+#define ADC8D 0
2216+#define ADC9D 1
2217+#define ADC10D 2
2218+
2219+#define TCCR1A _SFR_MEM8(0x80)
2220+#define WGM10 0
2221+#define WGM11 1
2222+#define COM1B0 4
2223+#define COM1B1 5
2224+#define COM1A0 6
2225+#define COM1A1 7
2226+
2227+#define TCCR1B _SFR_MEM8(0x81)
2228+#define CS10 0
2229+#define CS11 1
2230+#define CS12 2
2231+#define WGM12 3
2232+#define WGM13 4
2233+#define ICES1 6
2234+#define ICNC1 7
2235+
2236+#define TCCR1C _SFR_MEM8(0x82)
2237+#define FOC1B 6
2238+#define FOC1A 7
2239+
2240+#define TCCR1D _SFR_MEM8(0x83)
2241+#define OC1AU 0
2242+#define OC1AV 1
2243+#define OC1AW 2
2244+#define OC1AX 3
2245+#define OC1BU 4
2246+#define OC1BV 5
2247+#define OC1BW 6
2248+#define OC1BX 7
2249+
2250+/* Combine TCNT1L and TCNT1H */
2251+#define TCNT1 _SFR_MEM16(0x84)
2252+
2253+#define TCNT1L _SFR_MEM8(0x84)
2254+#define TCNT1H _SFR_MEM8(0x85)
2255+
2256+/* Combine ICR1L and ICR1H */
2257+#define ICR1 _SFR_MEM16(0x86)
2258+
2259+#define ICR1L _SFR_MEM8(0x86)
2260+#define ICR1H _SFR_MEM8(0x87)
2261+
2262+/* Combine OCR1AL and OCR1AH */
2263+#define OCR1A _SFR_MEM16(0x88)
2264+
2265+#define OCR1AL _SFR_MEM8(0x88)
2266+#define OCR1AH _SFR_MEM8(0x89)
2267+
2268+/* Combine OCR1BL and OCR1BH */
2269+#define OCR1B _SFR_MEM16(0x8A)
2270+
2271+#define OCR1BL _SFR_MEM8(0x8A)
2272+#define OCR1BH _SFR_MEM8(0x8B)
2273+
2274+/* Reserved [0x8C..0xB5] */
2275+
2276+#define ASSR _SFR_MEM8(0xB6)
2277+#define TCR0BUB 0
2278+#define TCR0AUB 1
2279+#define OCR0AUB 3
2280+#define TCN0UB 4
2281+#define AS0 5
2282+#define EXCLK 6
2283+
2284+/* Reserved [0xB7] */
2285+
2286+#define USICR _SFR_MEM8(0xB8)
2287+#define USITC 0
2288+#define USICLK 1
2289+#define USICS0 2
2290+#define USICS1 3
2291+#define USIWM0 4
2292+#define USIWM1 5
2293+#define USIOIE 6
2294+#define USISIE 7
2295+
2296+#define USISR _SFR_MEM8(0xB9)
2297+#define USICNT0 0
2298+#define USICNT1 1
2299+#define USICNT2 2
2300+#define USICNT3 3
2301+#define USIDC 4
2302+#define USIPF 5
2303+#define USIOIF 6
2304+#define USISIF 7
2305+
2306+#define USIDR _SFR_MEM8(0xBA)
2307+
2308+#define USIBR _SFR_MEM8(0xBB)
2309+
2310+#define USIPP _SFR_MEM8(0xBC)
2311+
2312+/* Reserved [0xBD..0xC7] */
2313+
2314+#define LINCR _SFR_MEM8(0xC8)
2315+#define LCMD0 0
2316+#define LCMD1 1
2317+#define LCMD2 2
2318+#define LENA 3
2319+#define LCONF0 4
2320+#define LCONF1 5
2321+#define LIN13 6
2322+#define LSWRES 7
2323+
2324+#define LINSIR _SFR_MEM8(0xC9)
2325+#define LRXOK 0
2326+#define LTXOK 1
2327+#define LIDOK 2
2328+#define LERR 3
2329+#define LBUSY 4
2330+#define LIDST0 5
2331+#define LIDST1 6
2332+#define LIDST2 7
2333+
2334+#define LINENIR _SFR_MEM8(0xCA)
2335+#define LENRXOK 0
2336+#define LENTXOK 1
2337+#define LENIDOK 2
2338+#define LENERR 3
2339+
2340+#define LINERR _SFR_MEM8(0xCB)
2341+#define LBERR 0
2342+#define LCERR 1
2343+#define LPERR 2
2344+#define LSERR 3
2345+#define LFERR 4
2346+#define LOVERR 5
2347+#define LTOERR 6
2348+#define LABORT 7
2349+
2350+#define LINBTR _SFR_MEM8(0xCC)
2351+#define LBT0 0
2352+#define LBT1 1
2353+#define LBT2 2
2354+#define LBT3 3
2355+#define LBT4 4
2356+#define LBT5 5
2357+#define LDISR 7
2358+
2359+#define LINBRRL _SFR_MEM8(0xCD)
2360+#define LDIV0 0
2361+#define LDIV1 1
2362+#define LDIV2 2
2363+#define LDIV3 3
2364+#define LDIV4 4
2365+#define LDIV5 5
2366+#define LDIV6 6
2367+#define LDIV7 7
2368+
2369+#define LINBRRH _SFR_MEM8(0xCE)
2370+#define LDIV8 0
2371+#define LDIV9 1
2372+#define LDIV10 2
2373+#define LDIV11 3
2374+
2375+#define LINDLR _SFR_MEM8(0xCF)
2376+#define LRXDL0 0
2377+#define LRXDL1 1
2378+#define LRXDL2 2
2379+#define LRXDL3 3
2380+#define LTXDL0 4
2381+#define LTXDL1 5
2382+#define LTXDL2 6
2383+#define LTXDL3 7
2384+
2385+#define LINIDR _SFR_MEM8(0xD0)
2386+#define LID0 0
2387+#define LID1 1
2388+#define LID2 2
2389+#define LID3 3
2390+#define LID4 4
2391+#define LID5 5
2392+#define LP0 6
2393+#define LP1 7
2394+
2395+#define LINSEL _SFR_MEM8(0xD1)
2396+#define LINDX0 0
2397+#define LINDX1 1
2398+#define LINDX2 2
2399+#define LAINC 3
2400+
2401+#define LINDAT _SFR_MEM8(0xD2)
2402+#define LDATA0 0
2403+#define LDATA1 1
2404+#define LDATA2 2
2405+#define LDATA3 3
2406+#define LDATA4 4
2407+#define LDATA5 5
2408+#define LDATA6 6
2409+#define LDATA7 7
2410+
2411+
2412+
2413+/* Interrupt vectors */
2414+/* Vector 0 is the reset vector */
2415+/* External Interrupt Request 0 */
2416+#define INT0_vect _VECTOR(1)
2417+#define INT0_vect_num 1
2418+
2419+/* External Interrupt Request 1 */
2420+#define INT1_vect _VECTOR(2)
2421+#define INT1_vect_num 2
2422+
2423+/* Pin Change Interrupt Request 0 */
2424+#define PCINT0_vect _VECTOR(3)
2425+#define PCINT0_vect_num 3
2426+
2427+/* Pin Change Interrupt Request 1 */
2428+#define PCINT1_vect _VECTOR(4)
2429+#define PCINT1_vect_num 4
2430+
2431+/* Watchdog Time-Out Interrupt */
2432+#define WDT_vect _VECTOR(5)
2433+#define WDT_vect_num 5
2434+
2435+/* Timer/Counter1 Capture Event */
2436+#define TIMER1_CAPT_vect _VECTOR(6)
2437+#define TIMER1_CAPT_vect_num 6
2438+
2439+/* Timer/Counter1 Compare Match 1A */
2440+#define TIMER1_COMPA_vect _VECTOR(7)
2441+#define TIMER1_COMPA_vect_num 7
2442+
2443+/* Timer/Counter1 Compare Match 1B */
2444+#define TIMER1_COMPB_vect _VECTOR(8)
2445+#define TIMER1_COMPB_vect_num 8
2446+
2447+/* Timer/Counter1 Overflow */
2448+#define TIMER1_OVF_vect _VECTOR(9)
2449+#define TIMER1_OVF_vect_num 9
2450+
2451+/* Timer/Counter0 Compare Match 0A */
2452+#define TIMER0_COMPA_vect _VECTOR(10)
2453+#define TIMER0_COMPA_vect_num 10
2454+
2455+/* Timer/Counter0 Overflow */
2456+#define TIMER0_OVF_vect _VECTOR(11)
2457+#define TIMER0_OVF_vect_num 11
2458+
2459+/* LIN Transfer Complete */
2460+#define LIN_TC_vect _VECTOR(12)
2461+#define LIN_TC_vect_num 12
2462+
2463+/* LIN Error */
2464+#define LIN_ERR_vect _VECTOR(13)
2465+#define LIN_ERR_vect_num 13
2466+
2467+/* SPI Serial Transfer Complete */
2468+#define SPI_STC_vect _VECTOR(14)
2469+#define SPI_STC_vect_num 14
2470+
2471+/* ADC Conversion Complete */
2472+#define ADC_vect _VECTOR(15)
2473+#define ADC_vect_num 15
2474+
2475+/* EEPROM Ready */
2476+#define EE_RDY_vect _VECTOR(16)
2477+#define EE_RDY_vect_num 16
2478+
2479+/* Analog Comparator */
2480+#define ANA_COMP_vect _VECTOR(17)
2481+#define ANA_COMP_vect_num 17
2482+
2483+/* USI Start */
2484+#define USI_START_vect _VECTOR(18)
2485+#define USI_START_vect_num 18
2486+
2487+/* USI Overflow */
2488+#define USI_OVF_vect _VECTOR(19)
2489+#define USI_OVF_vect_num 19
2490+
2491+#define _VECTORS_SIZE 80
2492+
2493+
2494+/* Constants */
2495+
2496+#define SPM_PAGESIZE 128
2497+#define FLASHEND 0x3FFF
2498+#define RAMSTART 0x0100
2499+#define RAMSIZE 512
2500+#define RAMEND 0x02FF
2501+#define E2START 0
2502+#define E2SIZE 512
2503+#define E2PAGESIZE 4
2504+#define E2END 0x01FF
2505+#define XRAMEND RAMEND
2506+
2507+
2508+/* Fuses */
2509+
2510+#define FUSE_MEMORY_SIZE 3
2511+
2512+/* Low Fuse Byte */
2513+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
2514+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
2515+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
2516+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
2517+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
2518+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
2519+#define FUSE_CKOUT (unsigned char)~_BV(6)
2520+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
2521+
2522+/* High Fuse Byte */
2523+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
2524+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
2525+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
2526+#define FUSE_EESAVE (unsigned char)~_BV(3)
2527+#define FUSE_WDTON (unsigned char)~_BV(4)
2528+#define FUSE_SPIEN (unsigned char)~_BV(5)
2529+#define FUSE_DWEN (unsigned char)~_BV(6)
2530+#define FUSE_RSTDISBL (unsigned char)~_BV(7)
2531+
2532+/* Extended Fuse Byte */
2533+#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
2534+
2535+
2536+/* Lock Bits */
2537+#define __LOCK_BITS_EXIST
2538+
2539+
2540+/* Signature */
2541+#define SIGNATURE_0 0x1E
2542+#define SIGNATURE_1 0x94
2543+#define SIGNATURE_2 0x87
2544+
2545+
2546+#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */
2547+
2548diff -urN avr-libc-1.8.0.orig/include/avr/ioa5790.h avr-libc-1.8.0/include/avr/ioa5790.h
2549--- avr-libc-1.8.0.orig/include/avr/ioa5790.h 1970-01-01 01:00:00.000000000 +0100
2550+++ avr-libc-1.8.0/include/avr/ioa5790.h 2013-01-18 09:50:25.000000000 +0100
2551@@ -0,0 +1,833 @@
2552+/*****************************************************************************
2553+ *
2554+ * Copyright (C) 2012 Atmel Corporation
2555+ * All rights reserved.
2556+ *
2557+ * Redistribution and use in source and binary forms, with or without
2558+ * modification, are permitted provided that the following conditions are met:
2559+ *
2560+ * * Redistributions of source code must retain the above copyright
2561+ * notice, this list of conditions and the following disclaimer.
2562+ *
2563+ * * Redistributions in binary form must reproduce the above copyright
2564+ * notice, this list of conditions and the following disclaimer in
2565+ * the documentation and/or other materials provided with the
2566+ * distribution.
2567+ *
2568+ * * Neither the name of the copyright holders nor the names of
2569+ * contributors may be used to endorse or promote products derived
2570+ * from this software without specific prior written permission.
2571+ *
2572+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2573+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2574+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2575+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
2576+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2577+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2578+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2579+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2580+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2581+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2582+ * POSSIBILITY OF SUCH DAMAGE.
2583+ ****************************************************************************/
2584+
2585+
2586+#ifndef _AVR_ATA5790_H_INCLUDED
2587+#define _AVR_ATA5790_H_INCLUDED
2588+
2589+
2590+#ifndef _AVR_IO_H_
2591+# error "Include <avr/io.h> instead of this file."
2592+#endif
2593+
2594+#ifndef _AVR_IOXXX_H_
2595+# define _AVR_IOXXX_H_ "ioa5790.h"
2596+#else
2597+# error "Attempt to include more than one <avr/ioXXX.h> file."
2598+#endif
2599+
2600+/* Registers and associated bit numbers */
2601+
2602+#define PINB _SFR_IO8(0x03)
2603+#define PINB7 7
2604+#define PINB6 6
2605+#define PINB5 5
2606+#define PINB4 4
2607+#define PINB3 3
2608+#define PINB2 2
2609+#define PINB1 1
2610+#define PINB0 0
2611+
2612+#define DDRB _SFR_IO8(0x04)
2613+#define DDRB7 7
2614+#define DDRB6 6
2615+#define DDRB5 5
2616+#define DDRB4 4
2617+#define DDRB3 3
2618+#define DDRB2 2
2619+#define DDRB1 1
2620+#define DDRB0 0
2621+
2622+#define PORTB _SFR_IO8(0x05)
2623+#define PORTB7 7
2624+#define PORTB6 6
2625+#define PORTB5 5
2626+#define PORTB4 4
2627+#define PORTB3 3
2628+#define PORTB2 2
2629+#define PORTB1 1
2630+#define PORTB0 0
2631+
2632+#define PINC _SFR_IO8(0x06)
2633+#define PINC7 7
2634+#define PINC6 6
2635+#define PINC5 5
2636+#define PINC4 4
2637+#define PINC3 3
2638+#define PINC2 2
2639+#define PINC1 1
2640+#define PINC0 0
2641+
2642+#define DDRC _SFR_IO8(0x07)
2643+#define DDRC7 7
2644+#define DDRC6 6
2645+#define DDRC5 5
2646+#define DDRC4 4
2647+#define DDRC3 3
2648+#define DDRC2 2
2649+#define DDRC1 1
2650+#define DDRC0 0
2651+
2652+#define PORTC _SFR_IO8(0x08)
2653+#define PORTC7 7
2654+#define PORTC6 6
2655+#define PORTC5 5
2656+#define PORTC4 4
2657+#define PORTC3 3
2658+#define PORTC2 2
2659+#define PORTC1 1
2660+#define PORTC0 0
2661+
2662+#define PIND _SFR_IO8(0x09)
2663+#define PIND7 7
2664+#define PIND6 6
2665+#define PIND5 5
2666+#define PIND4 4
2667+#define PIND3 3
2668+#define PIND2 2
2669+#define PIND1 1
2670+#define PIND0 0
2671+
2672+#define DDRD _SFR_IO8(0x0A)
2673+#define DDRD7 7
2674+#define DDRD6 6
2675+#define DDRD5 5
2676+#define DDRD4 4
2677+#define DDRD3 3
2678+#define DDRD2 2
2679+#define DDRD1 1
2680+#define DDRD0 0
2681+
2682+#define PORTD _SFR_IO8(0x0B)
2683+#define PORTD7 7
2684+#define PORTD6 6
2685+#define PORTD5 5
2686+#define PORTD4 4
2687+#define PORTD3 3
2688+#define PORTD2 2
2689+#define PORTD1 1
2690+#define PORTD0 0
2691+
2692+/* Reserved [0x0C] */
2693+
2694+#define TPCR _SFR_IO8(0x0D)
2695+#define TPMA 0
2696+#define TPMOD 1
2697+#define TPMS0 2
2698+#define TPMS1 3
2699+#define TPMD0 4
2700+#define TPMD1 5
2701+#define TPPSD 6
2702+#define TPD 7
2703+
2704+#define TPFR _SFR_IO8(0x0E)
2705+#define TPF 0
2706+#define TPA 1
2707+#define TPGAP 2
2708+#define TPPSW 3
2709+
2710+#define CMCR _SFR_IO8(0x0F)
2711+#define CMM0 0
2712+#define CMM1 1
2713+#define SRCD 2
2714+#define CO32D 3
2715+#define CCS 4
2716+#define ECINS 5
2717+#define CMONEN 6
2718+#define CMCCE 7
2719+
2720+#define CMSR _SFR_IO8(0x10)
2721+#define ECF 0
2722+#define SXF 1
2723+#define RTCF 2
2724+
2725+#define T2CR _SFR_IO8(0x11)
2726+#define T2OTM 0
2727+#define T2CTM 1
2728+#define T2CRM 2
2729+#define T2GRM 3
2730+#define T2TOP 4
2731+#define T2RES 5
2732+#define T2TS 6
2733+#define T2E 7
2734+
2735+#define T3CR _SFR_IO8(0x12)
2736+#define T3OTM 0
2737+#define T3CTM 1
2738+#define T3CRM 2
2739+#define T3CPRM 3
2740+#define T3TOP 4
2741+#define T3RES 5
2742+#define T3CPTM 6
2743+#define T3E 7
2744+
2745+#define AESCR _SFR_IO8(0x13)
2746+#define AESWK 0
2747+#define AESWD 1
2748+#define AESIM 2
2749+#define AESD 3
2750+#define AESXOR 4
2751+#define AESRES 5
2752+#define AESE 7
2753+
2754+#define AESSR _SFR_IO8(0x14)
2755+#define AESRF 0
2756+#define AESERF 7
2757+
2758+#define TMIFR _SFR_IO8(0x15)
2759+#define TMRXF 0
2760+#define TMTXF 1
2761+#define TMTCF 2
2762+#define TMRXS 3
2763+#define TMTXS 4
2764+
2765+#define VMSR _SFR_IO8(0x16)
2766+#define VMF 0
2767+
2768+#define PCIFR _SFR_IO8(0x17)
2769+#define PCIF0 0
2770+#define PCIF1 1
2771+
2772+#define LFFR _SFR_IO8(0x18)
2773+#define LFID0F 0
2774+#define LFID1F 1
2775+#define LFFEF 2
2776+#define LFDBF 3
2777+#define LFRSF 4
2778+#define LFSDF 5
2779+#define LFMDF 6
2780+#define LFCAF 7
2781+
2782+#define T0IFR _SFR_IO8(0x19)
2783+#define T0F 0
2784+
2785+#define T1IFR _SFR_IO8(0x1A)
2786+#define T1F 0
2787+
2788+#define T2IFR _SFR_IO8(0x1B)
2789+#define T2OFF 0
2790+#define T2COF 1
2791+
2792+#define T3IFR _SFR_IO8(0x1C)
2793+#define T3OFF 0
2794+#define T3COF 1
2795+#define T3ICF 2
2796+
2797+#define EIFR _SFR_IO8(0x1D)
2798+#define INTF0 0
2799+
2800+#define GPIOR _SFR_IO8(0x1E)
2801+
2802+#define EECR _SFR_IO8(0x1F)
2803+#define EERE 0
2804+#define EEWE 1
2805+#define EEMWE 2
2806+#define EERIE 3
2807+#define EEPM0 4
2808+#define EEPM1 5
2809+#define EELP 6
2810+
2811+#define EEDR _SFR_IO8(0x20)
2812+
2813+/* Combine EEARL and EEARH */
2814+#define EEAR _SFR_IO16(0x21)
2815+
2816+#define EEARL _SFR_IO8(0x21)
2817+#define EEARH _SFR_IO8(0x22)
2818+
2819+#define EEPR _SFR_IO8(0x23)
2820+#define EEAP0 0
2821+#define EEAP1 1
2822+#define EEAP2 2
2823+#define EEAP3 3
2824+
2825+#define EECCR _SFR_IO8(0x24)
2826+#define EEL0 0
2827+#define EEL1 1
2828+#define EEL2 2
2829+#define EEL3 3
2830+
2831+/* Reserved [0x25] */
2832+
2833+#define PCICR _SFR_IO8(0x26)
2834+#define PCIE0 0
2835+#define PCIE1 1
2836+
2837+#define EIMSK _SFR_IO8(0x27)
2838+#define INT0 0
2839+
2840+#define TMDR _SFR_IO8(0x28)
2841+
2842+#define AESDR _SFR_IO8(0x29)
2843+
2844+#define AESKR _SFR_IO8(0x2A)
2845+#define AESKR0 0
2846+#define AESKR1 1
2847+#define AESKR2 2
2848+#define AESKR3 3
2849+#define AESKR4 4
2850+#define AESKR5 5
2851+#define AESKR6 6
2852+#define AESKR7 7
2853+
2854+#define VMCR _SFR_IO8(0x2B)
2855+#define VMLS0 0
2856+#define VMLS1 1
2857+#define VMLS2 2
2858+#define VMLS3 3
2859+#define VMIM 4
2860+#define VMPS 5
2861+#define BODPD 6
2862+#define BODLS 7
2863+
2864+#define SPCR _SFR_IO8(0x2C)
2865+#define SPR0 0
2866+#define SPR1 1
2867+#define CPHA 2
2868+#define CPOL 3
2869+#define MSTR 4
2870+#define DORD 5
2871+#define SPE 6
2872+#define SPIE 7
2873+
2874+#define SPSR _SFR_IO8(0x2D)
2875+#define SPI2X 0
2876+#define WCOL 6
2877+#define SPIF 7
2878+
2879+#define SPDR _SFR_IO8(0x2E)
2880+
2881+#define LFCR0 _SFR_IO8(0x2F)
2882+#define LFCE1 0
2883+#define LFCE2 1
2884+#define LFCE3 2
2885+#define LFBRS 3
2886+#define LFRBS 4
2887+#define LFMG 5
2888+#define LFVC0 6
2889+#define LFVC1 7
2890+
2891+#define LFCR1 _SFR_IO8(0x30)
2892+#define LFM0 0
2893+#define LFM1 1
2894+#define LFFM0 2
2895+#define LFFM1 3
2896+#define LFRMS 4
2897+#define LFRMSA 5
2898+#define LFQCE 6
2899+#define LFRE 7
2900+
2901+/* Reserved [0x31] */
2902+
2903+#define LFRDB _SFR_IO8(0x32)
2904+
2905+#define SMCR _SFR_IO8(0x33)
2906+#define SE 0
2907+#define SM0 1
2908+#define SM1 2
2909+#define SM2 3
2910+
2911+#define MCUSR _SFR_IO8(0x34)
2912+#define PORF 0
2913+#define EXTRF 1
2914+#define BORF 2
2915+#define WDRF 3
2916+#define TPRF 5
2917+
2918+#define MCUCR _SFR_IO8(0x35)
2919+#define IVCE 0
2920+#define IVSEL 1
2921+#define PUD 4
2922+
2923+#define LFSR _SFR_IO8(0x36)
2924+#define LFES 0
2925+#define LFSD 1
2926+
2927+#define SPMCSR _SFR_IO8(0x37)
2928+#define SPMEN 0
2929+#define PGERS 1
2930+#define PGWRT 2
2931+#define BLBSET 3
2932+#define RWWSRE 4
2933+#define SIGRD 5
2934+#define RWWSB 6
2935+#define SPMIE 7
2936+
2937+#define T1CR _SFR_IO8(0x38)
2938+#define T1PS0 0
2939+#define T1PS1 1
2940+#define T1IE 2
2941+#define T1CS0 3
2942+#define T1CS1 4
2943+#define T1E 7
2944+
2945+#define T0CR _SFR_IO8(0x39)
2946+#define T0PS0 0
2947+#define T0PS1 1
2948+#define T0PS2 2
2949+#define T0IE 3
2950+#define T0PR 4
2951+
2952+/* Reserved [0x3A] */
2953+
2954+#define CMIMR _SFR_IO8(0x3B)
2955+#define ECIE 0
2956+#define SXIE 1
2957+#define RTCIE 2
2958+
2959+#define CLKPR _SFR_IO8(0x3C)
2960+#define CLKPS0 0
2961+#define CLKPS1 1
2962+#define CLKPS2 2
2963+#define CLTPS0 3
2964+#define CLTPS1 4
2965+#define CLTPS2 5
2966+#define CLKPCE 7
2967+
2968+/* SP [0x3D..0x3E] */
2969+
2970+/* SREG [0x3F] */
2971+
2972+#define WDTCR _SFR_MEM8(0x60)
2973+#define WDPS0 0
2974+#define WDPS1 1
2975+#define WDPS2 2
2976+#define WDE 3
2977+#define WDCE 4
2978+
2979+/* Reserved [0x61..0x62] */
2980+
2981+#define PRR0 _SFR_MEM8(0x63)
2982+#define PRLFR 0
2983+#define PRT1 1
2984+#define PRT2 2
2985+#define PRT3 3
2986+#define PRTM 4
2987+#define PRCU 5
2988+#define PRDS 6
2989+#define PRVM 7
2990+
2991+#define PRR1 _SFR_MEM8(0x64)
2992+#define PRCI 0
2993+#define PRSPI 1
2994+
2995+#define SRCCAL _SFR_MEM8(0x65)
2996+
2997+#define FRCCAL _SFR_MEM8(0x66)
2998+
2999+/* Reserved [0x67..0x68] */
3000+
3001+#define EICRA _SFR_MEM8(0x69)
3002+#define ISC00 0
3003+#define ISC01 1
3004+
3005+#define PCMSK0 _SFR_MEM8(0x6A)
3006+#define PCINT0 0
3007+#define PCINT1 1
3008+#define PCINT2 2
3009+#define PCINT3 3
3010+#define PCINT4 4
3011+#define PCINT5 5
3012+#define PCINT6 6
3013+#define PCINT7 7
3014+
3015+#define PCMSK1 _SFR_MEM8(0x6B)
3016+#define PCINT8 0
3017+#define PCINT9 1
3018+#define PCINT10 2
3019+#define PCINT11 3
3020+#define PCINT12 4
3021+#define PCINT13 5
3022+#define PCINT14 6
3023+#define PCINT15 7
3024+
3025+/* Reserved [0x6C] */
3026+
3027+#define LDCR _SFR_MEM8(0x6D)
3028+#define LDE 0
3029+#define LDCS0 1
3030+#define LDCS1 2
3031+
3032+/* Reserved [0x6E..0x6F] */
3033+
3034+#define T2CNT _SFR_MEM8(0x70)
3035+
3036+#define T2COR _SFR_MEM8(0x71)
3037+
3038+/* Reserved [0x72] */
3039+
3040+#define T2MR _SFR_MEM8(0x73)
3041+#define T2CS0 0
3042+#define T2CS1 1
3043+#define T2CS2 2
3044+#define T2PS0 3
3045+#define T2PS1 4
3046+#define T2PS2 5
3047+#define T2D0 6
3048+#define T2D1 7
3049+
3050+#define T2IMR _SFR_MEM8(0x74)
3051+#define T2OIM 0
3052+#define T2CIM 1
3053+
3054+/* Reserved [0x75] */
3055+
3056+#define T3CNT _SFR_MEM8(0x76)
3057+
3058+#define T3COR _SFR_MEM8(0x77)
3059+
3060+#define T3ICR _SFR_MEM8(0x78)
3061+
3062+#define T3MRA _SFR_MEM8(0x79)
3063+#define T3CS0 0
3064+#define T3CS1 1
3065+#define T3SCE 2
3066+#define T3CE0 3
3067+#define T3CE1 4
3068+#define T3CNC 5
3069+#define T3ICS0 6
3070+#define T3ICS1 7
3071+
3072+#define T3MRB _SFR_MEM8(0x7A)
3073+#define T3PS0 0
3074+#define T3PS1 1
3075+#define T3PS2 2
3076+
3077+#define T3IMR _SFR_MEM8(0x7B)
3078+#define T3OIM 0
3079+#define T3CIM 1
3080+#define T3CPIM 2
3081+
3082+/* Reserved [0x7C] */
3083+
3084+#define TMCR _SFR_MEM8(0x7D)
3085+#define MI1S0 0
3086+#define MI1S1 1
3087+#define MI2S0 2
3088+#define MI2S1 3
3089+#define MI4S0 4
3090+#define MI4S1 5
3091+#define TMCPOL 6
3092+#define TMSSIE 7
3093+
3094+#define TMMR _SFR_MEM8(0x7E)
3095+#define MOS0 0
3096+#define MOS1 1
3097+#define MSCS0 2
3098+#define MSCS1 3
3099+#define MOUTC 4
3100+#define TMMS0 5
3101+#define TMMS1 6
3102+#define TM12S 7
3103+
3104+#define TMIMR _SFR_MEM8(0x7F)
3105+#define TMRXIM 0
3106+#define TMTXIM 1
3107+#define TMTCIM 2
3108+
3109+/* Reserved [0x80..0x81] */
3110+
3111+#define LFIMR _SFR_MEM8(0x82)
3112+#define LFID0IM 0
3113+#define LFID1IM 1
3114+#define LFFEIM 2
3115+#define LFDBIM 3
3116+#define LFRSIM 4
3117+#define LFSDIM 5
3118+#define LFMDIM 6
3119+
3120+#define LFCAD _SFR_MEM8(0x83)
3121+
3122+#define LFID00 _SFR_MEM8(0x84)
3123+
3124+#define LFID01 _SFR_MEM8(0x85)
3125+
3126+#define LFID02 _SFR_MEM8(0x86)
3127+
3128+#define LFID03 _SFR_MEM8(0x87)
3129+
3130+#define LFID10 _SFR_MEM8(0x88)
3131+
3132+#define LFID11 _SFR_MEM8(0x89)
3133+
3134+#define LFID12 _SFR_MEM8(0x8A)
3135+
3136+#define LFID13 _SFR_MEM8(0x8B)
3137+
3138+#define LFRD0 _SFR_MEM8(0x8C)
3139+
3140+#define LFRD1 _SFR_MEM8(0x8D)
3141+
3142+#define LFRD2 _SFR_MEM8(0x8E)
3143+
3144+#define LFRD3 _SFR_MEM8(0x8F)
3145+
3146+#define LFID0M _SFR_MEM8(0x90)
3147+#define ID0FS0 0
3148+#define ID0FS1 1
3149+#define ID0FS2 2
3150+#define ID0FS3 3
3151+#define ID0FS4 4
3152+#define ID0E 7
3153+
3154+#define LFID1M _SFR_MEM8(0x91)
3155+#define ID1FS0 0
3156+#define ID1FS1 1
3157+#define ID1FS2 2
3158+#define ID1FS3 3
3159+#define ID1FS4 4
3160+#define ID1E 7
3161+
3162+#define LFRDF _SFR_MEM8(0x92)
3163+#define RDFS0 0
3164+#define RDFS1 1
3165+#define RDFS2 2
3166+#define RDFS3 3
3167+#define RDFS4 4
3168+#define RDFE 7
3169+
3170+#define LFRSD1 _SFR_MEM8(0x93)
3171+
3172+#define LFRSD2 _SFR_MEM8(0x94)
3173+
3174+#define LFRSD3 _SFR_MEM8(0x95)
3175+
3176+#define LFCC1 _SFR_MEM8(0x96)
3177+
3178+#define LFCC2 _SFR_MEM8(0x97)
3179+
3180+#define LFCC3 _SFR_MEM8(0x98)
3181+
3182+/* Reserved [0x99..0x9B] */
3183+
3184+#define TPIMR _SFR_MEM8(0x9C)
3185+#define TPIM 0
3186+
3187+/* Reserved [0x9D] */
3188+
3189+#define RTCCR _SFR_MEM8(0x9E)
3190+#define RTCR 0
3191+
3192+#define RTCDR _SFR_MEM8(0x9F)
3193+
3194+/* Reserved [0xA0..0xA7] */
3195+
3196+#define TMMDR _SFR_MEM8(0xA8)
3197+
3198+#define TMBDR _SFR_MEM8(0xA9)
3199+
3200+#define TMTDR _SFR_MEM8(0xAA)
3201+
3202+#define TMSR _SFR_MEM8(0xAB)
3203+
3204+/* Reserved [0xAC] */
3205+
3206+#define CRCDR _SFR_MEM8(0xAD)
3207+
3208+#define CRCCR _SFR_MEM8(0xAE)
3209+#define CRCN0 0
3210+#define CRCN1 1
3211+#define CRCN2 2
3212+#define CRCSEL 3
3213+#define REFLI 4
3214+#define REFLO 5
3215+#define CRCRS 7
3216+
3217+#define CRCSR _SFR_MEM8(0xAF)
3218+#define CRCBF 0
3219+
3220+
3221+
3222+/* Interrupt vectors */
3223+/* Vector 0 is the reset vector */
3224+/* Transponder Mode Interrupt */
3225+#define TPINT_vect _VECTOR(1)
3226+#define TPINT_vect_num 1
3227+
3228+/* External Interrupt Request 0 */
3229+#define INT0_vect _VECTOR(2)
3230+#define INT0_vect_num 2
3231+
3232+/* Pin Change Interrupt Request 0 */
3233+#define PCINT0_vect _VECTOR(3)
3234+#define PCINT0_vect_num 3
3235+
3236+/* Pin Change Interrupt Request 1 */
3237+#define PCINT1_vect _VECTOR(4)
3238+#define PCINT1_vect_num 4
3239+
3240+/* Voltage Monitoring Interrupt */
3241+#define VMINT_vect _VECTOR(5)
3242+#define VMINT_vect_num 5
3243+
3244+/* Timer0 Interval Interrupt */
3245+#define T0INT_vect _VECTOR(6)
3246+#define T0INT_vect_num 6
3247+
3248+/* LF-Receiver Identifier 0 Interrupt */
3249+#define LFID0INT_vect _VECTOR(7)
3250+#define LFID0INT_vect_num 7
3251+
3252+/* LF-Receiver Identifier 1 Interrupt */
3253+#define LFID1INT_vect _VECTOR(8)
3254+#define LFID1INT_vect_num 8
3255+
3256+/* LF-Receiver Frame End Interrupt */
3257+#define LFFEINT_vect _VECTOR(9)
3258+#define LFFEINT_vect_num 9
3259+
3260+/* LF-Receiver Data Buffer full Interrupt */
3261+#define LFDBINT_vect _VECTOR(10)
3262+#define LFDBINT_vect_num 10
3263+
3264+/* Timer/Counter3 Capture Event Interrupt */
3265+#define T3CAPINT_vect _VECTOR(11)
3266+#define T3CAPINT_vect_num 11
3267+
3268+/* Timer/Counter3 Compare Match Interrupt */
3269+#define T3COMINT_vect _VECTOR(12)
3270+#define T3COMINT_vect_num 12
3271+
3272+/* Timer/Counter3 Overflow Interrupt */
3273+#define T3OVFINT_vect _VECTOR(13)
3274+#define T3OVFINT_vect_num 13
3275+
3276+/* Timer/Counter2 Compare Match Interrupt */
3277+#define T2COMINT_vect _VECTOR(14)
3278+#define T2COMINT_vect_num 14
3279+
3280+/* Timer/Counter2 Overflow Interrupt */
3281+#define T2OVFINT_vect _VECTOR(15)
3282+#define T2OVFINT_vect_num 15
3283+
3284+/* Timer 1 Interval Interrupt */
3285+#define T1INT_vect _VECTOR(16)
3286+#define T1INT_vect_num 16
3287+
3288+/* SPI Serial Transfer Complete Interrupt */
3289+#define SPISTC_vect _VECTOR(17)
3290+#define SPISTC_vect_num 17
3291+
3292+/* Timer Modulator SSI Receive Buffer Interrupt */
3293+#define TMRXBINT_vect _VECTOR(18)
3294+#define TMRXBINT_vect_num 18
3295+
3296+/* Timer Modulator SSI Transmit Buffer Interrupt */
3297+#define TMTXBINT_vect _VECTOR(19)
3298+#define TMTXBINT_vect_num 19
3299+
3300+/* Timer Modulator Transmit Complete Interrupt */
3301+#define TMTXCINT_vect _VECTOR(20)
3302+#define TMTXCINT_vect_num 20
3303+
3304+/* AES Interrupt */
3305+#define AESINT_vect _VECTOR(21)
3306+#define AESINT_vect_num 21
3307+
3308+/* LF-Receiver RSSi measurement Interrupt */
3309+#define LFRSSINT_vect _VECTOR(22)
3310+#define LFRSSINT_vect_num 22
3311+
3312+/* LF-Receiver Signal Detect Interrupt */
3313+#define LFSDINT_vect _VECTOR(23)
3314+#define LFSDINT_vect_num 23
3315+
3316+/* LF-Receiver Manchester Decoder error Interrupt */
3317+#define LFMDINT_vect _VECTOR(24)
3318+#define LFMDINT_vect_num 24
3319+
3320+/* External Input Clock Monitoring Interrupt */
3321+#define EXCMINT_vect _VECTOR(25)
3322+#define EXCMINT_vect_num 25
3323+
3324+/* External XTAL Oscillator Break Down Interrupt */
3325+#define EXXMINT_vect _VECTOR(26)
3326+#define EXXMINT_vect_num 26
3327+
3328+/* Real Time Clock Interrupt */
3329+#define RTCINT_vect _VECTOR(27)
3330+#define RTCINT_vect_num 27
3331+
3332+/* EEPROM Ready Interrupt */
3333+#define EEREADY_vect _VECTOR(28)
3334+#define EEREADY_vect_num 28
3335+
3336+/* Store Program Memory Ready */
3337+#define SPMREADY_vect _VECTOR(29)
3338+#define SPMREADY_vect_num 29
3339+
3340+#define _VECTORS_SIZE 120
3341+
3342+
3343+/* Constants */
3344+
3345+#define SPM_PAGESIZE 128
3346+#define FLASHEND 0x3FFF
3347+#define RAMSTART 0x0100
3348+#define RAMSIZE 512
3349+#define RAMEND 0x02FF
3350+#define E2START 0
3351+#define E2SIZE 2048
3352+#define E2PAGESIZE 16
3353+#define E2END 0x07FF
3354+#define XRAMEND RAMEND
3355+
3356+
3357+/* Fuses */
3358+
3359+#define FUSE_MEMORY_SIZE 1
3360+
3361+/* Fuse Byte */
3362+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
3363+#define FUSE_DWEN (unsigned char)~_BV(64)
3364+#define FUSE_SPIEN (unsigned char)~_BV(32)
3365+#define FUSE_WDTON (unsigned char)~_BV(16)
3366+#define FUSE_EESAVE (unsigned char)~_BV(8)
3367+#define FUSE_Reserved (unsigned char)~_BV(4)
3368+#define FUSE__32OEN (unsigned char)~_BV(2)
3369+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
3370+
3371+/* Lock Bits */
3372+#define __LOCK_BITS_EXIST
3373+#define __BOOT_LOCK_BITS_0_EXIST
3374+#define __BOOT_LOCK_BITS_1_EXIST
3375+
3376+
3377+/* Signature */
3378+#define SIGNATURE_0 0x1E
3379+#define SIGNATURE_1 0x94
3380+#define SIGNATURE_2 0x61
3381+
3382+
3383+#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */
3384+
3385diff -urN avr-libc-1.8.0.orig/include/avr/ioa5795.h avr-libc-1.8.0/include/avr/ioa5795.h
3386--- avr-libc-1.8.0.orig/include/avr/ioa5795.h 1970-01-01 01:00:00.000000000 +0100
3387+++ avr-libc-1.8.0/include/avr/ioa5795.h 2013-01-18 09:50:25.000000000 +0100
3388@@ -0,0 +1,699 @@
3389+/*****************************************************************************
3390+ *
3391+ * Copyright (C) 2012 Atmel Corporation
3392+ * All rights reserved.
3393+ *
3394+ * Redistribution and use in source and binary forms, with or without
3395+ * modification, are permitted provided that the following conditions are met:
3396+ *
3397+ * * Redistributions of source code must retain the above copyright
3398+ * notice, this list of conditions and the following disclaimer.
3399+ *
3400+ * * Redistributions in binary form must reproduce the above copyright
3401+ * notice, this list of conditions and the following disclaimer in
3402+ * the documentation and/or other materials provided with the
3403+ * distribution.
3404+ *
3405+ * * Neither the name of the copyright holders nor the names of
3406+ * contributors may be used to endorse or promote products derived
3407+ * from this software without specific prior written permission.
3408+ *
3409+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
3410+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3411+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
3412+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
3413+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
3414+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
3415+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
3416+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
3417+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3418+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
3419+ * POSSIBILITY OF SUCH DAMAGE.
3420+ ****************************************************************************/
3421+
3422+
3423+#ifndef _AVR_ATA5795_H_INCLUDED
3424+#define _AVR_ATA5795_H_INCLUDED
3425+
3426+
3427+#ifndef _AVR_IO_H_
3428+# error "Include <avr/io.h> instead of this file."
3429+#endif
3430+
3431+#ifndef _AVR_IOXXX_H_
3432+# define _AVR_IOXXX_H_ "ioa5795.h"
3433+#else
3434+# error "Attempt to include more than one <avr/ioXXX.h> file."
3435+#endif
3436+
3437+/* Registers and associated bit numbers */
3438+
3439+#define PINB _SFR_IO8(0x03)
3440+#define PINB7 7
3441+#define PINB6 6
3442+#define PINB5 5
3443+#define PINB4 4
3444+#define PINB3 3
3445+#define PINB2 2
3446+#define PINB1 1
3447+#define PINB0 0
3448+
3449+#define DDRB _SFR_IO8(0x04)
3450+#define DDRB7 7
3451+#define DDRB6 6
3452+#define DDRB5 5
3453+#define DDRB4 4
3454+#define DDRB3 3
3455+#define DDRB2 2
3456+#define DDRB1 1
3457+#define DDRB0 0
3458+
3459+#define PORTB _SFR_IO8(0x05)
3460+#define PORTB7 7
3461+#define PORTB6 6
3462+#define PORTB5 5
3463+#define PORTB4 4
3464+#define PORTB3 3
3465+#define PORTB2 2
3466+#define PORTB1 1
3467+#define PORTB0 0
3468+
3469+#define PINC _SFR_IO8(0x06)
3470+#define PINC7 7
3471+#define PINC6 6
3472+#define PINC5 5
3473+#define PINC4 4
3474+#define PINC3 3
3475+#define PINC2 2
3476+#define PINC1 1
3477+#define PINC0 0
3478+
3479+#define DDRC _SFR_IO8(0x07)
3480+#define DDRC7 7
3481+#define DDRC6 6
3482+#define DDRC5 5
3483+#define DDRC4 4
3484+#define DDRC3 3
3485+#define DDRC2 2
3486+#define DDRC1 1
3487+#define DDRC0 0
3488+
3489+#define PORTC _SFR_IO8(0x08)
3490+#define PORTC7 7
3491+#define PORTC6 6
3492+#define PORTC5 5
3493+#define PORTC4 4
3494+#define PORTC3 3
3495+#define PORTC2 2
3496+#define PORTC1 1
3497+#define PORTC0 0
3498+
3499+#define PIND _SFR_IO8(0x09)
3500+#define PIND7 7
3501+#define PIND6 6
3502+#define PIND5 5
3503+#define PIND4 4
3504+#define PIND3 3
3505+#define PIND2 2
3506+#define PIND1 1
3507+#define PIND0 0
3508+
3509+#define DDRD _SFR_IO8(0x0A)
3510+#define DDRD7 7
3511+#define DDRD6 6
3512+#define DDRD5 5
3513+#define DDRD4 4
3514+#define DDRD3 3
3515+#define DDRD2 2
3516+#define DDRD1 1
3517+#define DDRD0 0
3518+
3519+#define PORTD _SFR_IO8(0x0B)
3520+#define PORTD7 7
3521+#define PORTD6 6
3522+#define PORTD5 5
3523+#define PORTD4 4
3524+#define PORTD3 3
3525+#define PORTD2 2
3526+#define PORTD1 1
3527+#define PORTD0 0
3528+
3529+/* Reserved [0x0C] */
3530+
3531+#define TPCR _SFR_IO8(0x0D)
3532+#define TPMA 0
3533+#define TPMOD 1
3534+#define TPMS0 2
3535+#define TPMS1 3
3536+#define TPMD0 4
3537+#define TPMD1 5
3538+#define TPPSD 6
3539+#define TPD 7
3540+
3541+#define TPFR _SFR_IO8(0x0E)
3542+#define TPF 0
3543+#define TPA 1
3544+#define TPGAP 2
3545+#define TPPSW 3
3546+
3547+#define CMCR _SFR_IO8(0x0F)
3548+#define CMM0 0
3549+#define CMM1 1
3550+#define SRCD 2
3551+#define CO32D 3
3552+#define CCS 4
3553+#define ECINS 5
3554+#define CMONEN 6
3555+#define CMCCE 7
3556+
3557+#define CMSR _SFR_IO8(0x10)
3558+#define ECF 0
3559+#define SXF 1
3560+#define RTCF 2
3561+
3562+#define T2CR _SFR_IO8(0x11)
3563+#define T2OTM 0
3564+#define T2CTM 1
3565+#define T2CRM 2
3566+#define T2GRM 3
3567+#define T2TOP 4
3568+#define T2RES 5
3569+#define T2TS 6
3570+#define T2E 7
3571+
3572+#define T3CR _SFR_IO8(0x12)
3573+#define T3OTM 0
3574+#define T3CTM 1
3575+#define T3CRM 2
3576+#define T3CPRM 3
3577+#define T3TOP 4
3578+#define T3RES 5
3579+#define T3CPTM 6
3580+#define T3E 7
3581+
3582+#define AESCR _SFR_IO8(0x13)
3583+#define AESWK 0
3584+#define AESWD 1
3585+#define AESIM 2
3586+#define AESD 3
3587+#define AESXOR 4
3588+#define AESRES 5
3589+#define AESE 7
3590+
3591+#define AESSR _SFR_IO8(0x14)
3592+#define AESRF 0
3593+#define AESERF 7
3594+
3595+#define TMIFR _SFR_IO8(0x15)
3596+#define TMRXF 0
3597+#define TMTXF 1
3598+#define TMTCF 2
3599+#define TMRXS 3
3600+#define TMTXS 4
3601+
3602+#define VMSR _SFR_IO8(0x16)
3603+#define VMF 0
3604+
3605+#define PCIFR _SFR_IO8(0x17)
3606+#define PCIF0 0
3607+#define PCIF1 1
3608+
3609+/* Reserved [0x18] */
3610+
3611+#define T0IFR _SFR_IO8(0x19)
3612+#define T0F 0
3613+
3614+#define T1IFR _SFR_IO8(0x1A)
3615+#define T1F 0
3616+
3617+#define T2IFR _SFR_IO8(0x1B)
3618+#define T2OFF 0
3619+#define T2COF 1
3620+
3621+#define T3IFR _SFR_IO8(0x1C)
3622+#define T3OFF 0
3623+#define T3COF 1
3624+#define T3ICF 2
3625+
3626+#define EIFR _SFR_IO8(0x1D)
3627+#define INTF0 0
3628+
3629+#define GPIOR0 _SFR_IO8(0x1E)
3630+
3631+#define EECR _SFR_IO8(0x1F)
3632+#define EERE 0
3633+#define EEWE 1
3634+#define EEMWE 2
3635+#define EERIE 3
3636+#define EEPM0 4
3637+#define EEPM1 5
3638+#define EELP 6
3639+
3640+#define EEDR _SFR_IO8(0x20)
3641+
3642+/* Combine EEARL and EEARH */
3643+#define EEAR _SFR_IO16(0x21)
3644+
3645+#define EEARL _SFR_IO8(0x21)
3646+#define EEARH _SFR_IO8(0x22)
3647+
3648+#define EEPR _SFR_IO8(0x23)
3649+#define EEAP0 0
3650+#define EEAP1 1
3651+#define EEAP2 2
3652+#define EEAP3 3
3653+
3654+#define EECCR _SFR_IO8(0x24)
3655+#define EEL0 0
3656+#define EEL1 1
3657+#define EEL2 2
3658+#define EEL3 3
3659+
3660+/* Reserved [0x25] */
3661+
3662+#define PCICR _SFR_IO8(0x26)
3663+#define PCIE0 0
3664+#define PCIE1 1
3665+
3666+#define EIMSK _SFR_IO8(0x27)
3667+#define INT0 0
3668+
3669+#define TMDR _SFR_IO8(0x28)
3670+
3671+#define AESDR _SFR_IO8(0x29)
3672+
3673+#define AESKR _SFR_IO8(0x2A)
3674+#define AESKR0 0
3675+#define AESKR1 1
3676+#define AESKR2 2
3677+#define AESKR3 3
3678+#define AESKR4 4
3679+#define AESKR5 5
3680+#define AESKR6 6
3681+#define AESKR7 7
3682+
3683+#define VMCR _SFR_IO8(0x2B)
3684+#define VMLS0 0
3685+#define VMLS1 1
3686+#define VMLS2 2
3687+#define VMLS3 3
3688+#define VMIM 4
3689+#define VMPS 5
3690+#define BODPD 6
3691+#define BODLS 7
3692+
3693+#define SPCR _SFR_IO8(0x2C)
3694+#define SPR0 0
3695+#define SPR1 1
3696+#define CPHA 2
3697+#define CPOL 3
3698+#define MSTR 4
3699+#define DORD 5
3700+#define SPE 6
3701+#define SPIE 7
3702+
3703+#define SPSR _SFR_IO8(0x2D)
3704+#define SPI2X 0
3705+#define WCOL 6
3706+#define SPIF 7
3707+
3708+#define SPDR _SFR_IO8(0x2E)
3709+
3710+/* Reserved [0x2F..0x32] */
3711+
3712+#define SMCR _SFR_IO8(0x33)
3713+#define SE 0
3714+#define SM0 1
3715+#define SM1 2
3716+#define SM2 3
3717+
3718+#define MCUSR _SFR_IO8(0x34)
3719+#define PORF 0
3720+#define EXTRF 1
3721+#define BORF 2
3722+#define WDRF 3
3723+#define TPRF 5
3724+
3725+#define MCUCR _SFR_IO8(0x35)
3726+#define IVCE 0
3727+#define IVSEL 1
3728+#define PUD 4
3729+
3730+/* Reserved [0x36] */
3731+
3732+#define SPMCSR _SFR_IO8(0x37)
3733+#define SPMEN 0
3734+#define PGERS 1
3735+#define PGWRT 2
3736+#define BLBSET 3
3737+#define RWWSRE 4
3738+#define SIGRD 5
3739+#define RWWSB 6
3740+#define SPMIE 7
3741+
3742+#define T1CR _SFR_IO8(0x38)
3743+#define T1PS0 0
3744+#define T1PS1 1
3745+#define T1IE 2
3746+#define T1CS0 3
3747+#define T1CS1 4
3748+#define T1E 7
3749+
3750+#define T0CR _SFR_IO8(0x39)
3751+#define T0PS0 0
3752+#define T0PS1 1
3753+#define T0PS2 2
3754+#define T0IE 3
3755+#define T0PR 4
3756+
3757+/* Reserved [0x3A] */
3758+
3759+#define CMIMR _SFR_IO8(0x3B)
3760+#define ECIE 0
3761+#define SXIE 1
3762+#define RTCIE 2
3763+
3764+#define CLKPR _SFR_IO8(0x3C)
3765+#define CLKPS0 0
3766+#define CLKPS1 1
3767+#define CLKPS2 2
3768+#define CLTPS0 3
3769+#define CLTPS1 4
3770+#define CLTPS2 5
3771+#define CLKPCE 7
3772+
3773+/* SP [0x3D..0x3E] */
3774+
3775+/* SREG [0x3F] */
3776+
3777+#define WDTCR _SFR_MEM8(0x60)
3778+#define WDPS0 0
3779+#define WDPS1 1
3780+#define WDPS2 2
3781+#define WDE 3
3782+#define WDCE 4
3783+
3784+/* Reserved [0x61..0x62] */
3785+
3786+#define PRR0 _SFR_MEM8(0x63)
3787+#define PRT1 1
3788+#define PRT2 2
3789+#define PRT3 3
3790+#define PRTM 4
3791+#define PRCU 5
3792+#define PRDS 6
3793+#define PRVM 7
3794+
3795+#define PRR1 _SFR_MEM8(0x64)
3796+#define PRCI 0
3797+#define PRSPI 1
3798+
3799+#define SRCCAL _SFR_MEM8(0x65)
3800+
3801+#define FRCCAL _SFR_MEM8(0x66)
3802+
3803+/* Reserved [0x67..0x68] */
3804+
3805+#define EICRA _SFR_MEM8(0x69)
3806+#define ISC00 0
3807+#define ISC01 1
3808+
3809+#define PCMSK0 _SFR_MEM8(0x6A)
3810+#define PCINT0 0
3811+#define PCINT1 1
3812+#define PCINT2 2
3813+#define PCINT3 3
3814+#define PCINT4 4
3815+#define PCINT5 5
3816+#define PCINT6 6
3817+#define PCINT7 7
3818+
3819+#define PCMSK1 _SFR_MEM8(0x6B)
3820+#define PCINT8 0
3821+#define PCINT9 1
3822+#define PCINT10 2
3823+#define PCINT11 3
3824+#define PCINT12 4
3825+#define PCINT13 5
3826+#define PCINT14 6
3827+#define PCINT15 7
3828+
3829+/* Reserved [0x6C] */
3830+
3831+#define LDCR _SFR_MEM8(0x6D)
3832+#define LDE 0
3833+#define LDCS0 1
3834+#define LDCS1 2
3835+
3836+/* Reserved [0x6E..0x6F] */
3837+
3838+#define T2CNT _SFR_MEM8(0x70)
3839+
3840+#define T2COR _SFR_MEM8(0x71)
3841+
3842+/* Reserved [0x72] */
3843+
3844+#define T2MR _SFR_MEM8(0x73)
3845+#define T2CS0 0
3846+#define T2CS1 1
3847+#define T2CS2 2
3848+#define T2PS0 3
3849+#define T2PS1 4
3850+#define T2PS2 5
3851+#define T2D0 6
3852+#define T2D1 7
3853+
3854+#define T2IMR _SFR_MEM8(0x74)
3855+#define T2OIM 0
3856+#define T2CIM 1
3857+
3858+/* Reserved [0x75] */
3859+
3860+#define T3CNT _SFR_MEM8(0x76)
3861+
3862+#define T3COR _SFR_MEM8(0x77)
3863+
3864+#define T3ICR _SFR_MEM8(0x78)
3865+
3866+#define T3MRA _SFR_MEM8(0x79)
3867+#define T3CS0 0
3868+#define T3CS1 1
3869+#define T3SCE 2
3870+#define T3CE0 3
3871+#define T3CE1 4
3872+#define T3CNC 5
3873+#define T3ICS0 6
3874+#define T3ICS1 7
3875+
3876+#define T3MRB _SFR_MEM8(0x7A)
3877+#define T3PS0 0
3878+#define T3PS1 1
3879+#define T3PS2 2
3880+
3881+#define T3IMR _SFR_MEM8(0x7B)
3882+#define T3OIM 0
3883+#define T3CIM 1
3884+#define T3CPIM 2
3885+
3886+/* Reserved [0x7C] */
3887+
3888+#define TMCR _SFR_MEM8(0x7D)
3889+#define MI1S0 0
3890+#define MI1S1 1
3891+#define MI2S0 2
3892+#define MI2S1 3
3893+#define MI4S0 4
3894+#define MI4S1 5
3895+#define TMCPOL 6
3896+#define TMSSIE 7
3897+
3898+#define TMMR _SFR_MEM8(0x7E)
3899+#define MOS0 0
3900+#define MOS1 1
3901+#define MSCS0 2
3902+#define MSCS1 3
3903+#define MOUTC 4
3904+#define TMMS0 5
3905+#define TMMS1 6
3906+#define TM12S 7
3907+
3908+#define TMIMR _SFR_MEM8(0x7F)
3909+#define TMRXIM 0
3910+#define TMTXIM 1
3911+#define TMTCIM 2
3912+
3913+/* Reserved [0x80..0x9B] */
3914+
3915+#define TPIMR _SFR_MEM8(0x9C)
3916+#define TPIM 0
3917+
3918+/* Reserved [0x9D] */
3919+
3920+#define RTCCR _SFR_MEM8(0x9E)
3921+#define RTCR 0
3922+
3923+#define RTCDR _SFR_MEM8(0x9F)
3924+
3925+/* Reserved [0xA0..0xA7] */
3926+
3927+#define TMMDR _SFR_MEM8(0xA8)
3928+
3929+#define TMBDR _SFR_MEM8(0xA9)
3930+
3931+#define TMTDR _SFR_MEM8(0xAA)
3932+
3933+#define TMSR _SFR_MEM8(0xAB)
3934+
3935+/* Reserved [0xAC] */
3936+
3937+#define CRCDR _SFR_MEM8(0xAD)
3938+
3939+#define CRCCR _SFR_MEM8(0xAE)
3940+#define CRCN0 0
3941+#define CRCN1 1
3942+#define CRCN2 2
3943+#define CRCSEL 3
3944+#define REFLI 4
3945+#define REFLO 5
3946+#define CRCRS 7
3947+
3948+#define CRCSR _SFR_MEM8(0xAF)
3949+#define CRCBF 0
3950+
3951+
3952+
3953+/* Interrupt vectors */
3954+/* Vector 0 is the reset vector */
3955+/* Transponder Mode Interrupt */
3956+#define TPINT_vect _VECTOR(2)
3957+#define TPINT_vect_num 2
3958+
3959+/* External Interrupt Request 0 */
3960+#define INT0_vect _VECTOR(4)
3961+#define INT0_vect_num 4
3962+
3963+/* Pin Change Interrupt Request 0 */
3964+#define PCINT0_vect _VECTOR(6)
3965+#define PCINT0_vect_num 6
3966+
3967+/* Pin Change Interrupt Request 1 */
3968+#define PCINT1_vect _VECTOR(8)
3969+#define PCINT1_vect_num 8
3970+
3971+/* Voltage Monitor Interrupt */
3972+#define VMINT_vect _VECTOR(10)
3973+#define VMINT_vect_num 10
3974+
3975+/* Timer0 Interval Interrupt */
3976+#define T0INT_vect _VECTOR(12)
3977+#define T0INT_vect_num 12
3978+
3979+/* Timer3 Capture Interrupt */
3980+#define T3CAPINT_vect _VECTOR(14)
3981+#define T3CAPINT_vect_num 14
3982+
3983+/* Timer3 Compare Match Interrupt */
3984+#define T3COMINT_vect _VECTOR(16)
3985+#define T3COMINT_vect_num 16
3986+
3987+/* Timer3 Overflow Interrupt */
3988+#define T3OVFINT_vect _VECTOR(18)
3989+#define T3OVFINT_vect_num 18
3990+
3991+/* Timer2 Compare Match Interrupt */
3992+#define T2COMINT_vect _VECTOR(20)
3993+#define T2COMINT_vect_num 20
3994+
3995+/* Timer2 Overflow Interrupt */
3996+#define T2OVFINT_vect _VECTOR(22)
3997+#define T2OVFINT_vect_num 22
3998+
3999+/* Timer1 Interval Interrupt */
4000+#define T1INT_vect _VECTOR(24)
4001+#define T1INT_vect_num 24
4002+
4003+/* SPI Serial Transfer Complete */
4004+#define SPISTC_vect _VECTOR(26)
4005+#define SPISTC_vect_num 26
4006+
4007+/* Timer Modulator SSI Receive Buffer Interrupt */
4008+#define TMRXBINT_vect _VECTOR(28)
4009+#define TMRXBINT_vect_num 28
4010+
4011+/* Timer Modulator SSI Transmit Buffer Interrupt */
4012+#define TMTXBINT_vect _VECTOR(30)
4013+#define TMTXBINT_vect_num 30
4014+
4015+/* Timer Modulator Transmit Complete Interrupt */
4016+#define TMTXCINT_vect _VECTOR(32)
4017+#define TMTXCINT_vect_num 32
4018+
4019+/* AES Interrupt */
4020+#define AESINT_vect _VECTOR(34)
4021+#define AESINT_vect_num 34
4022+
4023+/* External Input Clock Monitoring Interrupt */
4024+#define EXCMINT_vect _VECTOR(36)
4025+#define EXCMINT_vect_num 36
4026+
4027+/* External XTAL Oscillator Break Down Interrupt */
4028+#define EXXMINT_vect _VECTOR(38)
4029+#define EXXMINT_vect_num 38
4030+
4031+/* Real Time Clock Interrupt */
4032+#define RTCINT_vect _VECTOR(40)
4033+#define RTCINT_vect_num 40
4034+
4035+/* EEPROM Ready Interrupt */
4036+#define EEREADY_vect _VECTOR(42)
4037+#define EEREADY_vect_num 42
4038+
4039+/* Store Program Memory Ready */
4040+#define SPMREADY_vect _VECTOR(44)
4041+#define SPMREADY_vect_num 44
4042+
4043+#define _VECTORS_SIZE 46
4044+
4045+
4046+/* Constants */
4047+
4048+#define SPM_PAGESIZE 64
4049+#define FLASHEND 0x1FFF
4050+#define RAMSTART 0x0100
4051+#define RAMSIZE 512
4052+#define RAMEND 0x02FF
4053+#define E2START 0
4054+#define E2SIZE 2048
4055+#define E2PAGESIZE 16
4056+#define E2END 0x07FF
4057+#define XRAMEND RAMEND
4058+
4059+
4060+/* Fuses */
4061+
4062+#define FUSE_MEMORY_SIZE 1
4063+
4064+/* Fuse Byte */
4065+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
4066+#define FUSE_DWEN (unsigned char)~_BV(64)
4067+#define FUSE_SPIEN (unsigned char)~_BV(32)
4068+#define FUSE_WDTON (unsigned char)~_BV(16)
4069+#define FUSE_EESAVE (unsigned char)~_BV(8)
4070+#define FUSE_Reserved (unsigned char)~_BV(4)
4071+#define FUSE__32OEN (unsigned char)~_BV(2)
4072+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
4073+
4074+/* Lock Bits */
4075+#define __LOCK_BITS_EXIST
4076+#define __BOOT_LOCK_BITS_0_EXIST
4077+#define __BOOT_LOCK_BITS_1_EXIST
4078+
4079+
4080+/* Signature */
4081+#define SIGNATURE_0 0x1E
4082+#define SIGNATURE_1 0x93
4083+#define SIGNATURE_2 0x61
4084+
4085+
4086+#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */
4087+
4088diff -urN avr-libc-1.8.0.orig/include/avr/ioa6285.h avr-libc-1.8.0/include/avr/ioa6285.h
4089--- avr-libc-1.8.0.orig/include/avr/ioa6285.h 1970-01-01 01:00:00.000000000 +0100
4090+++ avr-libc-1.8.0/include/avr/ioa6285.h 2013-01-18 09:50:25.000000000 +0100
4091@@ -0,0 +1,705 @@
4092+/*****************************************************************************
4093+ *
4094+ * Copyright (C) 2012 Atmel Corporation
4095+ * All rights reserved.
4096+ *
4097+ * Redistribution and use in source and binary forms, with or without
4098+ * modification, are permitted provided that the following conditions are met:
4099+ *
4100+ * * Redistributions of source code must retain the above copyright
4101+ * notice, this list of conditions and the following disclaimer.
4102+ *
4103+ * * Redistributions in binary form must reproduce the above copyright
4104+ * notice, this list of conditions and the following disclaimer in
4105+ * the documentation and/or other materials provided with the
4106+ * distribution.
4107+ *
4108+ * * Neither the name of the copyright holders nor the names of
4109+ * contributors may be used to endorse or promote products derived
4110+ * from this software without specific prior written permission.
4111+ *
4112+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
4113+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4114+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4115+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
4116+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4117+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
4118+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
4119+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
4120+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4121+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
4122+ * POSSIBILITY OF SUCH DAMAGE.
4123+ ****************************************************************************/
4124+
4125+
4126+#ifndef _AVR_ATA6285_H_INCLUDED
4127+#define _AVR_ATA6285_H_INCLUDED
4128+
4129+
4130+#ifndef _AVR_IO_H_
4131+# error "Include <avr/io.h> instead of this file."
4132+#endif
4133+
4134+#ifndef _AVR_IOXXX_H_
4135+# define _AVR_IOXXX_H_ "ioa6285.h"
4136+#else
4137+# error "Attempt to include more than one <avr/ioXXX.h> file."
4138+#endif
4139+
4140+/* Registers and associated bit numbers */
4141+
4142+#define PINB _SFR_IO8(0x03)
4143+#define PINB7 7
4144+#define PINB6 6
4145+#define PINB5 5
4146+#define PINB4 4
4147+#define PINB3 3
4148+#define PINB2 2
4149+#define PINB1 1
4150+#define PINB0 0
4151+
4152+#define DDRB _SFR_IO8(0x04)
4153+#define DDRB7 7
4154+#define DDRB6 6
4155+#define DDRB5 5
4156+#define DDRB4 4
4157+#define DDRB3 3
4158+#define DDRB2 2
4159+#define DDRB1 1
4160+#define DDRB0 0
4161+
4162+#define PORTB _SFR_IO8(0x05)
4163+#define PORTB7 7
4164+#define PORTB6 6
4165+#define PORTB5 5
4166+#define PORTB4 4
4167+#define PORTB3 3
4168+#define PORTB2 2
4169+#define PORTB1 1
4170+#define PORTB0 0
4171+
4172+#define PINC _SFR_IO8(0x06)
4173+#define PINC7 7
4174+#define PINC6 6
4175+#define PINC5 5
4176+#define PINC4 4
4177+#define PINC3 3
4178+#define PINC2 2
4179+#define PINC1 1
4180+#define PINC0 0
4181+
4182+#define DDRC _SFR_IO8(0x07)
4183+#define DDRC7 7
4184+#define DDRC6 6
4185+#define DDRC5 5
4186+#define DDRC4 4
4187+#define DDRC3 3
4188+#define DDRC2 2
4189+#define DDRC1 1
4190+#define DDRC0 0
4191+
4192+#define PORTC _SFR_IO8(0x08)
4193+#define PORTC7 7
4194+#define PORTC6 6
4195+#define PORTC5 5
4196+#define PORTC4 4
4197+#define PORTC3 3
4198+#define PORTC2 2
4199+#define PORTC1 1
4200+#define PORTC0 0
4201+
4202+#define PIND _SFR_IO8(0x09)
4203+#define PIND7 7
4204+#define PIND6 6
4205+#define PIND5 5
4206+#define PIND4 4
4207+#define PIND3 3
4208+#define PIND2 2
4209+#define PIND1 1
4210+#define PIND0 0
4211+
4212+#define DDRD _SFR_IO8(0x0A)
4213+#define DDRD7 7
4214+#define DDRD6 6
4215+#define DDRD5 5
4216+#define DDRD4 4
4217+#define DDRD3 3
4218+#define DDRD2 2
4219+#define DDRD1 1
4220+#define DDRD0 0
4221+
4222+#define PORTD _SFR_IO8(0x0B)
4223+#define PORTD7 7
4224+#define PORTD6 6
4225+#define PORTD5 5
4226+#define PORTD4 4
4227+#define PORTD3 3
4228+#define PORTD2 2
4229+#define PORTD1 1
4230+#define PORTD0 0
4231+
4232+/* Reserved [0x0C..0x0E] */
4233+
4234+#define CMCR _SFR_IO8(0x0F)
4235+#define CMM0 0
4236+#define CMM1 1
4237+#define SRCD 2
4238+#define CMONEN 3
4239+#define CCS 4
4240+#define ECINS 5
4241+#define CMCCE 7
4242+
4243+#define CMSR _SFR_IO8(0x10)
4244+#define ECF 0
4245+
4246+#define T2CRA _SFR_IO8(0x11)
4247+#define T2OTM 0
4248+#define T2CTM 1
4249+#define T2CR 2
4250+#define T2CRM 3
4251+#define T2ICS 5
4252+#define T2TS 6
4253+#define T2E 7
4254+
4255+#define T2CRB _SFR_IO8(0x12)
4256+#define T2SCE 0
4257+
4258+/* Reserved [0x13] */
4259+
4260+#define T3CRA _SFR_IO8(0x14)
4261+#define T3AC 0
4262+#define T3SCE 1
4263+#define T3CR 2
4264+#define T3TS 6
4265+#define T3E 7
4266+
4267+/* Reserved [0x15] */
4268+
4269+#define VMCSR _SFR_IO8(0x16)
4270+#define VMEN 0
4271+#define VMLS0 1
4272+#define VMLS1 2
4273+#define VMLS2 3
4274+#define VMIM 4
4275+#define VMF 5
4276+#define BODPD 6
4277+#define BODLS 7
4278+
4279+#define PCIFR _SFR_IO8(0x17)
4280+#define PCIF0 0
4281+#define PCIF1 1
4282+#define PCIF2 2
4283+
4284+#define LFFR _SFR_IO8(0x18)
4285+#define LFWPF 0
4286+#define LFBF 1
4287+#define LFEDF 2
4288+#define LFRF 3
4289+
4290+#define SSFR _SFR_IO8(0x19)
4291+#define MSENF 0
4292+#define MSENO 1
4293+
4294+#define T10IFR _SFR_IO8(0x1A)
4295+#define T0F 0
4296+#define T1F 1
4297+
4298+#define T2IFR _SFR_IO8(0x1B)
4299+#define T2OFF 0
4300+#define T2COF 1
4301+#define T2ICF 2
4302+#define T2RXF 3
4303+#define T2TXF 4
4304+#define T2TCF 5
4305+
4306+#define T3IFR _SFR_IO8(0x1C)
4307+#define T3OFF 0
4308+#define T3COAF 1
4309+#define T3COBF 2
4310+#define T3ICF 3
4311+
4312+#define EIFR _SFR_IO8(0x1D)
4313+#define INTF0 0
4314+#define INTF1 1
4315+
4316+#define GPIOR0 _SFR_IO8(0x1E)
4317+
4318+#define EECR _SFR_IO8(0x1F)
4319+#define EERE 0
4320+#define EEWE 1
4321+#define EEMWE 2
4322+#define EERIE 3
4323+#define EEPM0 4
4324+#define EEPM1 5
4325+
4326+#define EEDR _SFR_IO8(0x20)
4327+
4328+/* Combine EEARL and EEARH */
4329+#define EEAR _SFR_IO16(0x21)
4330+
4331+#define EEARL _SFR_IO8(0x21)
4332+#define EEARH _SFR_IO8(0x22)
4333+
4334+#define PCICR _SFR_IO8(0x23)
4335+#define PCIE0 0
4336+#define PCIE1 1
4337+#define PCIE2 2
4338+
4339+#define EIMSK _SFR_IO8(0x24)
4340+#define INT0 0
4341+#define INT1 1
4342+
4343+/* Reserved [0x25..0x26] */
4344+
4345+#define SVCR _SFR_IO8(0x27)
4346+
4347+#define SCR _SFR_IO8(0x28)
4348+#define SMS 0
4349+#define SEN0 1
4350+#define SEN1 2
4351+#define SMEN 3
4352+
4353+#define SCCR _SFR_IO8(0x29)
4354+#define SRCC0 0
4355+#define SRCC1 1
4356+#define SCCS0 2
4357+#define SCCS1 3
4358+#define SCCS2 4
4359+
4360+#define GPIOR1 _SFR_IO8(0x2A)
4361+
4362+#define GPIOR2 _SFR_IO8(0x2B)
4363+
4364+#define SPCR _SFR_IO8(0x2C)
4365+#define SPR0 0
4366+#define SPR1 1
4367+#define CPHA 2
4368+#define CPOL 3
4369+#define MSTR 4
4370+#define DORD 5
4371+#define SPE 6
4372+#define SPIE 7
4373+
4374+#define SPSR _SFR_IO8(0x2D)
4375+#define SPI2X 0
4376+#define WCOL 6
4377+#define SPIF 7
4378+
4379+#define SPDR _SFR_IO8(0x2E)
4380+
4381+#define T2MDR _SFR_IO8(0x2F)
4382+
4383+#define LFRR _SFR_IO8(0x30)
4384+
4385+/* Reserved [0x31] */
4386+
4387+#define LFCDR _SFR_IO8(0x32)
4388+#define LFDO 0
4389+#define LFRST 6
4390+#define LFSCE 7
4391+
4392+#define SMCR _SFR_IO8(0x33)
4393+#define SE 0
4394+#define SM0 1
4395+#define SM1 2
4396+#define SM2 3
4397+
4398+#define MCUSR _SFR_IO8(0x34)
4399+#define PORF 0
4400+#define EXTRF 1
4401+#define BORF 2
4402+#define WDRF 3
4403+#define TSRF 5
4404+
4405+#define MCUCR _SFR_IO8(0x35)
4406+#define IVCE 0
4407+#define IVSEL 1
4408+#define PUD 4
4409+
4410+#define LFRB _SFR_IO8(0x36)
4411+
4412+#define SPMCSR _SFR_IO8(0x37)
4413+#define SELFPRGEN 0
4414+#define PGERS 1
4415+#define PGWRT 2
4416+#define BLBSET 3
4417+#define RWWSRE 4
4418+#define RWWSB 6
4419+#define SPMIE 7
4420+
4421+#define T1CR _SFR_IO8(0x38)
4422+#define T1PS0 0
4423+#define T1PS1 1
4424+#define T1PS2 2
4425+#define T1CS0 3
4426+#define T1CS1 4
4427+#define T1CS2 5
4428+#define T1IE 7
4429+
4430+#define T0CR _SFR_IO8(0x39)
4431+#define T0PAS0 0
4432+#define T0PAS1 1
4433+#define T0PAS2 2
4434+#define T0IE 3
4435+#define T0PR 4
4436+#define T0PBS0 5
4437+#define T0PBS1 6
4438+#define T0PBS2 7
4439+
4440+/* Reserved [0x3A] */
4441+
4442+#define CMIMR _SFR_IO8(0x3B)
4443+#define ECIE 0
4444+
4445+#define CLKPR _SFR_IO8(0x3C)
4446+#define CLKPS0 0
4447+#define CLKPS1 1
4448+#define CLKPS2 2
4449+#define CLTPS0 3
4450+#define CLTPS1 4
4451+#define CLTPS2 5
4452+#define CLPCE 7
4453+
4454+/* SP [0x3D..0x3E] */
4455+
4456+/* SREG [0x3F] */
4457+
4458+#define WDTCR _SFR_MEM8(0x60)
4459+#define WDPS0 0
4460+#define WDPS1 1
4461+#define WDPS2 2
4462+#define WDE 3
4463+#define WDCE 4
4464+
4465+#define SIMSK _SFR_MEM8(0x61)
4466+#define MSIE 0
4467+
4468+/* Reserved [0x62..0x63] */
4469+
4470+#define TSCR _SFR_MEM8(0x64)
4471+#define TSSD 0
4472+
4473+#define SRCCAL _SFR_MEM8(0x65)
4474+
4475+#define FRCCAL _SFR_MEM8(0x66)
4476+
4477+#define MSVCAL _SFR_MEM8(0x67)
4478+
4479+/* Reserved [0x68] */
4480+
4481+#define EICRA _SFR_MEM8(0x69)
4482+#define ISC00 0
4483+#define ISC01 1
4484+#define ISC10 2
4485+#define ISC11 3
4486+
4487+#define PCMSK0 _SFR_MEM8(0x6A)
4488+#define PCINT0 0
4489+#define PCINT1 1
4490+#define PCINT2 2
4491+#define PCINT3 3
4492+#define PCINT4 4
4493+#define PCINT5 5
4494+#define PCINT6 6
4495+#define PCINT7 7
4496+
4497+#define PCMSK1 _SFR_MEM8(0x6B)
4498+#define PCINT8 0
4499+#define PCINT9 1
4500+#define PCINT10 2
4501+
4502+#define PCMSK2 _SFR_MEM8(0x6C)
4503+#define PCINT16 0
4504+#define PCINT17 1
4505+#define PCINT18 2
4506+#define PCINT19 3
4507+#define PCINT20 4
4508+#define PCINT21 5
4509+#define PCINT22 6
4510+#define PCINT23 7
4511+
4512+/* Reserved [0x6D] */
4513+
4514+#define T2ICRL _SFR_MEM8(0x6E)
4515+
4516+#define T2ICR _SFR_MEM8(0x6F)
4517+
4518+/* Combine T2CORL and T2CORH */
4519+#define T2COR _SFR_MEM16(0x70)
4520+
4521+#define T2CORL _SFR_MEM8(0x70)
4522+#define T2CORH _SFR_MEM8(0x71)
4523+
4524+#define T2MRA _SFR_MEM8(0x72)
4525+#define T2CS0 0
4526+#define T2CS1 1
4527+#define T2CS2 2
4528+#define T2CE0 3
4529+#define T2CE1 4
4530+#define T2CNC 5
4531+#define T2TP0 6
4532+#define T2TP1 7
4533+
4534+#define T2MRB _SFR_MEM8(0x73)
4535+#define T2M0 0
4536+#define T2M1 1
4537+#define T2M2 2
4538+#define T2M3 3
4539+#define T2TOP 4
4540+#define T2CPOL 6
4541+#define T2SSIE 7
4542+
4543+#define T2IMR _SFR_MEM8(0x74)
4544+#define T2OIM 0
4545+#define T2CIM 1
4546+#define T2CPIM 2
4547+#define T2RXIM 3
4548+#define T2TXIM 4
4549+#define T2TCIM 5
4550+
4551+/* Reserved [0x75] */
4552+
4553+/* Combine T3ICRL and T3ICRH */
4554+#define T3ICR _SFR_MEM16(0x76)
4555+
4556+#define T3ICRL _SFR_MEM8(0x76)
4557+#define T3ICRH _SFR_MEM8(0x77)
4558+
4559+/* Combine T3CORAL and T3CORAH */
4560+#define T3CORA _SFR_MEM16(0x78)
4561+
4562+#define T3CORAL _SFR_MEM8(0x78)
4563+#define T3CORAH _SFR_MEM8(0x79)
4564+
4565+/* Combine T3CORBL and T3CORBH */
4566+#define T3CORB _SFR_MEM16(0x7A)
4567+
4568+#define T3CORBL _SFR_MEM8(0x7A)
4569+#define T3CORBH _SFR_MEM8(0x7B)
4570+
4571+#define T3MRA _SFR_MEM8(0x7C)
4572+#define T3CS0 0
4573+#define T3CS1 1
4574+#define T3CS2 2
4575+#define T3CE0 3
4576+#define T3CE1 4
4577+#define T3CNC 5
4578+#define T3ICS0 6
4579+#define T3ICS1 7
4580+
4581+#define T3MRB _SFR_MEM8(0x7D)
4582+#define T3M0 0
4583+#define T3M1 1
4584+#define T3M2 2
4585+#define T3TOP 4
4586+
4587+#define T3CRB _SFR_MEM8(0x7E)
4588+#define T3CTMA 0
4589+#define T3SAMA 1
4590+#define T3CRMA 2
4591+#define T3CTMB 3
4592+#define T3SAMB 4
4593+#define T3CRMB 5
4594+#define T3CPRM 6
4595+
4596+#define T3IMR _SFR_MEM8(0x7F)
4597+#define T3OIM 0
4598+#define T3CAIM 1
4599+#define T3CBIM 2
4600+#define T3CPIM 3
4601+
4602+/* Reserved [0x80] */
4603+
4604+#define LFIMR _SFR_MEM8(0x81)
4605+#define LFWIM 0
4606+#define LFBIM 1
4607+#define LFEIM 2
4608+
4609+#define LFRCR _SFR_MEM8(0x82)
4610+#define LFEN 0
4611+#define LFBM 1
4612+#define LFWM0 2
4613+#define LFWM1 3
4614+#define LFRSS 4
4615+#define LFCS0 5
4616+#define LFCS1 6
4617+#define LFCS2 7
4618+
4619+#define LFHCR _SFR_MEM8(0x83)
4620+
4621+/* Combine LFIDCL and LFIDCH */
4622+#define LFIDC _SFR_MEM16(0x84)
4623+
4624+#define LFIDCL _SFR_MEM8(0x84)
4625+#define LFIDCH _SFR_MEM8(0x85)
4626+
4627+/* Combine LFCALL and LFCALH */
4628+#define LFCAL _SFR_MEM16(0x86)
4629+
4630+#define LFCALL _SFR_MEM8(0x86)
4631+#define LFCALH _SFR_MEM8(0x87)
4632+
4633+
4634+
4635+/* Interrupt vectors */
4636+/* Vector 0 is the reset vector */
4637+/* External Interrupt Request 0 */
4638+#define INT0_vect _VECTOR(1)
4639+#define INT0_vect_num 1
4640+
4641+/* External Interrupt Request 1 */
4642+#define INT1_vect _VECTOR(2)
4643+#define INT1_vect_num 2
4644+
4645+/* Pin Change Interrupt Request 0 */
4646+#define PCINT0_vect _VECTOR(3)
4647+#define PCINT0_vect_num 3
4648+
4649+/* Pin Change Interrupt Request 1 */
4650+#define PCINT1_vect _VECTOR(4)
4651+#define PCINT1_vect_num 4
4652+
4653+/* Pin Change Interrupt Request 2 */
4654+#define PCINT2_vect _VECTOR(5)
4655+#define PCINT2_vect_num 5
4656+
4657+/* Voltage Monitor Interrupt */
4658+#define INTVM_vect _VECTOR(6)
4659+#define INTVM_vect_num 6
4660+
4661+/* Sensor Interface Interrupt */
4662+#define SENINT_vect _VECTOR(7)
4663+#define SENINT_vect_num 7
4664+
4665+/* Timer0 Interval Interrupt */
4666+#define INTT0_vect _VECTOR(8)
4667+#define INTT0_vect_num 8
4668+
4669+/* LF-Receiver Wake-up Interrupt */
4670+#define LFWP_vect _VECTOR(9)
4671+#define LFWP_vect_num 9
4672+
4673+/* Timer/Counter3 Capture Event */
4674+#define T3CAP_vect _VECTOR(10)
4675+#define T3CAP_vect_num 10
4676+
4677+/* Timer/Counter3 Compare Match A */
4678+#define T3COMA_vect _VECTOR(11)
4679+#define T3COMA_vect_num 11
4680+
4681+/* Timer/Counter3 Compare Match B */
4682+#define T3COMB_vect _VECTOR(12)
4683+#define T3COMB_vect_num 12
4684+
4685+/* Timer/Counter3 Overflow */
4686+#define T3OVF_vect _VECTOR(13)
4687+#define T3OVF_vect_num 13
4688+
4689+/* Timer/Counter2 Capture Event */
4690+#define T2CAP_vect _VECTOR(14)
4691+#define T2CAP_vect_num 14
4692+
4693+/* Timer/Counter2 Compare Match */
4694+#define T2COM_vect _VECTOR(15)
4695+#define T2COM_vect_num 15
4696+
4697+/* Timer/Counter2 Overflow */
4698+#define T2OVF_vect _VECTOR(16)
4699+#define T2OVF_vect_num 16
4700+
4701+/* SPI Serial Transfer Complete */
4702+#define SPISTC_vect _VECTOR(17)
4703+#define SPISTC_vect_num 17
4704+
4705+/* LF Receive Buffer Interrupt */
4706+#define LFRXB_vect _VECTOR(18)
4707+#define LFRXB_vect_num 18
4708+
4709+/* Timer1 Interval Interrupt */
4710+#define INTT1_vect _VECTOR(19)
4711+#define INTT1_vect_num 19
4712+
4713+/* Timer2 SSI Receive Buffer Interrupt */
4714+#define T2RXB_vect _VECTOR(20)
4715+#define T2RXB_vect_num 20
4716+
4717+/* Timer2 SSI Transmit Buffer Interrupt */
4718+#define T2TXB_vect _VECTOR(21)
4719+#define T2TXB_vect_num 21
4720+
4721+/* Timer2 SSI Transmit Complete Interrupt */
4722+#define T2TXC_vect _VECTOR(22)
4723+#define T2TXC_vect_num 22
4724+
4725+/* LF-Receiver End of Burst Interrupt */
4726+#define LFREOB_vect _VECTOR(23)
4727+#define LFREOB_vect_num 23
4728+
4729+/* External Input Clock break down Interrupt */
4730+#define EXCM_vect _VECTOR(24)
4731+#define EXCM_vect_num 24
4732+
4733+/* EEPROM Ready Interrupt */
4734+#define EEREADY_vect _VECTOR(25)
4735+#define EEREADY_vect_num 25
4736+
4737+/* Store Program Memory Ready */
4738+#define SPM_RDY_vect _VECTOR(26)
4739+#define SPM_RDY_vect_num 26
4740+
4741+#define _VECTORS_SIZE 54
4742+
4743+
4744+/* Constants */
4745+
4746+#define SPM_PAGESIZE 64
4747+#define FLASHEND 0x1FFF
4748+#define RAMSTART 0x0100
4749+#define RAMSIZE 512
4750+#define RAMEND 0x02FF
4751+#define E2START 0
4752+#define E2SIZE 320
4753+#define E2PAGESIZE 4
4754+#define E2END 0x013F
4755+#define XRAMEND RAMEND
4756+
4757+
4758+/* Fuses */
4759+
4760+#define FUSE_MEMORY_SIZE 2
4761+
4762+/* Low Fuse Byte */
4763+#define FUSE_TSRDI (unsigned char)~_BV(0)
4764+#define FUSE_BODEN (unsigned char)~_BV(1)
4765+#define FUSE_FRCFS (unsigned char)~_BV(2)
4766+#define FUSE_WDRCON (unsigned char)~_BV(3)
4767+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
4768+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
4769+#define FUSE_CKOUT (unsigned char)~_BV(6)
4770+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
4771+
4772+/* High Fuse Byte */
4773+#define FUSE_BOOTRST (unsigned char)~_BV(0)
4774+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
4775+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
4776+#define FUSE_EESAVE (unsigned char)~_BV(3)
4777+#define FUSE_WDTON (unsigned char)~_BV(4)
4778+#define FUSE_SPIEN (unsigned char)~_BV(5)
4779+#define FUSE_DWEN (unsigned char)~_BV(6)
4780+#define FUSE_EELOCK (unsigned char)~_BV(7)
4781+
4782+
4783+/* Lock Bits */
4784+#define __LOCK_BITS_EXIST
4785+#define __BOOT_LOCK_BITS_0_EXIST
4786+#define __BOOT_LOCK_BITS_1_EXIST
4787+
4788+
4789+/* Signature */
4790+#define SIGNATURE_0 0x1E
4791+#define SIGNATURE_1 0x93
4792+#define SIGNATURE_2 0x82
4793+
4794+
4795+#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */
4796+
4797diff -urN avr-libc-1.8.0.orig/include/avr/ioa6286.h avr-libc-1.8.0/include/avr/ioa6286.h
4798--- avr-libc-1.8.0.orig/include/avr/ioa6286.h 1970-01-01 01:00:00.000000000 +0100
4799+++ avr-libc-1.8.0/include/avr/ioa6286.h 2013-01-18 09:50:25.000000000 +0100
4800@@ -0,0 +1,705 @@
4801+/*****************************************************************************
4802+ *
4803+ * Copyright (C) 2012 Atmel Corporation
4804+ * All rights reserved.
4805+ *
4806+ * Redistribution and use in source and binary forms, with or without
4807+ * modification, are permitted provided that the following conditions are met:
4808+ *
4809+ * * Redistributions of source code must retain the above copyright
4810+ * notice, this list of conditions and the following disclaimer.
4811+ *
4812+ * * Redistributions in binary form must reproduce the above copyright
4813+ * notice, this list of conditions and the following disclaimer in
4814+ * the documentation and/or other materials provided with the
4815+ * distribution.
4816+ *
4817+ * * Neither the name of the copyright holders nor the names of
4818+ * contributors may be used to endorse or promote products derived
4819+ * from this software without specific prior written permission.
4820+ *
4821+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
4822+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4823+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4824+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
4825+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
4826+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
4827+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
4828+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
4829+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4830+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
4831+ * POSSIBILITY OF SUCH DAMAGE.
4832+ ****************************************************************************/
4833+
4834+
4835+#ifndef _AVR_ATA6286_H_INCLUDED
4836+#define _AVR_ATA6286_H_INCLUDED
4837+
4838+
4839+#ifndef _AVR_IO_H_
4840+# error "Include <avr/io.h> instead of this file."
4841+#endif
4842+
4843+#ifndef _AVR_IOXXX_H_
4844+# define _AVR_IOXXX_H_ "ioa6286.h"
4845+#else
4846+# error "Attempt to include more than one <avr/ioXXX.h> file."
4847+#endif
4848+
4849+/* Registers and associated bit numbers */
4850+
4851+#define PINB _SFR_IO8(0x03)
4852+#define PINB7 7
4853+#define PINB6 6
4854+#define PINB5 5
4855+#define PINB4 4
4856+#define PINB3 3
4857+#define PINB2 2
4858+#define PINB1 1
4859+#define PINB0 0
4860+
4861+#define DDRB _SFR_IO8(0x04)
4862+#define DDRB7 7
4863+#define DDRB6 6
4864+#define DDRB5 5
4865+#define DDRB4 4
4866+#define DDRB3 3
4867+#define DDRB2 2
4868+#define DDRB1 1
4869+#define DDRB0 0
4870+
4871+#define PORTB _SFR_IO8(0x05)
4872+#define PORTB7 7
4873+#define PORTB6 6
4874+#define PORTB5 5
4875+#define PORTB4 4
4876+#define PORTB3 3
4877+#define PORTB2 2
4878+#define PORTB1 1
4879+#define PORTB0 0
4880+
4881+#define PINC _SFR_IO8(0x06)
4882+#define PINC7 7
4883+#define PINC6 6
4884+#define PINC5 5
4885+#define PINC4 4
4886+#define PINC3 3
4887+#define PINC2 2
4888+#define PINC1 1
4889+#define PINC0 0
4890+
4891+#define DDRC _SFR_IO8(0x07)
4892+#define DDRC7 7
4893+#define DDRC6 6
4894+#define DDRC5 5
4895+#define DDRC4 4
4896+#define DDRC3 3
4897+#define DDRC2 2
4898+#define DDRC1 1
4899+#define DDRC0 0
4900+
4901+#define PORTC _SFR_IO8(0x08)
4902+#define PORTC7 7
4903+#define PORTC6 6
4904+#define PORTC5 5
4905+#define PORTC4 4
4906+#define PORTC3 3
4907+#define PORTC2 2
4908+#define PORTC1 1
4909+#define PORTC0 0
4910+
4911+#define PIND _SFR_IO8(0x09)
4912+#define PIND7 7
4913+#define PIND6 6
4914+#define PIND5 5
4915+#define PIND4 4
4916+#define PIND3 3
4917+#define PIND2 2
4918+#define PIND1 1
4919+#define PIND0 0
4920+
4921+#define DDRD _SFR_IO8(0x0A)
4922+#define DDRD7 7
4923+#define DDRD6 6
4924+#define DDRD5 5
4925+#define DDRD4 4
4926+#define DDRD3 3
4927+#define DDRD2 2
4928+#define DDRD1 1
4929+#define DDRD0 0
4930+
4931+#define PORTD _SFR_IO8(0x0B)
4932+#define PORTD7 7
4933+#define PORTD6 6
4934+#define PORTD5 5
4935+#define PORTD4 4
4936+#define PORTD3 3
4937+#define PORTD2 2
4938+#define PORTD1 1
4939+#define PORTD0 0
4940+
4941+/* Reserved [0x0C..0x0E] */
4942+
4943+#define CMCR _SFR_IO8(0x0F)
4944+#define CMM0 0
4945+#define CMM1 1
4946+#define SRCD 2
4947+#define CMONEN 3
4948+#define CCS 4
4949+#define ECINS 5
4950+#define CMCCE 7
4951+
4952+#define CMSR _SFR_IO8(0x10)
4953+#define ECF 0
4954+
4955+#define T2CRA _SFR_IO8(0x11)
4956+#define T2OTM 0
4957+#define T2CTM 1
4958+#define T2CR 2
4959+#define T2CRM 3
4960+#define T2ICS 5
4961+#define T2TS 6
4962+#define T2E 7
4963+
4964+#define T2CRB _SFR_IO8(0x12)
4965+#define T2SCE 0
4966+
4967+/* Reserved [0x13] */
4968+
4969+#define T3CRA _SFR_IO8(0x14)
4970+#define T3AC 0
4971+#define T3SCE 1
4972+#define T3CR 2
4973+#define T3TS 6
4974+#define T3E 7
4975+
4976+/* Reserved [0x15] */
4977+
4978+#define VMCSR _SFR_IO8(0x16)
4979+#define VMEN 0
4980+#define VMLS0 1
4981+#define VMLS1 2
4982+#define VMLS2 3
4983+#define VMIM 4
4984+#define VMF 5
4985+#define BODPD 6
4986+#define BODLS 7
4987+
4988+#define PCIFR _SFR_IO8(0x17)
4989+#define PCIF0 0
4990+#define PCIF1 1
4991+#define PCIF2 2
4992+
4993+#define LFFR _SFR_IO8(0x18)
4994+#define LFWPF 0
4995+#define LFBF 1
4996+#define LFEDF 2
4997+#define LFRF 3
4998+
4999+#define SSFR _SFR_IO8(0x19)
5000+#define MSENF 0
5001+#define MSENO 1
5002+
5003+#define T10IFR _SFR_IO8(0x1A)
5004+#define T0F 0
5005+#define T1F 1
5006+
5007+#define T2IFR _SFR_IO8(0x1B)
5008+#define T2OFF 0
5009+#define T2COF 1
5010+#define T2ICF 2
5011+#define T2RXF 3
5012+#define T2TXF 4
5013+#define T2TCF 5
5014+
5015+#define T3IFR _SFR_IO8(0x1C)
5016+#define T3OFF 0
5017+#define T3COAF 1
5018+#define T3COBF 2
5019+#define T3ICF 3
5020+
5021+#define EIFR _SFR_IO8(0x1D)
5022+#define INTF0 0
5023+#define INTF1 1
5024+
5025+#define GPIOR0 _SFR_IO8(0x1E)
5026+
5027+#define EECR _SFR_IO8(0x1F)
5028+#define EERE 0
5029+#define EEWE 1
5030+#define EEMWE 2
5031+#define EERIE 3
5032+#define EEPM0 4
5033+#define EEPM1 5
5034+
5035+#define EEDR _SFR_IO8(0x20)
5036+
5037+/* Combine EEARL and EEARH */
5038+#define EEAR _SFR_IO16(0x21)
5039+
5040+#define EEARL _SFR_IO8(0x21)
5041+#define EEARH _SFR_IO8(0x22)
5042+
5043+#define PCICR _SFR_IO8(0x23)
5044+#define PCIE0 0
5045+#define PCIE1 1
5046+#define PCIE2 2
5047+
5048+#define EIMSK _SFR_IO8(0x24)
5049+#define INT0 0
5050+#define INT1 1
5051+
5052+/* Reserved [0x25..0x26] */
5053+
5054+#define SVCR _SFR_IO8(0x27)
5055+
5056+#define SCR _SFR_IO8(0x28)
5057+#define SMS 0
5058+#define SEN0 1
5059+#define SEN1 2
5060+#define SMEN 3
5061+
5062+#define SCCR _SFR_IO8(0x29)
5063+#define SRCC0 0
5064+#define SRCC1 1
5065+#define SCCS0 2
5066+#define SCCS1 3
5067+#define SCCS2 4
5068+
5069+#define GPIOR1 _SFR_IO8(0x2A)
5070+
5071+#define GPIOR2 _SFR_IO8(0x2B)
5072+
5073+#define SPCR _SFR_IO8(0x2C)
5074+#define SPR0 0
5075+#define SPR1 1
5076+#define CPHA 2
5077+#define CPOL 3
5078+#define MSTR 4
5079+#define DORD 5
5080+#define SPE 6
5081+#define SPIE 7
5082+
5083+#define SPSR _SFR_IO8(0x2D)
5084+#define SPI2X 0
5085+#define WCOL 6
5086+#define SPIF 7
5087+
5088+#define SPDR _SFR_IO8(0x2E)
5089+
5090+#define T2MDR _SFR_IO8(0x2F)
5091+
5092+#define LFRR _SFR_IO8(0x30)
5093+
5094+/* Reserved [0x31] */
5095+
5096+#define LFCDR _SFR_IO8(0x32)
5097+#define LFDO 0
5098+#define LFRST 6
5099+#define LFSCE 7
5100+
5101+#define SMCR _SFR_IO8(0x33)
5102+#define SE 0
5103+#define SM0 1
5104+#define SM1 2
5105+#define SM2 3
5106+
5107+#define MCUSR _SFR_IO8(0x34)
5108+#define PORF 0
5109+#define EXTRF 1
5110+#define BORF 2
5111+#define WDRF 3
5112+#define TSRF 5
5113+
5114+#define MCUCR _SFR_IO8(0x35)
5115+#define IVCE 0
5116+#define IVSEL 1
5117+#define PUD 4
5118+
5119+#define LFRB _SFR_IO8(0x36)
5120+
5121+#define SPMCSR _SFR_IO8(0x37)
5122+#define SELFPRGEN 0
5123+#define PGERS 1
5124+#define PGWRT 2
5125+#define BLBSET 3
5126+#define RWWSRE 4
5127+#define RWWSB 6
5128+#define SPMIE 7
5129+
5130+#define T1CR _SFR_IO8(0x38)
5131+#define T1PS0 0
5132+#define T1PS1 1
5133+#define T1PS2 2
5134+#define T1CS0 3
5135+#define T1CS1 4
5136+#define T1CS2 5
5137+#define T1IE 7
5138+
5139+#define T0CR _SFR_IO8(0x39)
5140+#define T0PAS0 0
5141+#define T0PAS1 1
5142+#define T0PAS2 2
5143+#define T0IE 3
5144+#define T0PR 4
5145+#define T0PBS0 5
5146+#define T0PBS1 6
5147+#define T0PBS2 7
5148+
5149+/* Reserved [0x3A] */
5150+
5151+#define CMIMR _SFR_IO8(0x3B)
5152+#define ECIE 0
5153+
5154+#define CLKPR _SFR_IO8(0x3C)
5155+#define CLKPS0 0
5156+#define CLKPS1 1
5157+#define CLKPS2 2
5158+#define CLTPS0 3
5159+#define CLTPS1 4
5160+#define CLTPS2 5
5161+#define CLPCE 7
5162+
5163+/* SP [0x3D..0x3E] */
5164+
5165+/* SREG [0x3F] */
5166+
5167+#define WDTCR _SFR_MEM8(0x60)
5168+#define WDPS0 0
5169+#define WDPS1 1
5170+#define WDPS2 2
5171+#define WDE 3
5172+#define WDCE 4
5173+
5174+#define SIMSK _SFR_MEM8(0x61)
5175+#define MSIE 0
5176+
5177+/* Reserved [0x62..0x63] */
5178+
5179+#define TSCR _SFR_MEM8(0x64)
5180+#define TSSD 0
5181+
5182+#define SRCCAL _SFR_MEM8(0x65)
5183+
5184+#define FRCCAL _SFR_MEM8(0x66)
5185+
5186+#define MSVCAL _SFR_MEM8(0x67)
5187+
5188+/* Reserved [0x68] */
5189+
5190+#define EICRA _SFR_MEM8(0x69)
5191+#define ISC00 0
5192+#define ISC01 1
5193+#define ISC10 2
5194+#define ISC11 3
5195+
5196+#define PCMSK0 _SFR_MEM8(0x6A)
5197+#define PCINT0 0
5198+#define PCINT1 1
5199+#define PCINT2 2
5200+#define PCINT3 3
5201+#define PCINT4 4
5202+#define PCINT5 5
5203+#define PCINT6 6
5204+#define PCINT7 7
5205+
5206+#define PCMSK1 _SFR_MEM8(0x6B)
5207+#define PCINT8 0
5208+#define PCINT9 1
5209+#define PCINT10 2
5210+
5211+#define PCMSK2 _SFR_MEM8(0x6C)
5212+#define PCINT16 0
5213+#define PCINT17 1
5214+#define PCINT18 2
5215+#define PCINT19 3
5216+#define PCINT20 4
5217+#define PCINT21 5
5218+#define PCINT22 6
5219+#define PCINT23 7
5220+
5221+/* Reserved [0x6D] */
5222+
5223+#define T2ICRL _SFR_MEM8(0x6E)
5224+
5225+#define T2ICR _SFR_MEM8(0x6F)
5226+
5227+/* Combine T2CORL and T2CORH */
5228+#define T2COR _SFR_MEM16(0x70)
5229+
5230+#define T2CORL _SFR_MEM8(0x70)
5231+#define T2CORH _SFR_MEM8(0x71)
5232+
5233+#define T2MRA _SFR_MEM8(0x72)
5234+#define T2CS0 0
5235+#define T2CS1 1
5236+#define T2CS2 2
5237+#define T2CE0 3
5238+#define T2CE1 4
5239+#define T2CNC 5
5240+#define T2TP0 6
5241+#define T2TP1 7
5242+
5243+#define T2MRB _SFR_MEM8(0x73)
5244+#define T2M0 0
5245+#define T2M1 1
5246+#define T2M2 2
5247+#define T2M3 3
5248+#define T2TOP 4
5249+#define T2CPOL 6
5250+#define T2SSIE 7
5251+
5252+#define T2IMR _SFR_MEM8(0x74)
5253+#define T2OIM 0
5254+#define T2CIM 1
5255+#define T2CPIM 2
5256+#define T2RXIM 3
5257+#define T2TXIM 4
5258+#define T2TCIM 5
5259+
5260+/* Reserved [0x75] */
5261+
5262+/* Combine T3ICRL and T3ICRH */
5263+#define T3ICR _SFR_MEM16(0x76)
5264+
5265+#define T3ICRL _SFR_MEM8(0x76)
5266+#define T3ICRH _SFR_MEM8(0x77)
5267+
5268+/* Combine T3CORAL and T3CORAH */
5269+#define T3CORA _SFR_MEM16(0x78)
5270+
5271+#define T3CORAL _SFR_MEM8(0x78)
5272+#define T3CORAH _SFR_MEM8(0x79)
5273+
5274+/* Combine T3CORBL and T3CORBH */
5275+#define T3CORB _SFR_MEM16(0x7A)
5276+
5277+#define T3CORBL _SFR_MEM8(0x7A)
5278+#define T3CORBH _SFR_MEM8(0x7B)
5279+
5280+#define T3MRA _SFR_MEM8(0x7C)
5281+#define T3CS0 0
5282+#define T3CS1 1
5283+#define T3CS2 2
5284+#define T3CE0 3
5285+#define T3CE1 4
5286+#define T3CNC 5
5287+#define T3ICS0 6
5288+#define T3ICS1 7
5289+
5290+#define T3MRB _SFR_MEM8(0x7D)
5291+#define T3M0 0
5292+#define T3M1 1
5293+#define T3M2 2
5294+#define T3TOP 4
5295+
5296+#define T3CRB _SFR_MEM8(0x7E)
5297+#define T3CTMA 0
5298+#define T3SAMA 1
5299+#define T3CRMA 2
5300+#define T3CTMB 3
5301+#define T3SAMB 4
5302+#define T3CRMB 5
5303+#define T3CPRM 6
5304+
5305+#define T3IMR _SFR_MEM8(0x7F)
5306+#define T3OIM 0
5307+#define T3CAIM 1
5308+#define T3CBIM 2
5309+#define T3CPIM 3
5310+
5311+/* Reserved [0x80] */
5312+
5313+#define LFIMR _SFR_MEM8(0x81)
5314+#define LFWIM 0
5315+#define LFBIM 1
5316+#define LFEIM 2
5317+
5318+#define LFRCR _SFR_MEM8(0x82)
5319+#define LFEN 0
5320+#define LFBM 1
5321+#define LFWM0 2
5322+#define LFWM1 3
5323+#define LFRSS 4
5324+#define LFCS0 5
5325+#define LFCS1 6
5326+#define LFCS2 7
5327+
5328+#define LFHCR _SFR_MEM8(0x83)
5329+
5330+/* Combine LFIDCL and LFIDCH */
5331+#define LFIDC _SFR_MEM16(0x84)
5332+
5333+#define LFIDCL _SFR_MEM8(0x84)
5334+#define LFIDCH _SFR_MEM8(0x85)
5335+
5336+/* Combine LFCALL and LFCALH */
5337+#define LFCAL _SFR_MEM16(0x86)
5338+
5339+#define LFCALL _SFR_MEM8(0x86)
5340+#define LFCALH _SFR_MEM8(0x87)
5341+
5342+
5343+
5344+/* Interrupt vectors */
5345+/* Vector 0 is the reset vector */
5346+/* External Interrupt Request 0 */
5347+#define INT0_vect _VECTOR(1)
5348+#define INT0_vect_num 1
5349+
5350+/* External Interrupt Request 1 */
5351+#define INT1_vect _VECTOR(2)
5352+#define INT1_vect_num 2
5353+
5354+/* Pin Change Interrupt Request 0 */
5355+#define PCINT0_vect _VECTOR(3)
5356+#define PCINT0_vect_num 3
5357+
5358+/* Pin Change Interrupt Request 1 */
5359+#define PCINT1_vect _VECTOR(4)
5360+#define PCINT1_vect_num 4
5361+
5362+/* Pin Change Interrupt Request 2 */
5363+#define PCINT2_vect _VECTOR(5)
5364+#define PCINT2_vect_num 5
5365+
5366+/* Voltage Monitor Interrupt */
5367+#define INTVM_vect _VECTOR(6)
5368+#define INTVM_vect_num 6
5369+
5370+/* Sensor Interface Interrupt */
5371+#define SENINT_vect _VECTOR(7)
5372+#define SENINT_vect_num 7
5373+
5374+/* Timer0 Interval Interrupt */
5375+#define INTT0_vect _VECTOR(8)
5376+#define INTT0_vect_num 8
5377+
5378+/* LF-Receiver Wake-up Interrupt */
5379+#define LFWP_vect _VECTOR(9)
5380+#define LFWP_vect_num 9
5381+
5382+/* Timer/Counter3 Capture Event */
5383+#define T3CAP_vect _VECTOR(10)
5384+#define T3CAP_vect_num 10
5385+
5386+/* Timer/Counter3 Compare Match A */
5387+#define T3COMA_vect _VECTOR(11)
5388+#define T3COMA_vect_num 11
5389+
5390+/* Timer/Counter3 Compare Match B */
5391+#define T3COMB_vect _VECTOR(12)
5392+#define T3COMB_vect_num 12
5393+
5394+/* Timer/Counter3 Overflow */
5395+#define T3OVF_vect _VECTOR(13)
5396+#define T3OVF_vect_num 13
5397+
5398+/* Timer/Counter2 Capture Event */
5399+#define T2CAP_vect _VECTOR(14)
5400+#define T2CAP_vect_num 14
5401+
5402+/* Timer/Counter2 Compare Match */
5403+#define T2COM_vect _VECTOR(15)
5404+#define T2COM_vect_num 15
5405+
5406+/* Timer/Counter2 Overflow */
5407+#define T2OVF_vect _VECTOR(16)
5408+#define T2OVF_vect_num 16
5409+
5410+/* SPI Serial Transfer Complete */
5411+#define SPISTC_vect _VECTOR(17)
5412+#define SPISTC_vect_num 17
5413+
5414+/* LF Receive Buffer Interrupt */
5415+#define LFRXB_vect _VECTOR(18)
5416+#define LFRXB_vect_num 18
5417+
5418+/* Timer1 Interval Interrupt */
5419+#define INTT1_vect _VECTOR(19)
5420+#define INTT1_vect_num 19
5421+
5422+/* Timer2 SSI Receive Buffer Interrupt */
5423+#define T2RXB_vect _VECTOR(20)
5424+#define T2RXB_vect_num 20
5425+
5426+/* Timer2 SSI Transmit Buffer Interrupt */
5427+#define T2TXB_vect _VECTOR(21)
5428+#define T2TXB_vect_num 21
5429+
5430+/* Timer2 SSI Transmit Complete Interrupt */
5431+#define T2TXC_vect _VECTOR(22)
5432+#define T2TXC_vect_num 22
5433+
5434+/* LF-Receiver End of Burst Interrupt */
5435+#define LFREOB_vect _VECTOR(23)
5436+#define LFREOB_vect_num 23
5437+
5438+/* External Input Clock break down Interrupt */
5439+#define EXCM_vect _VECTOR(24)
5440+#define EXCM_vect_num 24
5441+
5442+/* EEPROM Ready Interrupt */
5443+#define EEREADY_vect _VECTOR(25)
5444+#define EEREADY_vect_num 25
5445+
5446+/* Store Program Memory Ready */
5447+#define SPM_RDY_vect _VECTOR(26)
5448+#define SPM_RDY_vect_num 26
5449+
5450+#define _VECTORS_SIZE 54
5451+
5452+
5453+/* Constants */
5454+
5455+#define SPM_PAGESIZE 64
5456+#define FLASHEND 0x1FFF
5457+#define RAMSTART 0x0100
5458+#define RAMSIZE 512
5459+#define RAMEND 0x02FF
5460+#define E2START 0
5461+#define E2SIZE 320
5462+#define E2PAGESIZE 4
5463+#define E2END 0x013F
5464+#define XRAMEND RAMEND
5465+
5466+
5467+/* Fuses */
5468+
5469+#define FUSE_MEMORY_SIZE 2
5470+
5471+/* Low Fuse Byte */
5472+#define FUSE_TSRDI (unsigned char)~_BV(0)
5473+#define FUSE_BODEN (unsigned char)~_BV(1)
5474+#define FUSE_FRCFS (unsigned char)~_BV(2)
5475+#define FUSE_WDRCON (unsigned char)~_BV(3)
5476+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
5477+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
5478+#define FUSE_CKOUT (unsigned char)~_BV(6)
5479+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
5480+
5481+/* High Fuse Byte */
5482+#define FUSE_BOOTRST (unsigned char)~_BV(0)
5483+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
5484+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
5485+#define FUSE_EESAVE (unsigned char)~_BV(3)
5486+#define FUSE_WDTON (unsigned char)~_BV(4)
5487+#define FUSE_SPIEN (unsigned char)~_BV(5)
5488+#define FUSE_DWEN (unsigned char)~_BV(6)
5489+#define FUSE_EELOCK (unsigned char)~_BV(7)
5490+
5491+
5492+/* Lock Bits */
5493+#define __LOCK_BITS_EXIST
5494+#define __BOOT_LOCK_BITS_0_EXIST
5495+#define __BOOT_LOCK_BITS_1_EXIST
5496+
5497+
5498+/* Signature */
5499+#define SIGNATURE_0 0x1E
5500+#define SIGNATURE_1 0x93
5501+#define SIGNATURE_2 0x82
5502+
5503+
5504+#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */
5505+
5506diff -urN avr-libc-1.8.0.orig/include/avr/io.h avr-libc-1.8.0/include/avr/io.h
5507--- avr-libc-1.8.0.orig/include/avr/io.h 2013-01-18 09:49:50.000000000 +0100
5508+++ avr-libc-1.8.0/include/avr/io.h 2013-01-18 09:50:25.000000000 +0100
5509@@ -162,8 +162,12 @@
5510 # include <avr/iom1284p.h>
5511 #elif defined (__AVR_ATmega128RFA1__)
5512 # include <avr/iom128rfa1.h>
5513+#elif defined (__AVR_ATmega128RFA2__)
5514+# include <avr/iom128rfa2.h>
5515 #elif defined (__AVR_ATmega128RFR2__)
5516 # include <avr/iom128rfr2.h>
5517+#elif defined (__AVR_ATmega256RFA2__)
5518+# include <avr/iom256rfa2.h>
5519 #elif defined (__AVR_ATmega256RFR2__)
5520 # include <avr/iom256rfr2.h>
5521 #elif defined (__AVR_ATmega2560__)
5522@@ -188,6 +192,8 @@
5523 # include <avr/iousb1286.h>
5524 #elif defined (__AVR_AT90USB1287__)
5525 # include <avr/iousb1287.h>
5526+#elif defined (__AVR_ATmega64RFA2__)
5527+# include <avr/iom64rfa2.h>
5528 #elif defined (__AVR_ATmega64RFR2__)
5529 # include <avr/iom64rfr2.h>
5530 #elif defined (__AVR_ATmega64__)
5531@@ -336,6 +342,8 @@
5532 # include <avr/iom16hvb.h>
5533 #elif defined (__AVR_ATmega16HVBREVB__)
5534 # include <avr/iom16hvbrevb.h>
5535+#elif defined (__AVR_ATmega26HVG__)
5536+# include <avr/iom26hvg.h>
5537 #elif defined (__AVR_ATmega8__)
5538 # include <avr/iom8.h>
5539 #elif defined (__AVR_ATmega8A__)
5540@@ -354,6 +362,8 @@
5541 # include <avr/iom88a.h>
5542 #elif defined (__AVR_ATmega88P__)
5543 # include <avr/iom88p.h>
5544+#elif defined (__AVR_ATmega48HVF__)
5545+# include <avr/iom48hvf.h>
5546 #elif defined (__AVR_ATmega88PA__)
5547 # include <avr/iom88pa.h>
5548 #elif defined (__AVR_ATmega8515__)
5549@@ -424,6 +434,8 @@
5550 # include <avr/iotn84.h>
5551 #elif defined (__AVR_ATtiny84A__)
5552 # include <avr/iotn84a.h>
5553+#elif defined (__AVR_ATtiny841__)
5554+# include <avr/iotn841.h>
5555 #elif defined (__AVR_ATtiny261__)
5556 # include <avr/iotn261.h>
5557 #elif defined (__AVR_ATtiny261A__)
5558@@ -452,6 +464,18 @@
5559 # include <avr/iotn1634.h>
5560 #elif defined (__AVR_AT90SCR100__)
5561 # include <avr/io90scr100.h>
5562+#elif defined (__AVR_ATMXT112SL__)
5563+# include <avr/iomxt112sl.h>
5564+#elif defined (__AVR_ATMXT224__)
5565+# include <avr/iomxt224.h>
5566+#elif defined (__AVR_ATMXT224E__)
5567+# include <avr/iomxt224e.h>
5568+#elif defined (__AVR_ATMXT336S__)
5569+# include <avr/iomxt336s.h>
5570+#elif defined (__AVR_ATMXT540S__)
5571+# include <avr/iomxt540s.h>
5572+#elif defined (__AVR_ATMXT540SREVA__)
5573+# include <avr/iomxt540sreva.h>
5574 #elif defined (__AVR_ATxmega16A4__)
5575 # include <avr/iox16a4.h>
5576 #elif defined (__AVR_ATxmega16A4U__)
5577@@ -468,5 +492,7 @@
5578 #elif defined (__AVR_ATxmega32E5__)
5579 # include <avr/iox32e5.h>
5580+#elif defined (__AVR_ATxmega32X1__)
5581+# include <avr/iox32x1.h>
5582 #elif defined (__AVR_ATxmega64A1__)
5583 # include <avr/iox64a1.h>
5584 #elif defined (__AVR_ATxmega64A1U__)
5585@@ -540,12 +562,16 @@
5586 # include <avr/iox384d3.h>
5587 #elif defined (__AVR_ATA5790__)
5588 # include <avr/ioa5790.h>
5589+#elif defined (__AVR_ATA5790N__)
5590+# include <avr/ioa5790n.h>
5591 #elif defined (__AVR_ATA5272__)
5592 # include <avr/ioa5272.h>
5593 #elif defined (__AVR_ATA5505__)
5594 # include <avr/ioa5505.h>
5595 #elif defined (__AVR_ATA5795__)
5596 # include <avr/ioa5795.h>
5597+#elif defined (__AVR_ATA5831__)
5598+# include <avr/ioa5831.h>
5599 #elif defined (__AVR_ATA6285__)
5600 # include <avr/ioa6285.h>
5601 #elif defined (__AVR_ATA6286__)
5602diff -urN avr-libc-1.8.0.orig/include/avr/iom103.h avr-libc-1.8.0/include/avr/iom103.h
5603--- avr-libc-1.8.0.orig/include/avr/iom103.h 2011-12-29 09:51:50.000000000 +0100
5604+++ avr-libc-1.8.0/include/avr/iom103.h 2013-01-18 09:50:25.000000000 +0100
5605@@ -202,7 +202,7 @@
5606 /* Timer/Counter Interrupt MaSK register */
5607 #define TIMSK _SFR_IO8(0x37)
5608
5609