--- /dev/null
+diff -urN avr-libc-1.8.0.orig/include/avr/builtins.h avr-libc-1.8.0/include/avr/builtins.h
+--- avr-libc-1.8.0.orig/include/avr/builtins.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/builtins.h 2013-01-18 09:50:25.000000000 +0100
+@@ -1,4 +1,5 @@
+-/* Copyright (c) 2008 Anatoly Sokolv
++/* Copyright (c) 2008 Anatoly Sokolov
++ Copyright (c) 2010 Joerg Wunsch
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+@@ -28,74 +29,85 @@
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+-/* $Id$ */
++/* $Id: builtins.h.in 2103 2010-03-17 05:16:10Z joerg_wunsch $ */
+
+ /*
+- avr/builtins.h -
++ avr/builtins.h - Intrinsic functions built into the compiler
+ */
+
+ #ifndef _AVR_BUILTINS_H_
+ #define _AVR_BUILTINS_H_
+
++#ifndef __HAS_DELAY_CYCLES
++#define __HAS_DELAY_CYCLES 1
++#endif
++
+ /** \file */
+ /** \defgroup avr_builtins <avr/builtins.h>: GCC builtins
+ \code #include <avr/builtins.h> \endcode
+
+- This header file declares avr builtins. */
++ This header file declares AVR builtins.
++ All the functions documented here are built into the
++ compiler, and cause it to emit the corresponding assembly
++ code instructions.
++*/
+
+-/**
++/**
+ \ingroup avr_builtins
+
+ Enables interrupts by setting the global interrupt mask. */
+ extern void __builtin_avr_sei(void);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+ Disables all interrupts by clearing the global interrupt mask. */
+ extern void __builtin_avr_cli(void);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits a \c SLEEP instruction. */
+
+ extern void __builtin_avr_sleep(void);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits a WDR (watchdog reset) instruction. */
+ extern void __builtin_avr_wdr(void);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits a SWAP (nibble swap) instruction on __b. */
+ extern unsigned char __builtin_avr_swap(unsigned char __b);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits an FMUL (fractional multiply unsigned) instruction. */
+ extern unsigned int __builtin_avr_fmul(unsigned char __a, unsigned char __b);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits an FMUL (fractional multiply signed) instruction. */
+ extern int __builtin_avr_fmuls(char __a, char __b);
+
+-/**
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits an FMUL (fractional multiply signed with unsigned) instruction. */
+ extern int __builtin_avr_fmulsu(char __a, unsigned char __b);
+
+-/**
++#if __HAS_DELAY_CYCLES || defined(__DOXYGEN__)
++/**
+ \ingroup avr_builtins
+
+- TODO. */
++ Emits a sequence of instructions causing the CPU to spend
++ \c __n cycles on it. */
+ extern void __builtin_avr_delay_cycles(unsigned long __n);
++#endif
+
+-#endif /* _AVR_BUILTINS_H_ */
+\ Brak znaku nowej linii na końcu pliku
++#endif /* _AVR_BUILTINS_H_ */
+diff -urN avr-libc-1.8.0.orig/include/avr/eeprom.h avr-libc-1.8.0/include/avr/eeprom.h
+--- avr-libc-1.8.0.orig/include/avr/eeprom.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/eeprom.h 2013-01-18 09:50:25.000000000 +0100
+@@ -107,9 +107,13 @@
+ # define _EEPROM_SUFFIX _m1284p
+ #elif defined (__AVR_ATmega128RFA1__)
+ # define _EEPROM_SUFFIX _m128rfa1
++#elif defined (__AVR_ATmega128RFA2__)
++# define _EEPROM_SUFFIX _m128rfa2
+ #elif defined (__AVR_ATmega128RFR2__)
+ # define _EEPROM_SUFFIX _m128rfr2
+ #elif defined (__AVR_ATmega256RFA2__)
++# define _EEPROM_SUFFIX _m256rfa2
++#elif defined (__AVR_ATmega256RFR2__)
+ # define _EEPROM_SUFFIX _m256rfr2
+ #elif defined (__AVR_ATmega2560__)
+ # define _EEPROM_SUFFIX _m2560
+@@ -133,6 +137,8 @@
+ # define _EEPROM_SUFFIX _usb1286
+ #elif defined (__AVR_AT90USB1287__)
+ # define _EEPROM_SUFFIX _usb1287
++#elif defined (__AVR_ATmega64RFA2__)
++# define _EEPROM_SUFFIX _m64rfa2
+ #elif defined (__AVR_ATmega64RFR2__)
+ # define _EEPROM_SUFFIX _m64rfr2
+ #elif defined (__AVR_ATmega64__)
+@@ -281,6 +287,8 @@
+ # define _EEPROM_SUFFIX _m16hvb
+ #elif defined (__AVR_ATmega16HVBREVB__)
+ # define _EEPROM_SUFFIX _m16hvbrevb
++#elif defined (__AVR_ATmega26HVG__)
++# define _EEPROM_SUFFIX _m26hvg
+ #elif defined (__AVR_ATmega8__)
+ # define _EEPROM_SUFFIX _m8
+ #elif defined (__AVR_ATmega8A__)
+@@ -289,6 +297,8 @@
+ # define _EEPROM_SUFFIX _m48
+ #elif defined (__AVR_ATmega48A__)
+ # define _EEPROM_SUFFIX _m48a
++#elif defined (__AVR_ATmega48HVF__)
++# define _EEPROM_SUFFIX _m48hvf
+ #elif defined (__AVR_ATmega48PA__)
+ # define _EEPROM_SUFFIX _m48pa
+ #elif defined (__AVR_ATmega48P__)
+@@ -357,6 +367,8 @@
+ # define _EEPROM_SUFFIX _tn84
+ #elif defined (__AVR_ATtiny84A__)
+ # define _EEPROM_SUFFIX _tn84a
++#elif defined (__AVR_ATtiny841__)
++# define _EEPROM_SUFFIX _tn841
+ #elif defined (__AVR_ATtiny261__)
+ # define _EEPROM_SUFFIX _tn261
+ #elif defined (__AVR_ATtiny261A__)
+@@ -401,12 +413,10 @@
+ # define _EEPROM_SUFFIX _x32c4
+ #elif defined (__AVR_ATxmega32D4__)
+ # define _EEPROM_SUFFIX _x32d4
+-#elif defined (__AVR_ATxmega8E5__)
+-#define _EEPROM_SUFFIX _x8e5
+-#elif defined (__AVR_ATxmega16E5__)
+-#define _EEPROM_SUFFIX _x16e5
+ #elif defined (__AVR_ATxmega32E5__)
+ # define _EEPROM_SUFFIX _x32e5
++#elif defined (__AVR_ATxmega32X1__)
++# define _EEPROM_SUFFIX _x32x1
+ #elif defined (__AVR_ATxmega64A1__)
+ # define _EEPROM_SUFFIX _x64a1
+ #elif defined (__AVR_ATxmega64A1U__)
+@@ -483,8 +493,12 @@
+ # define _EEPROM_SUFFIX _a6289
+ #elif defined (__AVR_ATA5790__)
+ # define _EEPROM_SUFFIX _a5790
++#elif defined (__AVR_ATA5790N__)
++# define _EEPROM_SUFFIX _a5790n
+ #elif defined (__AVR_ATA5795__)
+ # define _EEPROM_SUFFIX _a5795
++#elif defined (__AVR_ATA5831__)
++# define _EEPROM_SUFFIX _a5831
+ /* avr1: the following only supported for assembler programs */
+ #elif defined (__AVR_ATtiny28__)
+ # define _EEPROM_SUFFIX _tn28
+diff -urN avr-libc-1.8.0.orig/include/avr/io90pwm161.h avr-libc-1.8.0/include/avr/io90pwm161.h
+--- avr-libc-1.8.0.orig/include/avr/io90pwm161.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/io90pwm161.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,865 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_AT90PWM161_H_INCLUDED
++#define _AVR_AT90PWM161_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "io90pwm161.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define ACSR _SFR_IO8(0x00)
++#define AC1O 1
++#define AC2O 2
++#define AC3O 3
++#define AC1IF 5
++#define AC2IF 6
++#define AC3IF 7
++
++#define TIMSK1 _SFR_IO8(0x01)
++#define TOIE1 0
++#define ICIE1 5
++
++#define TIFR1 _SFR_IO8(0x02)
++#define TOV1 0
++#define ICF1 5
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define ADCSRA _SFR_IO8(0x06)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_IO8(0x07)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ADTS3 3
++#define ADSSEN 4
++#define ADNCDIS 6
++#define ADHSM 7
++
++#define ADMUX _SFR_IO8(0x08)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PIM0 _SFR_IO8(0x0F)
++#define PEOPE0 0
++#define PEOEPE0 1
++#define PEVE0A 3
++#define PEVE0B 4
++
++#define PIFR0 _SFR_IO8(0x10)
++#define PEOP0 0
++#define PRN00 1
++#define PRN01 2
++#define PEV0A 3
++#define PEV0B 4
++#define POAC0A 6
++#define POAC0B 7
++
++#define PCNF0 _SFR_IO8(0x11)
++#define PCLKSEL0 1
++#define POP0 2
++#define PMODE00 3
++#define PMODE01 4
++#define PLOCK0 5
++#define PALOCK0 6
++#define PFIFTY0 7
++
++#define PCTL0 _SFR_IO8(0x12)
++#define PRUN0 0
++#define PCCYC0 1
++#define PAOC0A 3
++#define PAOC0B 4
++#define PBFM00 2
++#define PBFM01 5
++#define PPRE00 6
++#define PPRE01 7
++
++#define PIM2 _SFR_IO8(0x13)
++#define PEOPE2 0
++#define PEOEPE2 1
++#define PEVE2A 3
++#define PEVE2B 4
++#define PSEIE2 5
++
++#define PIFR2 _SFR_IO8(0x14)
++#define PEOP2 0
++#define PRN20 1
++#define PRN21 2
++#define PEV2A 3
++#define PEV2B 4
++#define PSEI2 5
++#define POAC2A 6
++#define POAC2B 7
++
++#define PCNF2 _SFR_IO8(0x15)
++#define POME2 0
++#define PCLKSEL2 1
++#define POP2 2
++#define PMODE20 3
++#define PMODE21 4
++#define PLOCK2 5
++#define PALOCK2 6
++#define PFIFTY2 7
++
++#define PCTL2 _SFR_IO8(0x16)
++#define PRUN2 0
++#define PCCYC2 1
++#define PARUN2 2
++#define PAOC2A 3
++#define PAOC2B 4
++#define PBFM2 5
++#define PPRE20 6
++#define PPRE21 7
++
++#define SPCR _SFR_IO8(0x17)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x18)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define GPIOR0 _SFR_IO8(0x19)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define GPIOR1 _SFR_IO8(0x1A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x1B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++#define EEPAGE 6
++#define NVMBSY 7
++
++#define EEDR _SFR_IO8(0x1D)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x1E)
++
++#define EEARL _SFR_IO8(0x1E)
++#define EEARH _SFR_IO8(0x1F)
++
++#define EIFR _SFR_IO8(0x20)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++
++#define EIMSK _SFR_IO8(0x21)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++
++/* Combine OCR0SBL and OCR0SBH */
++#define OCR0SB _SFR_IO16(0x22)
++
++#define OCR0SBL _SFR_IO8(0x22)
++#define OCR0SBH _SFR_IO8(0x23)
++
++/* Combine OCR0RBL and OCR0RBH */
++#define OCR0RB _SFR_IO16(0x24)
++
++#define OCR0RBL _SFR_IO8(0x24)
++#define OCR0RBH _SFR_IO8(0x25)
++
++/* Combine OCR2SBL and OCR2SBH */
++#define OCR2SB _SFR_IO16(0x26)
++
++#define OCR2SBL _SFR_IO8(0x26)
++#define OCR2SBH _SFR_IO8(0x27)
++
++/* Combine OCR2RBL and OCR2RBH */
++#define OCR2RB _SFR_IO16(0x28)
++
++#define OCR2RBL _SFR_IO8(0x28)
++#define OCR2RBH _SFR_IO8(0x29)
++
++/* Combine OCR0RAL and OCR0RAH */
++#define OCR0RA _SFR_IO16(0x2A)
++
++#define OCR0RAL _SFR_IO8(0x2A)
++#define OCR0RAH _SFR_IO8(0x2B)
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x2C)
++#endif
++#define ADCW _SFR_IO16(0x2C)
++
++#define ADCL _SFR_IO8(0x2C)
++#define ADCH _SFR_IO8(0x2D)
++
++/* Combine OCR2RAL and OCR2RAH */
++#define OCR2RA _SFR_IO16(0x2E)
++
++#define OCR2RAL _SFR_IO8(0x2E)
++#define OCR2RAH _SFR_IO8(0x2F)
++
++/* Reserved [0x30..0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define CKRC81 2
++#define RSTDIS 3
++#define PUD 4
++
++#define SPDR _SFR_IO8(0x36)
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++#define DACL _SFR_IO8(0x38)
++#define DACL0 0
++#define DACL1 1
++#define DACL2 2
++#define DACL3 3
++#define DACL4 4
++#define DACL5 5
++#define DACL6 6
++#define DACL7 7
++
++#define DACH _SFR_IO8(0x39)
++#define DACH0 0
++#define DACH1 1
++#define DACH2 2
++#define DACH3 3
++#define DACH4 4
++#define DACH5 5
++#define DACH6 6
++#define DACH7 7
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_IO16(0x3A)
++
++#define TCNT1L _SFR_IO8(0x3A)
++#define TCNT1H _SFR_IO8(0x3B)
++
++/* Reserved [0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++/* Combine OCR0SAL and OCR0SAH */
++#define OCR0SA _SFR_MEM16(0x60)
++
++#define OCR0SAL _SFR_MEM8(0x60)
++#define OCR0SAH _SFR_MEM8(0x61)
++
++#define PFRC0A _SFR_MEM8(0x62)
++#define PRFM0A0 0
++#define PRFM0A1 1
++#define PRFM0A2 2
++#define PRFM0A3 3
++#define PFLTE0A 4
++#define PELEV0A 5
++#define PISEL0A 6
++#define PCAE0A 7
++
++#define PFRC0B _SFR_MEM8(0x63)
++#define PRFM0B0 0
++#define PRFM0B1 1
++#define PRFM0B2 2
++#define PRFM0B3 3
++#define PFLTE0B 4
++#define PELEV0B 5
++#define PISEL0B 6
++#define PCAE0B 7
++
++/* Combine OCR2SAL and OCR2SAH */
++#define OCR2SA _SFR_MEM16(0x64)
++
++#define OCR2SAL _SFR_MEM8(0x64)
++#define OCR2SAH _SFR_MEM8(0x65)
++
++#define PFRC2A _SFR_MEM8(0x66)
++#define PRFM2A0 0
++#define PRFM2A1 1
++#define PRFM2A2 2
++#define PRFM2A3 3
++#define PFLTE2A 4
++#define PELEV2A 5
++#define PISEL2A 6
++#define PCAE2A 7
++
++#define PFRC2B _SFR_MEM8(0x67)
++#define PRFM2B0 0
++#define PRFM2B1 1
++#define PRFM2B2 2
++#define PRFM2B3 3
++#define PFLTE2B 4
++#define PELEV2B 5
++#define PISEL2B 6
++#define PCAE2B 7
++
++/* Combine PICR0L and PICR0H */
++#define PICR0 _SFR_MEM16(0x68)
++
++#define PICR0L _SFR_MEM8(0x68)
++#define PICR0H _SFR_MEM8(0x69)
++
++#define PSOC0 _SFR_MEM8(0x6A)
++#define POEN0A 0
++#define POEN0B 2
++#define PSYNC00 4
++#define PSYNC01 5
++#define PISEL0B1 6
++#define PISEL0A1 7
++
++/* Reserved [0x6B] */
++
++#define PICR2L _SFR_MEM8(0x6C)
++
++#define PICR2H _SFR_MEM8(0x6D)
++#define PICR28 0
++#define PICR29 1
++#define PICR210 2
++#define PICR211 3
++#define PCST2 7
++
++#define PSOC2 _SFR_MEM8(0x6E)
++#define POEN2A 0
++#define POEN2C 1
++#define POEN2B 2
++#define POEN2D 3
++#define PSYNC20 4
++#define PSYNC21 5
++#define POS22 6
++#define POS23 7
++
++#define POM2 _SFR_MEM8(0x6F)
++#define POMV2A0 0
++#define POMV2A1 1
++#define POMV2A2 2
++#define POMV2A3 3
++#define POMV2B0 4
++#define POMV2B1 5
++#define POMV2B2 6
++#define POMV2B3 7
++
++#define PCNFE2 _SFR_MEM8(0x70)
++#define PISEL2B1 0
++#define PISEL2A1 1
++#define PELEV2B1 2
++#define PELEV2A1 3
++#define PBFM21 4
++#define PASDLK20 5
++#define PASDLK21 6
++#define PASDLK22 7
++
++#define PASDLY2 _SFR_MEM8(0x71)
++
++/* Reserved [0x72..0x75] */
++
++#define DACON _SFR_MEM8(0x76)
++#define DAEN 0
++#define DALA 2
++#define DATS0 4
++#define DATS1 5
++#define DATS2 6
++#define DAATE 7
++
++#define DIDR0 _SFR_MEM8(0x77)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x78)
++#define ADC9D 0
++#define ADC10D 1
++#define AMP0POSD 2
++#define ACMP1MD 3
++
++#define AMP0CSR _SFR_MEM8(0x79)
++#define AMP0TS0 0
++#define AMP0TS1 1
++#define AMP0GS 3
++#define AMP0G0 4
++#define AMP0G1 5
++#define AMP0IS 6
++#define AMP0EN 7
++
++#define AC1ECON _SFR_MEM8(0x7A)
++#define AC1H0 0
++#define AC1H1 1
++#define AC1H2 2
++#define AC1ICE 3
++#define AC1OE 4
++#define AC1OI 5
++
++#define AC2ECON _SFR_MEM8(0x7B)
++#define AC2H0 0
++#define AC2H1 1
++#define AC2H2 2
++#define AC2OE 4
++#define AC2OI 5
++
++#define AC3ECON _SFR_MEM8(0x7C)
++#define AC3H0 0
++#define AC3H1 1
++#define AC3H2 2
++#define AC3OE 4
++#define AC3OI 5
++
++#define AC1CON _SFR_MEM8(0x7D)
++#define AC1M0 0
++#define AC1M1 1
++#define AC1M2 2
++#define AC1IS0 4
++#define AC1IS1 5
++#define AC1IE 6
++#define AC1EN 7
++
++#define AC2CON _SFR_MEM8(0x7E)
++#define AC2M0 0
++#define AC2M1 1
++#define AC2M2 2
++#define AC2IS0 4
++#define AC2IS1 5
++#define AC2IE 6
++#define AC2EN 7
++
++#define AC3CON _SFR_MEM8(0x7F)
++#define AC3M0 0
++#define AC3M1 1
++#define AC3M2 2
++#define AC3OEA 3
++#define AC3IS0 4
++#define AC3IS1 5
++#define AC3IE 6
++#define AC3EN 7
++
++#define BGCRR _SFR_MEM8(0x80)
++#define BGCR0 0
++#define BGCR1 1
++#define BGCR2 2
++#define BGCR3 3
++
++#define BGCCR _SFR_MEM8(0x81)
++#define BGCC0 0
++#define BGCC1 1
++#define BGCC2 2
++#define BGCC3 3
++
++#define WDTCSR _SFR_MEM8(0x82)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x83)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++#define CLKCSR _SFR_MEM8(0x84)
++#define CLKC0 0
++#define CLKC1 1
++#define CLKC2 2
++#define CLKC3 3
++#define CLKRDY 4
++#define CLKCCE 7
++
++#define CLKSELR _SFR_MEM8(0x85)
++#define CKSEL0 0
++#define CKSEL1 1
++#define CKSEL2 2
++#define CKSEL3 3
++#define CSUT0 4
++#define CSUT1 5
++#define COUT 6
++
++#define PRR _SFR_MEM8(0x86)
++#define PRADC 0
++#define PRSPI 2
++#define PRTIM1 4
++#define PRPSCR 5
++#define PRPSC2 7
++
++#define PLLCSR _SFR_MEM8(0x87)
++#define PLOCK 0
++#define PLLE 1
++#define PLLF0 2
++#define PLLF1 3
++#define PLLF2 4
++#define PLLF3 5
++
++#define OSCCAL _SFR_MEM8(0x88)
++
++#define EICRA _SFR_MEM8(0x89)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++
++#define TCCR1B _SFR_MEM8(0x8A)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++/* Reserved [0x8B] */
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x8C)
++
++#define ICR1L _SFR_MEM8(0x8C)
++#define ICR1H _SFR_MEM8(0x8D)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* PSC2 Capture Event */
++#define PSC2_CAPT_vect _VECTOR(1)
++#define PSC2_CAPT_vect_num 1
++
++/* PSC2 End Cycle */
++#define PSC2_EC_vect _VECTOR(2)
++#define PSC2_EC_vect_num 2
++
++/* PSC2 End Of Enhanced Cycle */
++#define PSC2_EEC_vect _VECTOR(3)
++#define PSC2_EEC_vect_num 3
++
++/* PSC0 Capture Event */
++#define PSC0_CAPT_vect _VECTOR(4)
++#define PSC0_CAPT_vect_num 4
++
++/* PSC0 End Cycle */
++#define PSC0_EC_vect _VECTOR(5)
++#define PSC0_EC_vect_num 5
++
++/* PSC0 End Of Enhanced Cycle */
++#define PSC0_EEC_vect _VECTOR(6)
++#define PSC0_EEC_vect_num 6
++
++/* Analog Comparator 1 */
++#define ANALOG_COMP_1_vect _VECTOR(7)
++#define ANALOG_COMP_1_vect_num 7
++
++/* Analog Comparator 2 */
++#define ANALOG_COMP_2_vect _VECTOR(8)
++#define ANALOG_COMP_2_vect_num 8
++
++/* Analog Comparator 3 */
++#define ANALOG_COMP_3_vect _VECTOR(9)
++#define ANALOG_COMP_3_vect_num 9
++
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(10)
++#define INT0_vect_num 10
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(11)
++#define TIMER1_CAPT_vect_num 11
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(12)
++#define TIMER1_OVF_vect_num 12
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(13)
++#define ADC_vect_num 13
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(14)
++#define INT1_vect_num 14
++
++/* SPI Serial Transfer Complet */
++#define SPI__STC_vect _VECTOR(15)
++#define SPI__STC_vect_num 15
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(16)
++#define INT2_vect_num 16
++
++/* Watchdog Timeout Interrupt */
++#define WDT_vect _VECTOR(17)
++#define WDT_vect_num 17
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(18)
++#define EE_READY_vect_num 18
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(19)
++#define SPM_READY_vect_num 19
++
++#define _VECTORS_SIZE 80
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 1024
++#define RAMEND 0x04FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_PSCINRB (unsigned char)~_BV(3)
++#define FUSE_PSCRV (unsigned char)~_BV(4)
++#define FUSE_PSC0RB (unsigned char)~_BV(5)
++#define FUSE_PSC2RBA (unsigned char)~_BV(6)
++#define FUSE_PSC2RB (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x8B
++
++
++#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa5272.h avr-libc-1.8.0/include/avr/ioa5272.h
+--- avr-libc-1.8.0.orig/include/avr/ioa5272.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa5272.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,736 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA5272_H_INCLUDED
++#define _AVR_ATA5272_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa5272.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++/* Reserved [0x06..0x11] */
++
++#define PORTCR _SFR_IO8(0x12)
++
++/* Reserved [0x13..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++/* Reserved [0x17..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR1 0
++#define PSR0 1
++#define TSM 7
++
++/* Reserved [0x24] */
++
++#define TCCR0A _SFR_IO8(0x25)
++#define WGM00 0
++#define WGM01 1
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x26)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define FOC0A 7
++
++#define TCNT2 _SFR_IO8(0x27)
++
++#define OCR0A _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACIRS 6
++#define ACD 7
++
++#define DWDR _SFR_IO8(0x31)
++
++/* Reserved [0x32] */
++
++#define MCUSR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++/* Reserved [0x34] */
++
++#define MCUCR _SFR_IO8(0x35)
++#define PUD 4
++#define BODS 5
++#define BODSE 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define RFLB 3
++#define CTPB 4
++#define SIGRD 5
++#define RWWSB 6
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++#define CLKCSR _SFR_MEM8(0x62)
++#define CLKC0 0
++#define CLKC1 1
++#define CLKC2 2
++#define CLKC3 3
++#define CLKRDY 4
++#define CLKCCE 7
++
++#define CLKSELR _SFR_MEM8(0x63)
++#define CSEL0 0
++#define CSEL1 1
++#define CSEL2 2
++#define CSEL3 3
++#define CSUT0 4
++#define CSUT1 5
++#define COUT 6
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSI 1
++#define PRTIM0 2
++#define PRTIM1 3
++#define PRSPI 4
++#define PRLIN 5
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6D] */
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++/* Reserved [0x70..0x76] */
++
++#define AMISCR _SFR_MEM8(0x77)
++#define XREFEN 1
++#define AREFEN 2
++#define ISRCEN 0
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define BIN 7
++#define ACIR0 4
++#define ACIR1 5
++#define ACME 6
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++#define TCCR1D _SFR_MEM8(0x83)
++#define OC1AU 0
++#define OC1AV 1
++#define OC1AW 2
++#define OC1AX 3
++#define OC1BU 4
++#define OC1BV 5
++#define OC1BW 6
++#define OC1BX 7
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR0BUB 0
++#define TCR0AUB 1
++#define OCR0AUB 3
++#define TCN0UB 4
++#define AS0 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++#define USIBR _SFR_MEM8(0xBB)
++
++#define USIPP _SFR_MEM8(0xBC)
++
++/* Reserved [0xBD..0xC7] */
++
++#define LINCR _SFR_MEM8(0xC8)
++#define LCMD0 0
++#define LCMD1 1
++#define LCMD2 2
++#define LENA 3
++#define LCONF0 4
++#define LCONF1 5
++#define LIN13 6
++#define LSWRES 7
++
++#define LINSIR _SFR_MEM8(0xC9)
++#define LRXOK 0
++#define LTXOK 1
++#define LIDOK 2
++#define LERR 3
++#define LBUSY 4
++#define LIDST0 5
++#define LIDST1 6
++#define LIDST2 7
++
++#define LINENIR _SFR_MEM8(0xCA)
++#define LENRXOK 0
++#define LENTXOK 1
++#define LENIDOK 2
++#define LENERR 3
++
++#define LINERR _SFR_MEM8(0xCB)
++#define LBERR 0
++#define LCERR 1
++#define LPERR 2
++#define LSERR 3
++#define LFERR 4
++#define LOVERR 5
++#define LTOERR 6
++#define LABORT 7
++
++#define LINBTR _SFR_MEM8(0xCC)
++#define LBT0 0
++#define LBT1 1
++#define LBT2 2
++#define LBT3 3
++#define LBT4 4
++#define LBT5 5
++#define LDISR 7
++
++#define LINBRRL _SFR_MEM8(0xCD)
++#define LDIV0 0
++#define LDIV1 1
++#define LDIV2 2
++#define LDIV3 3
++#define LDIV4 4
++#define LDIV5 5
++#define LDIV6 6
++#define LDIV7 7
++
++#define LINBRRH _SFR_MEM8(0xCE)
++#define LDIV8 0
++#define LDIV9 1
++#define LDIV10 2
++#define LDIV11 3
++
++#define LINDLR _SFR_MEM8(0xCF)
++#define LRXDL0 0
++#define LRXDL1 1
++#define LRXDL2 2
++#define LRXDL3 3
++#define LTXDL0 4
++#define LTXDL1 5
++#define LTXDL2 6
++#define LTXDL3 7
++
++#define LINIDR _SFR_MEM8(0xD0)
++#define LID0 0
++#define LID1 1
++#define LID2 2
++#define LID3 3
++#define LID4 4
++#define LID5 5
++#define LP0 6
++#define LP1 7
++
++#define LINSEL _SFR_MEM8(0xD1)
++#define LINDX0 0
++#define LINDX1 1
++#define LINDX2 2
++#define LAINC 3
++
++#define LINDAT _SFR_MEM8(0xD2)
++#define LDATA0 0
++#define LDATA1 1
++#define LDATA2 2
++#define LDATA3 3
++#define LDATA4 4
++#define LDATA5 5
++#define LDATA6 6
++#define LDATA7 7
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Watchdog Time-Out Interrupt */
++#define WDT_vect _VECTOR(5)
++#define WDT_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match 1A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter1 Compare Match 1B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match 0A */
++#define TIMER0_COMPA_vect _VECTOR(10)
++#define TIMER0_COMPA_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* LIN Transfer Complete */
++#define LIN_TC_vect _VECTOR(12)
++#define LIN_TC_vect_num 12
++
++/* LIN Error */
++#define LIN_ERR_vect _VECTOR(13)
++#define LIN_ERR_vect_num 13
++
++/* SPI Serial Transfer Complete */
++#define SPI_STC_vect _VECTOR(14)
++#define SPI_STC_vect_num 14
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(15)
++#define ADC_vect_num 15
++
++/* EEPROM Ready */
++#define EE_RDY_vect _VECTOR(16)
++#define EE_RDY_vect_num 16
++
++/* Analog Comparator */
++#define ANA_COMP_vect _VECTOR(34)
++#define ANA_COMP_vect_num 34
++
++/* USI Start */
++#define USI_START_vect _VECTOR(36)
++#define USI_START_vect_num 36
++
++/* USI Overflow */
++#define USI_OVF_vect _VECTOR(19)
++#define USI_OVF_vect_num 19
++
++#define _VECTORS_SIZE 40
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x87
++
++
++#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa5505.h avr-libc-1.8.0/include/avr/ioa5505.h
+--- avr-libc-1.8.0.orig/include/avr/ioa5505.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa5505.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,736 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA5505_H_INCLUDED
++#define _AVR_ATA5505_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa5505.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++/* Reserved [0x06..0x11] */
++
++#define PORTCR _SFR_IO8(0x12)
++
++/* Reserved [0x13..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++/* Reserved [0x17..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR1 0
++#define PSR0 1
++#define TSM 7
++
++/* Reserved [0x24] */
++
++#define TCCR0A _SFR_IO8(0x25)
++#define WGM00 0
++#define WGM01 1
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x26)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define FOC0A 7
++
++#define TCNT2 _SFR_IO8(0x27)
++
++#define OCR0A _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACIRS 6
++#define ACD 7
++
++#define DWDR _SFR_IO8(0x31)
++
++/* Reserved [0x32] */
++
++#define MCUSR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++/* Reserved [0x34] */
++
++#define MCUCR _SFR_IO8(0x35)
++#define PUD 4
++#define BODS 5
++#define BODSE 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define RFLB 3
++#define CTPB 4
++#define SIGRD 5
++#define RWWSB 6
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++#define CLKCSR _SFR_MEM8(0x62)
++#define CLKC0 0
++#define CLKC1 1
++#define CLKC2 2
++#define CLKC3 3
++#define CLKRDY 4
++#define CLKCCE 7
++
++#define CLKSELR _SFR_MEM8(0x63)
++#define CSEL0 0
++#define CSEL1 1
++#define CSEL2 2
++#define CSEL3 3
++#define CSUT0 4
++#define CSUT1 5
++#define COUT 6
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSI 1
++#define PRTIM0 2
++#define PRTIM1 3
++#define PRSPI 4
++#define PRLIN 5
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6D] */
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++/* Reserved [0x70..0x76] */
++
++#define AMISCR _SFR_MEM8(0x77)
++#define XREFEN 1
++#define AREFEN 2
++#define ISRCEN 0
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define BIN 7
++#define ACIR0 4
++#define ACIR1 5
++#define ACME 6
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++#define TCCR1D _SFR_MEM8(0x83)
++#define OC1AU 0
++#define OC1AV 1
++#define OC1AW 2
++#define OC1AX 3
++#define OC1BU 4
++#define OC1BV 5
++#define OC1BW 6
++#define OC1BX 7
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR0BUB 0
++#define TCR0AUB 1
++#define OCR0AUB 3
++#define TCN0UB 4
++#define AS0 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++#define USIBR _SFR_MEM8(0xBB)
++
++#define USIPP _SFR_MEM8(0xBC)
++
++/* Reserved [0xBD..0xC7] */
++
++#define LINCR _SFR_MEM8(0xC8)
++#define LCMD0 0
++#define LCMD1 1
++#define LCMD2 2
++#define LENA 3
++#define LCONF0 4
++#define LCONF1 5
++#define LIN13 6
++#define LSWRES 7
++
++#define LINSIR _SFR_MEM8(0xC9)
++#define LRXOK 0
++#define LTXOK 1
++#define LIDOK 2
++#define LERR 3
++#define LBUSY 4
++#define LIDST0 5
++#define LIDST1 6
++#define LIDST2 7
++
++#define LINENIR _SFR_MEM8(0xCA)
++#define LENRXOK 0
++#define LENTXOK 1
++#define LENIDOK 2
++#define LENERR 3
++
++#define LINERR _SFR_MEM8(0xCB)
++#define LBERR 0
++#define LCERR 1
++#define LPERR 2
++#define LSERR 3
++#define LFERR 4
++#define LOVERR 5
++#define LTOERR 6
++#define LABORT 7
++
++#define LINBTR _SFR_MEM8(0xCC)
++#define LBT0 0
++#define LBT1 1
++#define LBT2 2
++#define LBT3 3
++#define LBT4 4
++#define LBT5 5
++#define LDISR 7
++
++#define LINBRRL _SFR_MEM8(0xCD)
++#define LDIV0 0
++#define LDIV1 1
++#define LDIV2 2
++#define LDIV3 3
++#define LDIV4 4
++#define LDIV5 5
++#define LDIV6 6
++#define LDIV7 7
++
++#define LINBRRH _SFR_MEM8(0xCE)
++#define LDIV8 0
++#define LDIV9 1
++#define LDIV10 2
++#define LDIV11 3
++
++#define LINDLR _SFR_MEM8(0xCF)
++#define LRXDL0 0
++#define LRXDL1 1
++#define LRXDL2 2
++#define LRXDL3 3
++#define LTXDL0 4
++#define LTXDL1 5
++#define LTXDL2 6
++#define LTXDL3 7
++
++#define LINIDR _SFR_MEM8(0xD0)
++#define LID0 0
++#define LID1 1
++#define LID2 2
++#define LID3 3
++#define LID4 4
++#define LID5 5
++#define LP0 6
++#define LP1 7
++
++#define LINSEL _SFR_MEM8(0xD1)
++#define LINDX0 0
++#define LINDX1 1
++#define LINDX2 2
++#define LAINC 3
++
++#define LINDAT _SFR_MEM8(0xD2)
++#define LDATA0 0
++#define LDATA1 1
++#define LDATA2 2
++#define LDATA3 3
++#define LDATA4 4
++#define LDATA5 5
++#define LDATA6 6
++#define LDATA7 7
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Watchdog Time-Out Interrupt */
++#define WDT_vect _VECTOR(5)
++#define WDT_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match 1A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter1 Compare Match 1B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match 0A */
++#define TIMER0_COMPA_vect _VECTOR(10)
++#define TIMER0_COMPA_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* LIN Transfer Complete */
++#define LIN_TC_vect _VECTOR(12)
++#define LIN_TC_vect_num 12
++
++/* LIN Error */
++#define LIN_ERR_vect _VECTOR(13)
++#define LIN_ERR_vect_num 13
++
++/* SPI Serial Transfer Complete */
++#define SPI_STC_vect _VECTOR(14)
++#define SPI_STC_vect_num 14
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(15)
++#define ADC_vect_num 15
++
++/* EEPROM Ready */
++#define EE_RDY_vect _VECTOR(16)
++#define EE_RDY_vect_num 16
++
++/* Analog Comparator */
++#define ANA_COMP_vect _VECTOR(17)
++#define ANA_COMP_vect_num 17
++
++/* USI Start */
++#define USI_START_vect _VECTOR(18)
++#define USI_START_vect_num 18
++
++/* USI Overflow */
++#define USI_OVF_vect _VECTOR(19)
++#define USI_OVF_vect_num 19
++
++#define _VECTORS_SIZE 80
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x87
++
++
++#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa5790.h avr-libc-1.8.0/include/avr/ioa5790.h
+--- avr-libc-1.8.0.orig/include/avr/ioa5790.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa5790.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,833 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA5790_H_INCLUDED
++#define _AVR_ATA5790_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa5790.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C] */
++
++#define TPCR _SFR_IO8(0x0D)
++#define TPMA 0
++#define TPMOD 1
++#define TPMS0 2
++#define TPMS1 3
++#define TPMD0 4
++#define TPMD1 5
++#define TPPSD 6
++#define TPD 7
++
++#define TPFR _SFR_IO8(0x0E)
++#define TPF 0
++#define TPA 1
++#define TPGAP 2
++#define TPPSW 3
++
++#define CMCR _SFR_IO8(0x0F)
++#define CMM0 0
++#define CMM1 1
++#define SRCD 2
++#define CO32D 3
++#define CCS 4
++#define ECINS 5
++#define CMONEN 6
++#define CMCCE 7
++
++#define CMSR _SFR_IO8(0x10)
++#define ECF 0
++#define SXF 1
++#define RTCF 2
++
++#define T2CR _SFR_IO8(0x11)
++#define T2OTM 0
++#define T2CTM 1
++#define T2CRM 2
++#define T2GRM 3
++#define T2TOP 4
++#define T2RES 5
++#define T2TS 6
++#define T2E 7
++
++#define T3CR _SFR_IO8(0x12)
++#define T3OTM 0
++#define T3CTM 1
++#define T3CRM 2
++#define T3CPRM 3
++#define T3TOP 4
++#define T3RES 5
++#define T3CPTM 6
++#define T3E 7
++
++#define AESCR _SFR_IO8(0x13)
++#define AESWK 0
++#define AESWD 1
++#define AESIM 2
++#define AESD 3
++#define AESXOR 4
++#define AESRES 5
++#define AESE 7
++
++#define AESSR _SFR_IO8(0x14)
++#define AESRF 0
++#define AESERF 7
++
++#define TMIFR _SFR_IO8(0x15)
++#define TMRXF 0
++#define TMTXF 1
++#define TMTCF 2
++#define TMRXS 3
++#define TMTXS 4
++
++#define VMSR _SFR_IO8(0x16)
++#define VMF 0
++
++#define PCIFR _SFR_IO8(0x17)
++#define PCIF0 0
++#define PCIF1 1
++
++#define LFFR _SFR_IO8(0x18)
++#define LFID0F 0
++#define LFID1F 1
++#define LFFEF 2
++#define LFDBF 3
++#define LFRSF 4
++#define LFSDF 5
++#define LFMDF 6
++#define LFCAF 7
++
++#define T0IFR _SFR_IO8(0x19)
++#define T0F 0
++
++#define T1IFR _SFR_IO8(0x1A)
++#define T1F 0
++
++#define T2IFR _SFR_IO8(0x1B)
++#define T2OFF 0
++#define T2COF 1
++
++#define T3IFR _SFR_IO8(0x1C)
++#define T3OFF 0
++#define T3COF 1
++#define T3ICF 2
++
++#define EIFR _SFR_IO8(0x1D)
++#define INTF0 0
++
++#define GPIOR _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++#define EELP 6
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define EEPR _SFR_IO8(0x23)
++#define EEAP0 0
++#define EEAP1 1
++#define EEAP2 2
++#define EEAP3 3
++
++#define EECCR _SFR_IO8(0x24)
++#define EEL0 0
++#define EEL1 1
++#define EEL2 2
++#define EEL3 3
++
++/* Reserved [0x25] */
++
++#define PCICR _SFR_IO8(0x26)
++#define PCIE0 0
++#define PCIE1 1
++
++#define EIMSK _SFR_IO8(0x27)
++#define INT0 0
++
++#define TMDR _SFR_IO8(0x28)
++
++#define AESDR _SFR_IO8(0x29)
++
++#define AESKR _SFR_IO8(0x2A)
++#define AESKR0 0
++#define AESKR1 1
++#define AESKR2 2
++#define AESKR3 3
++#define AESKR4 4
++#define AESKR5 5
++#define AESKR6 6
++#define AESKR7 7
++
++#define VMCR _SFR_IO8(0x2B)
++#define VMLS0 0
++#define VMLS1 1
++#define VMLS2 2
++#define VMLS3 3
++#define VMIM 4
++#define VMPS 5
++#define BODPD 6
++#define BODLS 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++#define LFCR0 _SFR_IO8(0x2F)
++#define LFCE1 0
++#define LFCE2 1
++#define LFCE3 2
++#define LFBRS 3
++#define LFRBS 4
++#define LFMG 5
++#define LFVC0 6
++#define LFVC1 7
++
++#define LFCR1 _SFR_IO8(0x30)
++#define LFM0 0
++#define LFM1 1
++#define LFFM0 2
++#define LFFM1 3
++#define LFRMS 4
++#define LFRMSA 5
++#define LFQCE 6
++#define LFRE 7
++
++/* Reserved [0x31] */
++
++#define LFRDB _SFR_IO8(0x32)
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define TPRF 5
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++#define LFSR _SFR_IO8(0x36)
++#define LFES 0
++#define LFSD 1
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++#define T1CR _SFR_IO8(0x38)
++#define T1PS0 0
++#define T1PS1 1
++#define T1IE 2
++#define T1CS0 3
++#define T1CS1 4
++#define T1E 7
++
++#define T0CR _SFR_IO8(0x39)
++#define T0PS0 0
++#define T0PS1 1
++#define T0PS2 2
++#define T0IE 3
++#define T0PR 4
++
++/* Reserved [0x3A] */
++
++#define CMIMR _SFR_IO8(0x3B)
++#define ECIE 0
++#define SXIE 1
++#define RTCIE 2
++
++#define CLKPR _SFR_IO8(0x3C)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLTPS0 3
++#define CLTPS1 4
++#define CLTPS2 5
++#define CLKPCE 7
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDPS0 0
++#define WDPS1 1
++#define WDPS2 2
++#define WDE 3
++#define WDCE 4
++
++/* Reserved [0x61..0x62] */
++
++#define PRR0 _SFR_MEM8(0x63)
++#define PRLFR 0
++#define PRT1 1
++#define PRT2 2
++#define PRT3 3
++#define PRTM 4
++#define PRCU 5
++#define PRDS 6
++#define PRVM 7
++
++#define PRR1 _SFR_MEM8(0x64)
++#define PRCI 0
++#define PRSPI 1
++
++#define SRCCAL _SFR_MEM8(0x65)
++
++#define FRCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++#define PCMSK0 _SFR_MEM8(0x6A)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6B)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6C] */
++
++#define LDCR _SFR_MEM8(0x6D)
++#define LDE 0
++#define LDCS0 1
++#define LDCS1 2
++
++/* Reserved [0x6E..0x6F] */
++
++#define T2CNT _SFR_MEM8(0x70)
++
++#define T2COR _SFR_MEM8(0x71)
++
++/* Reserved [0x72] */
++
++#define T2MR _SFR_MEM8(0x73)
++#define T2CS0 0
++#define T2CS1 1
++#define T2CS2 2
++#define T2PS0 3
++#define T2PS1 4
++#define T2PS2 5
++#define T2D0 6
++#define T2D1 7
++
++#define T2IMR _SFR_MEM8(0x74)
++#define T2OIM 0
++#define T2CIM 1
++
++/* Reserved [0x75] */
++
++#define T3CNT _SFR_MEM8(0x76)
++
++#define T3COR _SFR_MEM8(0x77)
++
++#define T3ICR _SFR_MEM8(0x78)
++
++#define T3MRA _SFR_MEM8(0x79)
++#define T3CS0 0
++#define T3CS1 1
++#define T3SCE 2
++#define T3CE0 3
++#define T3CE1 4
++#define T3CNC 5
++#define T3ICS0 6
++#define T3ICS1 7
++
++#define T3MRB _SFR_MEM8(0x7A)
++#define T3PS0 0
++#define T3PS1 1
++#define T3PS2 2
++
++#define T3IMR _SFR_MEM8(0x7B)
++#define T3OIM 0
++#define T3CIM 1
++#define T3CPIM 2
++
++/* Reserved [0x7C] */
++
++#define TMCR _SFR_MEM8(0x7D)
++#define MI1S0 0
++#define MI1S1 1
++#define MI2S0 2
++#define MI2S1 3
++#define MI4S0 4
++#define MI4S1 5
++#define TMCPOL 6
++#define TMSSIE 7
++
++#define TMMR _SFR_MEM8(0x7E)
++#define MOS0 0
++#define MOS1 1
++#define MSCS0 2
++#define MSCS1 3
++#define MOUTC 4
++#define TMMS0 5
++#define TMMS1 6
++#define TM12S 7
++
++#define TMIMR _SFR_MEM8(0x7F)
++#define TMRXIM 0
++#define TMTXIM 1
++#define TMTCIM 2
++
++/* Reserved [0x80..0x81] */
++
++#define LFIMR _SFR_MEM8(0x82)
++#define LFID0IM 0
++#define LFID1IM 1
++#define LFFEIM 2
++#define LFDBIM 3
++#define LFRSIM 4
++#define LFSDIM 5
++#define LFMDIM 6
++
++#define LFCAD _SFR_MEM8(0x83)
++
++#define LFID00 _SFR_MEM8(0x84)
++
++#define LFID01 _SFR_MEM8(0x85)
++
++#define LFID02 _SFR_MEM8(0x86)
++
++#define LFID03 _SFR_MEM8(0x87)
++
++#define LFID10 _SFR_MEM8(0x88)
++
++#define LFID11 _SFR_MEM8(0x89)
++
++#define LFID12 _SFR_MEM8(0x8A)
++
++#define LFID13 _SFR_MEM8(0x8B)
++
++#define LFRD0 _SFR_MEM8(0x8C)
++
++#define LFRD1 _SFR_MEM8(0x8D)
++
++#define LFRD2 _SFR_MEM8(0x8E)
++
++#define LFRD3 _SFR_MEM8(0x8F)
++
++#define LFID0M _SFR_MEM8(0x90)
++#define ID0FS0 0
++#define ID0FS1 1
++#define ID0FS2 2
++#define ID0FS3 3
++#define ID0FS4 4
++#define ID0E 7
++
++#define LFID1M _SFR_MEM8(0x91)
++#define ID1FS0 0
++#define ID1FS1 1
++#define ID1FS2 2
++#define ID1FS3 3
++#define ID1FS4 4
++#define ID1E 7
++
++#define LFRDF _SFR_MEM8(0x92)
++#define RDFS0 0
++#define RDFS1 1
++#define RDFS2 2
++#define RDFS3 3
++#define RDFS4 4
++#define RDFE 7
++
++#define LFRSD1 _SFR_MEM8(0x93)
++
++#define LFRSD2 _SFR_MEM8(0x94)
++
++#define LFRSD3 _SFR_MEM8(0x95)
++
++#define LFCC1 _SFR_MEM8(0x96)
++
++#define LFCC2 _SFR_MEM8(0x97)
++
++#define LFCC3 _SFR_MEM8(0x98)
++
++/* Reserved [0x99..0x9B] */
++
++#define TPIMR _SFR_MEM8(0x9C)
++#define TPIM 0
++
++/* Reserved [0x9D] */
++
++#define RTCCR _SFR_MEM8(0x9E)
++#define RTCR 0
++
++#define RTCDR _SFR_MEM8(0x9F)
++
++/* Reserved [0xA0..0xA7] */
++
++#define TMMDR _SFR_MEM8(0xA8)
++
++#define TMBDR _SFR_MEM8(0xA9)
++
++#define TMTDR _SFR_MEM8(0xAA)
++
++#define TMSR _SFR_MEM8(0xAB)
++
++/* Reserved [0xAC] */
++
++#define CRCDR _SFR_MEM8(0xAD)
++
++#define CRCCR _SFR_MEM8(0xAE)
++#define CRCN0 0
++#define CRCN1 1
++#define CRCN2 2
++#define CRCSEL 3
++#define REFLI 4
++#define REFLO 5
++#define CRCRS 7
++
++#define CRCSR _SFR_MEM8(0xAF)
++#define CRCBF 0
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* Transponder Mode Interrupt */
++#define TPINT_vect _VECTOR(1)
++#define TPINT_vect_num 1
++
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(2)
++#define INT0_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Voltage Monitoring Interrupt */
++#define VMINT_vect _VECTOR(5)
++#define VMINT_vect_num 5
++
++/* Timer0 Interval Interrupt */
++#define T0INT_vect _VECTOR(6)
++#define T0INT_vect_num 6
++
++/* LF-Receiver Identifier 0 Interrupt */
++#define LFID0INT_vect _VECTOR(7)
++#define LFID0INT_vect_num 7
++
++/* LF-Receiver Identifier 1 Interrupt */
++#define LFID1INT_vect _VECTOR(8)
++#define LFID1INT_vect_num 8
++
++/* LF-Receiver Frame End Interrupt */
++#define LFFEINT_vect _VECTOR(9)
++#define LFFEINT_vect_num 9
++
++/* LF-Receiver Data Buffer full Interrupt */
++#define LFDBINT_vect _VECTOR(10)
++#define LFDBINT_vect_num 10
++
++/* Timer/Counter3 Capture Event Interrupt */
++#define T3CAPINT_vect _VECTOR(11)
++#define T3CAPINT_vect_num 11
++
++/* Timer/Counter3 Compare Match Interrupt */
++#define T3COMINT_vect _VECTOR(12)
++#define T3COMINT_vect_num 12
++
++/* Timer/Counter3 Overflow Interrupt */
++#define T3OVFINT_vect _VECTOR(13)
++#define T3OVFINT_vect_num 13
++
++/* Timer/Counter2 Compare Match Interrupt */
++#define T2COMINT_vect _VECTOR(14)
++#define T2COMINT_vect_num 14
++
++/* Timer/Counter2 Overflow Interrupt */
++#define T2OVFINT_vect _VECTOR(15)
++#define T2OVFINT_vect_num 15
++
++/* Timer 1 Interval Interrupt */
++#define T1INT_vect _VECTOR(16)
++#define T1INT_vect_num 16
++
++/* SPI Serial Transfer Complete Interrupt */
++#define SPISTC_vect _VECTOR(17)
++#define SPISTC_vect_num 17
++
++/* Timer Modulator SSI Receive Buffer Interrupt */
++#define TMRXBINT_vect _VECTOR(18)
++#define TMRXBINT_vect_num 18
++
++/* Timer Modulator SSI Transmit Buffer Interrupt */
++#define TMTXBINT_vect _VECTOR(19)
++#define TMTXBINT_vect_num 19
++
++/* Timer Modulator Transmit Complete Interrupt */
++#define TMTXCINT_vect _VECTOR(20)
++#define TMTXCINT_vect_num 20
++
++/* AES Interrupt */
++#define AESINT_vect _VECTOR(21)
++#define AESINT_vect_num 21
++
++/* LF-Receiver RSSi measurement Interrupt */
++#define LFRSSINT_vect _VECTOR(22)
++#define LFRSSINT_vect_num 22
++
++/* LF-Receiver Signal Detect Interrupt */
++#define LFSDINT_vect _VECTOR(23)
++#define LFSDINT_vect_num 23
++
++/* LF-Receiver Manchester Decoder error Interrupt */
++#define LFMDINT_vect _VECTOR(24)
++#define LFMDINT_vect_num 24
++
++/* External Input Clock Monitoring Interrupt */
++#define EXCMINT_vect _VECTOR(25)
++#define EXCMINT_vect_num 25
++
++/* External XTAL Oscillator Break Down Interrupt */
++#define EXXMINT_vect _VECTOR(26)
++#define EXXMINT_vect_num 26
++
++/* Real Time Clock Interrupt */
++#define RTCINT_vect _VECTOR(27)
++#define RTCINT_vect_num 27
++
++/* EEPROM Ready Interrupt */
++#define EEREADY_vect _VECTOR(28)
++#define EEREADY_vect_num 28
++
++/* Store Program Memory Ready */
++#define SPMREADY_vect _VECTOR(29)
++#define SPMREADY_vect_num 29
++
++#define _VECTORS_SIZE 120
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 2048
++#define E2PAGESIZE 16
++#define E2END 0x07FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 1
++
++/* Fuse Byte */
++#define FUSE_CKDIV8 (unsigned char)~_BV(128)
++#define FUSE_DWEN (unsigned char)~_BV(64)
++#define FUSE_SPIEN (unsigned char)~_BV(32)
++#define FUSE_WDTON (unsigned char)~_BV(16)
++#define FUSE_EESAVE (unsigned char)~_BV(8)
++#define FUSE_Reserved (unsigned char)~_BV(4)
++#define FUSE__32OEN (unsigned char)~_BV(2)
++#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x61
++
++
++#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa5795.h avr-libc-1.8.0/include/avr/ioa5795.h
+--- avr-libc-1.8.0.orig/include/avr/ioa5795.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa5795.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,699 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA5795_H_INCLUDED
++#define _AVR_ATA5795_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa5795.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C] */
++
++#define TPCR _SFR_IO8(0x0D)
++#define TPMA 0
++#define TPMOD 1
++#define TPMS0 2
++#define TPMS1 3
++#define TPMD0 4
++#define TPMD1 5
++#define TPPSD 6
++#define TPD 7
++
++#define TPFR _SFR_IO8(0x0E)
++#define TPF 0
++#define TPA 1
++#define TPGAP 2
++#define TPPSW 3
++
++#define CMCR _SFR_IO8(0x0F)
++#define CMM0 0
++#define CMM1 1
++#define SRCD 2
++#define CO32D 3
++#define CCS 4
++#define ECINS 5
++#define CMONEN 6
++#define CMCCE 7
++
++#define CMSR _SFR_IO8(0x10)
++#define ECF 0
++#define SXF 1
++#define RTCF 2
++
++#define T2CR _SFR_IO8(0x11)
++#define T2OTM 0
++#define T2CTM 1
++#define T2CRM 2
++#define T2GRM 3
++#define T2TOP 4
++#define T2RES 5
++#define T2TS 6
++#define T2E 7
++
++#define T3CR _SFR_IO8(0x12)
++#define T3OTM 0
++#define T3CTM 1
++#define T3CRM 2
++#define T3CPRM 3
++#define T3TOP 4
++#define T3RES 5
++#define T3CPTM 6
++#define T3E 7
++
++#define AESCR _SFR_IO8(0x13)
++#define AESWK 0
++#define AESWD 1
++#define AESIM 2
++#define AESD 3
++#define AESXOR 4
++#define AESRES 5
++#define AESE 7
++
++#define AESSR _SFR_IO8(0x14)
++#define AESRF 0
++#define AESERF 7
++
++#define TMIFR _SFR_IO8(0x15)
++#define TMRXF 0
++#define TMTXF 1
++#define TMTCF 2
++#define TMRXS 3
++#define TMTXS 4
++
++#define VMSR _SFR_IO8(0x16)
++#define VMF 0
++
++#define PCIFR _SFR_IO8(0x17)
++#define PCIF0 0
++#define PCIF1 1
++
++/* Reserved [0x18] */
++
++#define T0IFR _SFR_IO8(0x19)
++#define T0F 0
++
++#define T1IFR _SFR_IO8(0x1A)
++#define T1F 0
++
++#define T2IFR _SFR_IO8(0x1B)
++#define T2OFF 0
++#define T2COF 1
++
++#define T3IFR _SFR_IO8(0x1C)
++#define T3OFF 0
++#define T3COF 1
++#define T3ICF 2
++
++#define EIFR _SFR_IO8(0x1D)
++#define INTF0 0
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++#define EELP 6
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define EEPR _SFR_IO8(0x23)
++#define EEAP0 0
++#define EEAP1 1
++#define EEAP2 2
++#define EEAP3 3
++
++#define EECCR _SFR_IO8(0x24)
++#define EEL0 0
++#define EEL1 1
++#define EEL2 2
++#define EEL3 3
++
++/* Reserved [0x25] */
++
++#define PCICR _SFR_IO8(0x26)
++#define PCIE0 0
++#define PCIE1 1
++
++#define EIMSK _SFR_IO8(0x27)
++#define INT0 0
++
++#define TMDR _SFR_IO8(0x28)
++
++#define AESDR _SFR_IO8(0x29)
++
++#define AESKR _SFR_IO8(0x2A)
++#define AESKR0 0
++#define AESKR1 1
++#define AESKR2 2
++#define AESKR3 3
++#define AESKR4 4
++#define AESKR5 5
++#define AESKR6 6
++#define AESKR7 7
++
++#define VMCR _SFR_IO8(0x2B)
++#define VMLS0 0
++#define VMLS1 1
++#define VMLS2 2
++#define VMLS3 3
++#define VMIM 4
++#define VMPS 5
++#define BODPD 6
++#define BODLS 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F..0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define TPRF 5
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++#define T1CR _SFR_IO8(0x38)
++#define T1PS0 0
++#define T1PS1 1
++#define T1IE 2
++#define T1CS0 3
++#define T1CS1 4
++#define T1E 7
++
++#define T0CR _SFR_IO8(0x39)
++#define T0PS0 0
++#define T0PS1 1
++#define T0PS2 2
++#define T0IE 3
++#define T0PR 4
++
++/* Reserved [0x3A] */
++
++#define CMIMR _SFR_IO8(0x3B)
++#define ECIE 0
++#define SXIE 1
++#define RTCIE 2
++
++#define CLKPR _SFR_IO8(0x3C)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLTPS0 3
++#define CLTPS1 4
++#define CLTPS2 5
++#define CLKPCE 7
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDPS0 0
++#define WDPS1 1
++#define WDPS2 2
++#define WDE 3
++#define WDCE 4
++
++/* Reserved [0x61..0x62] */
++
++#define PRR0 _SFR_MEM8(0x63)
++#define PRT1 1
++#define PRT2 2
++#define PRT3 3
++#define PRTM 4
++#define PRCU 5
++#define PRDS 6
++#define PRVM 7
++
++#define PRR1 _SFR_MEM8(0x64)
++#define PRCI 0
++#define PRSPI 1
++
++#define SRCCAL _SFR_MEM8(0x65)
++
++#define FRCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++#define PCMSK0 _SFR_MEM8(0x6A)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6B)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6C] */
++
++#define LDCR _SFR_MEM8(0x6D)
++#define LDE 0
++#define LDCS0 1
++#define LDCS1 2
++
++/* Reserved [0x6E..0x6F] */
++
++#define T2CNT _SFR_MEM8(0x70)
++
++#define T2COR _SFR_MEM8(0x71)
++
++/* Reserved [0x72] */
++
++#define T2MR _SFR_MEM8(0x73)
++#define T2CS0 0
++#define T2CS1 1
++#define T2CS2 2
++#define T2PS0 3
++#define T2PS1 4
++#define T2PS2 5
++#define T2D0 6
++#define T2D1 7
++
++#define T2IMR _SFR_MEM8(0x74)
++#define T2OIM 0
++#define T2CIM 1
++
++/* Reserved [0x75] */
++
++#define T3CNT _SFR_MEM8(0x76)
++
++#define T3COR _SFR_MEM8(0x77)
++
++#define T3ICR _SFR_MEM8(0x78)
++
++#define T3MRA _SFR_MEM8(0x79)
++#define T3CS0 0
++#define T3CS1 1
++#define T3SCE 2
++#define T3CE0 3
++#define T3CE1 4
++#define T3CNC 5
++#define T3ICS0 6
++#define T3ICS1 7
++
++#define T3MRB _SFR_MEM8(0x7A)
++#define T3PS0 0
++#define T3PS1 1
++#define T3PS2 2
++
++#define T3IMR _SFR_MEM8(0x7B)
++#define T3OIM 0
++#define T3CIM 1
++#define T3CPIM 2
++
++/* Reserved [0x7C] */
++
++#define TMCR _SFR_MEM8(0x7D)
++#define MI1S0 0
++#define MI1S1 1
++#define MI2S0 2
++#define MI2S1 3
++#define MI4S0 4
++#define MI4S1 5
++#define TMCPOL 6
++#define TMSSIE 7
++
++#define TMMR _SFR_MEM8(0x7E)
++#define MOS0 0
++#define MOS1 1
++#define MSCS0 2
++#define MSCS1 3
++#define MOUTC 4
++#define TMMS0 5
++#define TMMS1 6
++#define TM12S 7
++
++#define TMIMR _SFR_MEM8(0x7F)
++#define TMRXIM 0
++#define TMTXIM 1
++#define TMTCIM 2
++
++/* Reserved [0x80..0x9B] */
++
++#define TPIMR _SFR_MEM8(0x9C)
++#define TPIM 0
++
++/* Reserved [0x9D] */
++
++#define RTCCR _SFR_MEM8(0x9E)
++#define RTCR 0
++
++#define RTCDR _SFR_MEM8(0x9F)
++
++/* Reserved [0xA0..0xA7] */
++
++#define TMMDR _SFR_MEM8(0xA8)
++
++#define TMBDR _SFR_MEM8(0xA9)
++
++#define TMTDR _SFR_MEM8(0xAA)
++
++#define TMSR _SFR_MEM8(0xAB)
++
++/* Reserved [0xAC] */
++
++#define CRCDR _SFR_MEM8(0xAD)
++
++#define CRCCR _SFR_MEM8(0xAE)
++#define CRCN0 0
++#define CRCN1 1
++#define CRCN2 2
++#define CRCSEL 3
++#define REFLI 4
++#define REFLO 5
++#define CRCRS 7
++
++#define CRCSR _SFR_MEM8(0xAF)
++#define CRCBF 0
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* Transponder Mode Interrupt */
++#define TPINT_vect _VECTOR(2)
++#define TPINT_vect_num 2
++
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(4)
++#define INT0_vect_num 4
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(6)
++#define PCINT0_vect_num 6
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(8)
++#define PCINT1_vect_num 8
++
++/* Voltage Monitor Interrupt */
++#define VMINT_vect _VECTOR(10)
++#define VMINT_vect_num 10
++
++/* Timer0 Interval Interrupt */
++#define T0INT_vect _VECTOR(12)
++#define T0INT_vect_num 12
++
++/* Timer3 Capture Interrupt */
++#define T3CAPINT_vect _VECTOR(14)
++#define T3CAPINT_vect_num 14
++
++/* Timer3 Compare Match Interrupt */
++#define T3COMINT_vect _VECTOR(16)
++#define T3COMINT_vect_num 16
++
++/* Timer3 Overflow Interrupt */
++#define T3OVFINT_vect _VECTOR(18)
++#define T3OVFINT_vect_num 18
++
++/* Timer2 Compare Match Interrupt */
++#define T2COMINT_vect _VECTOR(20)
++#define T2COMINT_vect_num 20
++
++/* Timer2 Overflow Interrupt */
++#define T2OVFINT_vect _VECTOR(22)
++#define T2OVFINT_vect_num 22
++
++/* Timer1 Interval Interrupt */
++#define T1INT_vect _VECTOR(24)
++#define T1INT_vect_num 24
++
++/* SPI Serial Transfer Complete */
++#define SPISTC_vect _VECTOR(26)
++#define SPISTC_vect_num 26
++
++/* Timer Modulator SSI Receive Buffer Interrupt */
++#define TMRXBINT_vect _VECTOR(28)
++#define TMRXBINT_vect_num 28
++
++/* Timer Modulator SSI Transmit Buffer Interrupt */
++#define TMTXBINT_vect _VECTOR(30)
++#define TMTXBINT_vect_num 30
++
++/* Timer Modulator Transmit Complete Interrupt */
++#define TMTXCINT_vect _VECTOR(32)
++#define TMTXCINT_vect_num 32
++
++/* AES Interrupt */
++#define AESINT_vect _VECTOR(34)
++#define AESINT_vect_num 34
++
++/* External Input Clock Monitoring Interrupt */
++#define EXCMINT_vect _VECTOR(36)
++#define EXCMINT_vect_num 36
++
++/* External XTAL Oscillator Break Down Interrupt */
++#define EXXMINT_vect _VECTOR(38)
++#define EXXMINT_vect_num 38
++
++/* Real Time Clock Interrupt */
++#define RTCINT_vect _VECTOR(40)
++#define RTCINT_vect_num 40
++
++/* EEPROM Ready Interrupt */
++#define EEREADY_vect _VECTOR(42)
++#define EEREADY_vect_num 42
++
++/* Store Program Memory Ready */
++#define SPMREADY_vect _VECTOR(44)
++#define SPMREADY_vect_num 44
++
++#define _VECTORS_SIZE 46
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 2048
++#define E2PAGESIZE 16
++#define E2END 0x07FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 1
++
++/* Fuse Byte */
++#define FUSE_CKDIV8 (unsigned char)~_BV(128)
++#define FUSE_DWEN (unsigned char)~_BV(64)
++#define FUSE_SPIEN (unsigned char)~_BV(32)
++#define FUSE_WDTON (unsigned char)~_BV(16)
++#define FUSE_EESAVE (unsigned char)~_BV(8)
++#define FUSE_Reserved (unsigned char)~_BV(4)
++#define FUSE__32OEN (unsigned char)~_BV(2)
++#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x61
++
++
++#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa6285.h avr-libc-1.8.0/include/avr/ioa6285.h
+--- avr-libc-1.8.0.orig/include/avr/ioa6285.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa6285.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,705 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA6285_H_INCLUDED
++#define _AVR_ATA6285_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa6285.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x0E] */
++
++#define CMCR _SFR_IO8(0x0F)
++#define CMM0 0
++#define CMM1 1
++#define SRCD 2
++#define CMONEN 3
++#define CCS 4
++#define ECINS 5
++#define CMCCE 7
++
++#define CMSR _SFR_IO8(0x10)
++#define ECF 0
++
++#define T2CRA _SFR_IO8(0x11)
++#define T2OTM 0
++#define T2CTM 1
++#define T2CR 2
++#define T2CRM 3
++#define T2ICS 5
++#define T2TS 6
++#define T2E 7
++
++#define T2CRB _SFR_IO8(0x12)
++#define T2SCE 0
++
++/* Reserved [0x13] */
++
++#define T3CRA _SFR_IO8(0x14)
++#define T3AC 0
++#define T3SCE 1
++#define T3CR 2
++#define T3TS 6
++#define T3E 7
++
++/* Reserved [0x15] */
++
++#define VMCSR _SFR_IO8(0x16)
++#define VMEN 0
++#define VMLS0 1
++#define VMLS1 2
++#define VMLS2 3
++#define VMIM 4
++#define VMF 5
++#define BODPD 6
++#define BODLS 7
++
++#define PCIFR _SFR_IO8(0x17)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define LFFR _SFR_IO8(0x18)
++#define LFWPF 0
++#define LFBF 1
++#define LFEDF 2
++#define LFRF 3
++
++#define SSFR _SFR_IO8(0x19)
++#define MSENF 0
++#define MSENO 1
++
++#define T10IFR _SFR_IO8(0x1A)
++#define T0F 0
++#define T1F 1
++
++#define T2IFR _SFR_IO8(0x1B)
++#define T2OFF 0
++#define T2COF 1
++#define T2ICF 2
++#define T2RXF 3
++#define T2TXF 4
++#define T2TCF 5
++
++#define T3IFR _SFR_IO8(0x1C)
++#define T3OFF 0
++#define T3COAF 1
++#define T3COBF 2
++#define T3ICF 3
++
++#define EIFR _SFR_IO8(0x1D)
++#define INTF0 0
++#define INTF1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define PCICR _SFR_IO8(0x23)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EIMSK _SFR_IO8(0x24)
++#define INT0 0
++#define INT1 1
++
++/* Reserved [0x25..0x26] */
++
++#define SVCR _SFR_IO8(0x27)
++
++#define SCR _SFR_IO8(0x28)
++#define SMS 0
++#define SEN0 1
++#define SEN1 2
++#define SMEN 3
++
++#define SCCR _SFR_IO8(0x29)
++#define SRCC0 0
++#define SRCC1 1
++#define SCCS0 2
++#define SCCS1 3
++#define SCCS2 4
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++#define T2MDR _SFR_IO8(0x2F)
++
++#define LFRR _SFR_IO8(0x30)
++
++/* Reserved [0x31] */
++
++#define LFCDR _SFR_IO8(0x32)
++#define LFDO 0
++#define LFRST 6
++#define LFSCE 7
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define TSRF 5
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++#define LFRB _SFR_IO8(0x36)
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SELFPRGEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++#define T1CR _SFR_IO8(0x38)
++#define T1PS0 0
++#define T1PS1 1
++#define T1PS2 2
++#define T1CS0 3
++#define T1CS1 4
++#define T1CS2 5
++#define T1IE 7
++
++#define T0CR _SFR_IO8(0x39)
++#define T0PAS0 0
++#define T0PAS1 1
++#define T0PAS2 2
++#define T0IE 3
++#define T0PR 4
++#define T0PBS0 5
++#define T0PBS1 6
++#define T0PBS2 7
++
++/* Reserved [0x3A] */
++
++#define CMIMR _SFR_IO8(0x3B)
++#define ECIE 0
++
++#define CLKPR _SFR_IO8(0x3C)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLTPS0 3
++#define CLTPS1 4
++#define CLTPS2 5
++#define CLPCE 7
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDPS0 0
++#define WDPS1 1
++#define WDPS2 2
++#define WDE 3
++#define WDCE 4
++
++#define SIMSK _SFR_MEM8(0x61)
++#define MSIE 0
++
++/* Reserved [0x62..0x63] */
++
++#define TSCR _SFR_MEM8(0x64)
++#define TSSD 0
++
++#define SRCCAL _SFR_MEM8(0x65)
++
++#define FRCCAL _SFR_MEM8(0x66)
++
++#define MSVCAL _SFR_MEM8(0x67)
++
++/* Reserved [0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++#define PCMSK0 _SFR_MEM8(0x6A)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6B)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++
++#define PCMSK2 _SFR_MEM8(0x6C)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++/* Reserved [0x6D] */
++
++#define T2ICRL _SFR_MEM8(0x6E)
++
++#define T2ICR _SFR_MEM8(0x6F)
++
++/* Combine T2CORL and T2CORH */
++#define T2COR _SFR_MEM16(0x70)
++
++#define T2CORL _SFR_MEM8(0x70)
++#define T2CORH _SFR_MEM8(0x71)
++
++#define T2MRA _SFR_MEM8(0x72)
++#define T2CS0 0
++#define T2CS1 1
++#define T2CS2 2
++#define T2CE0 3
++#define T2CE1 4
++#define T2CNC 5
++#define T2TP0 6
++#define T2TP1 7
++
++#define T2MRB _SFR_MEM8(0x73)
++#define T2M0 0
++#define T2M1 1
++#define T2M2 2
++#define T2M3 3
++#define T2TOP 4
++#define T2CPOL 6
++#define T2SSIE 7
++
++#define T2IMR _SFR_MEM8(0x74)
++#define T2OIM 0
++#define T2CIM 1
++#define T2CPIM 2
++#define T2RXIM 3
++#define T2TXIM 4
++#define T2TCIM 5
++
++/* Reserved [0x75] */
++
++/* Combine T3ICRL and T3ICRH */
++#define T3ICR _SFR_MEM16(0x76)
++
++#define T3ICRL _SFR_MEM8(0x76)
++#define T3ICRH _SFR_MEM8(0x77)
++
++/* Combine T3CORAL and T3CORAH */
++#define T3CORA _SFR_MEM16(0x78)
++
++#define T3CORAL _SFR_MEM8(0x78)
++#define T3CORAH _SFR_MEM8(0x79)
++
++/* Combine T3CORBL and T3CORBH */
++#define T3CORB _SFR_MEM16(0x7A)
++
++#define T3CORBL _SFR_MEM8(0x7A)
++#define T3CORBH _SFR_MEM8(0x7B)
++
++#define T3MRA _SFR_MEM8(0x7C)
++#define T3CS0 0
++#define T3CS1 1
++#define T3CS2 2
++#define T3CE0 3
++#define T3CE1 4
++#define T3CNC 5
++#define T3ICS0 6
++#define T3ICS1 7
++
++#define T3MRB _SFR_MEM8(0x7D)
++#define T3M0 0
++#define T3M1 1
++#define T3M2 2
++#define T3TOP 4
++
++#define T3CRB _SFR_MEM8(0x7E)
++#define T3CTMA 0
++#define T3SAMA 1
++#define T3CRMA 2
++#define T3CTMB 3
++#define T3SAMB 4
++#define T3CRMB 5
++#define T3CPRM 6
++
++#define T3IMR _SFR_MEM8(0x7F)
++#define T3OIM 0
++#define T3CAIM 1
++#define T3CBIM 2
++#define T3CPIM 3
++
++/* Reserved [0x80] */
++
++#define LFIMR _SFR_MEM8(0x81)
++#define LFWIM 0
++#define LFBIM 1
++#define LFEIM 2
++
++#define LFRCR _SFR_MEM8(0x82)
++#define LFEN 0
++#define LFBM 1
++#define LFWM0 2
++#define LFWM1 3
++#define LFRSS 4
++#define LFCS0 5
++#define LFCS1 6
++#define LFCS2 7
++
++#define LFHCR _SFR_MEM8(0x83)
++
++/* Combine LFIDCL and LFIDCH */
++#define LFIDC _SFR_MEM16(0x84)
++
++#define LFIDCL _SFR_MEM8(0x84)
++#define LFIDCH _SFR_MEM8(0x85)
++
++/* Combine LFCALL and LFCALH */
++#define LFCAL _SFR_MEM16(0x86)
++
++#define LFCALL _SFR_MEM8(0x86)
++#define LFCALH _SFR_MEM8(0x87)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(5)
++#define PCINT2_vect_num 5
++
++/* Voltage Monitor Interrupt */
++#define INTVM_vect _VECTOR(6)
++#define INTVM_vect_num 6
++
++/* Sensor Interface Interrupt */
++#define SENINT_vect _VECTOR(7)
++#define SENINT_vect_num 7
++
++/* Timer0 Interval Interrupt */
++#define INTT0_vect _VECTOR(8)
++#define INTT0_vect_num 8
++
++/* LF-Receiver Wake-up Interrupt */
++#define LFWP_vect _VECTOR(9)
++#define LFWP_vect_num 9
++
++/* Timer/Counter3 Capture Event */
++#define T3CAP_vect _VECTOR(10)
++#define T3CAP_vect_num 10
++
++/* Timer/Counter3 Compare Match A */
++#define T3COMA_vect _VECTOR(11)
++#define T3COMA_vect_num 11
++
++/* Timer/Counter3 Compare Match B */
++#define T3COMB_vect _VECTOR(12)
++#define T3COMB_vect_num 12
++
++/* Timer/Counter3 Overflow */
++#define T3OVF_vect _VECTOR(13)
++#define T3OVF_vect_num 13
++
++/* Timer/Counter2 Capture Event */
++#define T2CAP_vect _VECTOR(14)
++#define T2CAP_vect_num 14
++
++/* Timer/Counter2 Compare Match */
++#define T2COM_vect _VECTOR(15)
++#define T2COM_vect_num 15
++
++/* Timer/Counter2 Overflow */
++#define T2OVF_vect _VECTOR(16)
++#define T2OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPISTC_vect _VECTOR(17)
++#define SPISTC_vect_num 17
++
++/* LF Receive Buffer Interrupt */
++#define LFRXB_vect _VECTOR(18)
++#define LFRXB_vect_num 18
++
++/* Timer1 Interval Interrupt */
++#define INTT1_vect _VECTOR(19)
++#define INTT1_vect_num 19
++
++/* Timer2 SSI Receive Buffer Interrupt */
++#define T2RXB_vect _VECTOR(20)
++#define T2RXB_vect_num 20
++
++/* Timer2 SSI Transmit Buffer Interrupt */
++#define T2TXB_vect _VECTOR(21)
++#define T2TXB_vect_num 21
++
++/* Timer2 SSI Transmit Complete Interrupt */
++#define T2TXC_vect _VECTOR(22)
++#define T2TXC_vect_num 22
++
++/* LF-Receiver End of Burst Interrupt */
++#define LFREOB_vect _VECTOR(23)
++#define LFREOB_vect_num 23
++
++/* External Input Clock break down Interrupt */
++#define EXCM_vect _VECTOR(24)
++#define EXCM_vect_num 24
++
++/* EEPROM Ready Interrupt */
++#define EEREADY_vect _VECTOR(25)
++#define EEREADY_vect_num 25
++
++/* Store Program Memory Ready */
++#define SPM_RDY_vect _VECTOR(26)
++#define SPM_RDY_vect_num 26
++
++#define _VECTORS_SIZE 54
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 320
++#define E2PAGESIZE 4
++#define E2END 0x013F
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 2
++
++/* Low Fuse Byte */
++#define FUSE_TSRDI (unsigned char)~_BV(0)
++#define FUSE_BODEN (unsigned char)~_BV(1)
++#define FUSE_FRCFS (unsigned char)~_BV(2)
++#define FUSE_WDRCON (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_EELOCK (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x82
++
++
++#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/ioa6286.h avr-libc-1.8.0/include/avr/ioa6286.h
+--- avr-libc-1.8.0.orig/include/avr/ioa6286.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/ioa6286.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,705 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATA6286_H_INCLUDED
++#define _AVR_ATA6286_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "ioa6286.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x0E] */
++
++#define CMCR _SFR_IO8(0x0F)
++#define CMM0 0
++#define CMM1 1
++#define SRCD 2
++#define CMONEN 3
++#define CCS 4
++#define ECINS 5
++#define CMCCE 7
++
++#define CMSR _SFR_IO8(0x10)
++#define ECF 0
++
++#define T2CRA _SFR_IO8(0x11)
++#define T2OTM 0
++#define T2CTM 1
++#define T2CR 2
++#define T2CRM 3
++#define T2ICS 5
++#define T2TS 6
++#define T2E 7
++
++#define T2CRB _SFR_IO8(0x12)
++#define T2SCE 0
++
++/* Reserved [0x13] */
++
++#define T3CRA _SFR_IO8(0x14)
++#define T3AC 0
++#define T3SCE 1
++#define T3CR 2
++#define T3TS 6
++#define T3E 7
++
++/* Reserved [0x15] */
++
++#define VMCSR _SFR_IO8(0x16)
++#define VMEN 0
++#define VMLS0 1
++#define VMLS1 2
++#define VMLS2 3
++#define VMIM 4
++#define VMF 5
++#define BODPD 6
++#define BODLS 7
++
++#define PCIFR _SFR_IO8(0x17)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define LFFR _SFR_IO8(0x18)
++#define LFWPF 0
++#define LFBF 1
++#define LFEDF 2
++#define LFRF 3
++
++#define SSFR _SFR_IO8(0x19)
++#define MSENF 0
++#define MSENO 1
++
++#define T10IFR _SFR_IO8(0x1A)
++#define T0F 0
++#define T1F 1
++
++#define T2IFR _SFR_IO8(0x1B)
++#define T2OFF 0
++#define T2COF 1
++#define T2ICF 2
++#define T2RXF 3
++#define T2TXF 4
++#define T2TCF 5
++
++#define T3IFR _SFR_IO8(0x1C)
++#define T3OFF 0
++#define T3COAF 1
++#define T3COBF 2
++#define T3ICF 3
++
++#define EIFR _SFR_IO8(0x1D)
++#define INTF0 0
++#define INTF1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define PCICR _SFR_IO8(0x23)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EIMSK _SFR_IO8(0x24)
++#define INT0 0
++#define INT1 1
++
++/* Reserved [0x25..0x26] */
++
++#define SVCR _SFR_IO8(0x27)
++
++#define SCR _SFR_IO8(0x28)
++#define SMS 0
++#define SEN0 1
++#define SEN1 2
++#define SMEN 3
++
++#define SCCR _SFR_IO8(0x29)
++#define SRCC0 0
++#define SRCC1 1
++#define SCCS0 2
++#define SCCS1 3
++#define SCCS2 4
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++#define T2MDR _SFR_IO8(0x2F)
++
++#define LFRR _SFR_IO8(0x30)
++
++/* Reserved [0x31] */
++
++#define LFCDR _SFR_IO8(0x32)
++#define LFDO 0
++#define LFRST 6
++#define LFSCE 7
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define TSRF 5
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++#define LFRB _SFR_IO8(0x36)
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SELFPRGEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++#define T1CR _SFR_IO8(0x38)
++#define T1PS0 0
++#define T1PS1 1
++#define T1PS2 2
++#define T1CS0 3
++#define T1CS1 4
++#define T1CS2 5
++#define T1IE 7
++
++#define T0CR _SFR_IO8(0x39)
++#define T0PAS0 0
++#define T0PAS1 1
++#define T0PAS2 2
++#define T0IE 3
++#define T0PR 4
++#define T0PBS0 5
++#define T0PBS1 6
++#define T0PBS2 7
++
++/* Reserved [0x3A] */
++
++#define CMIMR _SFR_IO8(0x3B)
++#define ECIE 0
++
++#define CLKPR _SFR_IO8(0x3C)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLTPS0 3
++#define CLTPS1 4
++#define CLTPS2 5
++#define CLPCE 7
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDPS0 0
++#define WDPS1 1
++#define WDPS2 2
++#define WDE 3
++#define WDCE 4
++
++#define SIMSK _SFR_MEM8(0x61)
++#define MSIE 0
++
++/* Reserved [0x62..0x63] */
++
++#define TSCR _SFR_MEM8(0x64)
++#define TSSD 0
++
++#define SRCCAL _SFR_MEM8(0x65)
++
++#define FRCCAL _SFR_MEM8(0x66)
++
++#define MSVCAL _SFR_MEM8(0x67)
++
++/* Reserved [0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++#define PCMSK0 _SFR_MEM8(0x6A)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6B)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++
++#define PCMSK2 _SFR_MEM8(0x6C)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++/* Reserved [0x6D] */
++
++#define T2ICRL _SFR_MEM8(0x6E)
++
++#define T2ICR _SFR_MEM8(0x6F)
++
++/* Combine T2CORL and T2CORH */
++#define T2COR _SFR_MEM16(0x70)
++
++#define T2CORL _SFR_MEM8(0x70)
++#define T2CORH _SFR_MEM8(0x71)
++
++#define T2MRA _SFR_MEM8(0x72)
++#define T2CS0 0
++#define T2CS1 1
++#define T2CS2 2
++#define T2CE0 3
++#define T2CE1 4
++#define T2CNC 5
++#define T2TP0 6
++#define T2TP1 7
++
++#define T2MRB _SFR_MEM8(0x73)
++#define T2M0 0
++#define T2M1 1
++#define T2M2 2
++#define T2M3 3
++#define T2TOP 4
++#define T2CPOL 6
++#define T2SSIE 7
++
++#define T2IMR _SFR_MEM8(0x74)
++#define T2OIM 0
++#define T2CIM 1
++#define T2CPIM 2
++#define T2RXIM 3
++#define T2TXIM 4
++#define T2TCIM 5
++
++/* Reserved [0x75] */
++
++/* Combine T3ICRL and T3ICRH */
++#define T3ICR _SFR_MEM16(0x76)
++
++#define T3ICRL _SFR_MEM8(0x76)
++#define T3ICRH _SFR_MEM8(0x77)
++
++/* Combine T3CORAL and T3CORAH */
++#define T3CORA _SFR_MEM16(0x78)
++
++#define T3CORAL _SFR_MEM8(0x78)
++#define T3CORAH _SFR_MEM8(0x79)
++
++/* Combine T3CORBL and T3CORBH */
++#define T3CORB _SFR_MEM16(0x7A)
++
++#define T3CORBL _SFR_MEM8(0x7A)
++#define T3CORBH _SFR_MEM8(0x7B)
++
++#define T3MRA _SFR_MEM8(0x7C)
++#define T3CS0 0
++#define T3CS1 1
++#define T3CS2 2
++#define T3CE0 3
++#define T3CE1 4
++#define T3CNC 5
++#define T3ICS0 6
++#define T3ICS1 7
++
++#define T3MRB _SFR_MEM8(0x7D)
++#define T3M0 0
++#define T3M1 1
++#define T3M2 2
++#define T3TOP 4
++
++#define T3CRB _SFR_MEM8(0x7E)
++#define T3CTMA 0
++#define T3SAMA 1
++#define T3CRMA 2
++#define T3CTMB 3
++#define T3SAMB 4
++#define T3CRMB 5
++#define T3CPRM 6
++
++#define T3IMR _SFR_MEM8(0x7F)
++#define T3OIM 0
++#define T3CAIM 1
++#define T3CBIM 2
++#define T3CPIM 3
++
++/* Reserved [0x80] */
++
++#define LFIMR _SFR_MEM8(0x81)
++#define LFWIM 0
++#define LFBIM 1
++#define LFEIM 2
++
++#define LFRCR _SFR_MEM8(0x82)
++#define LFEN 0
++#define LFBM 1
++#define LFWM0 2
++#define LFWM1 3
++#define LFRSS 4
++#define LFCS0 5
++#define LFCS1 6
++#define LFCS2 7
++
++#define LFHCR _SFR_MEM8(0x83)
++
++/* Combine LFIDCL and LFIDCH */
++#define LFIDC _SFR_MEM16(0x84)
++
++#define LFIDCL _SFR_MEM8(0x84)
++#define LFIDCH _SFR_MEM8(0x85)
++
++/* Combine LFCALL and LFCALH */
++#define LFCAL _SFR_MEM16(0x86)
++
++#define LFCALL _SFR_MEM8(0x86)
++#define LFCALH _SFR_MEM8(0x87)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(5)
++#define PCINT2_vect_num 5
++
++/* Voltage Monitor Interrupt */
++#define INTVM_vect _VECTOR(6)
++#define INTVM_vect_num 6
++
++/* Sensor Interface Interrupt */
++#define SENINT_vect _VECTOR(7)
++#define SENINT_vect_num 7
++
++/* Timer0 Interval Interrupt */
++#define INTT0_vect _VECTOR(8)
++#define INTT0_vect_num 8
++
++/* LF-Receiver Wake-up Interrupt */
++#define LFWP_vect _VECTOR(9)
++#define LFWP_vect_num 9
++
++/* Timer/Counter3 Capture Event */
++#define T3CAP_vect _VECTOR(10)
++#define T3CAP_vect_num 10
++
++/* Timer/Counter3 Compare Match A */
++#define T3COMA_vect _VECTOR(11)
++#define T3COMA_vect_num 11
++
++/* Timer/Counter3 Compare Match B */
++#define T3COMB_vect _VECTOR(12)
++#define T3COMB_vect_num 12
++
++/* Timer/Counter3 Overflow */
++#define T3OVF_vect _VECTOR(13)
++#define T3OVF_vect_num 13
++
++/* Timer/Counter2 Capture Event */
++#define T2CAP_vect _VECTOR(14)
++#define T2CAP_vect_num 14
++
++/* Timer/Counter2 Compare Match */
++#define T2COM_vect _VECTOR(15)
++#define T2COM_vect_num 15
++
++/* Timer/Counter2 Overflow */
++#define T2OVF_vect _VECTOR(16)
++#define T2OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPISTC_vect _VECTOR(17)
++#define SPISTC_vect_num 17
++
++/* LF Receive Buffer Interrupt */
++#define LFRXB_vect _VECTOR(18)
++#define LFRXB_vect_num 18
++
++/* Timer1 Interval Interrupt */
++#define INTT1_vect _VECTOR(19)
++#define INTT1_vect_num 19
++
++/* Timer2 SSI Receive Buffer Interrupt */
++#define T2RXB_vect _VECTOR(20)
++#define T2RXB_vect_num 20
++
++/* Timer2 SSI Transmit Buffer Interrupt */
++#define T2TXB_vect _VECTOR(21)
++#define T2TXB_vect_num 21
++
++/* Timer2 SSI Transmit Complete Interrupt */
++#define T2TXC_vect _VECTOR(22)
++#define T2TXC_vect_num 22
++
++/* LF-Receiver End of Burst Interrupt */
++#define LFREOB_vect _VECTOR(23)
++#define LFREOB_vect_num 23
++
++/* External Input Clock break down Interrupt */
++#define EXCM_vect _VECTOR(24)
++#define EXCM_vect_num 24
++
++/* EEPROM Ready Interrupt */
++#define EEREADY_vect _VECTOR(25)
++#define EEREADY_vect_num 25
++
++/* Store Program Memory Ready */
++#define SPM_RDY_vect _VECTOR(26)
++#define SPM_RDY_vect_num 26
++
++#define _VECTORS_SIZE 54
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 320
++#define E2PAGESIZE 4
++#define E2END 0x013F
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 2
++
++/* Low Fuse Byte */
++#define FUSE_TSRDI (unsigned char)~_BV(0)
++#define FUSE_BODEN (unsigned char)~_BV(1)
++#define FUSE_FRCFS (unsigned char)~_BV(2)
++#define FUSE_WDRCON (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_EELOCK (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x82
++
++
++#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/io.h avr-libc-1.8.0/include/avr/io.h
+--- avr-libc-1.8.0.orig/include/avr/io.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/io.h 2013-01-18 09:50:25.000000000 +0100
+@@ -162,8 +162,12 @@
+ # include <avr/iom1284p.h>
+ #elif defined (__AVR_ATmega128RFA1__)
+ # include <avr/iom128rfa1.h>
++#elif defined (__AVR_ATmega128RFA2__)
++# include <avr/iom128rfa2.h>
+ #elif defined (__AVR_ATmega128RFR2__)
+ # include <avr/iom128rfr2.h>
++#elif defined (__AVR_ATmega256RFA2__)
++# include <avr/iom256rfa2.h>
+ #elif defined (__AVR_ATmega256RFR2__)
+ # include <avr/iom256rfr2.h>
+ #elif defined (__AVR_ATmega2560__)
+@@ -188,6 +192,8 @@
+ # include <avr/iousb1286.h>
+ #elif defined (__AVR_AT90USB1287__)
+ # include <avr/iousb1287.h>
++#elif defined (__AVR_ATmega64RFA2__)
++# include <avr/iom64rfa2.h>
+ #elif defined (__AVR_ATmega64RFR2__)
+ # include <avr/iom64rfr2.h>
+ #elif defined (__AVR_ATmega64__)
+@@ -336,6 +342,8 @@
+ # include <avr/iom16hvb.h>
+ #elif defined (__AVR_ATmega16HVBREVB__)
+ # include <avr/iom16hvbrevb.h>
++#elif defined (__AVR_ATmega26HVG__)
++# include <avr/iom26hvg.h>
+ #elif defined (__AVR_ATmega8__)
+ # include <avr/iom8.h>
+ #elif defined (__AVR_ATmega8A__)
+@@ -354,6 +362,8 @@
+ # include <avr/iom88a.h>
+ #elif defined (__AVR_ATmega88P__)
+ # include <avr/iom88p.h>
++#elif defined (__AVR_ATmega48HVF__)
++# include <avr/iom48hvf.h>
+ #elif defined (__AVR_ATmega88PA__)
+ # include <avr/iom88pa.h>
+ #elif defined (__AVR_ATmega8515__)
+@@ -424,6 +434,8 @@
+ # include <avr/iotn84.h>
+ #elif defined (__AVR_ATtiny84A__)
+ # include <avr/iotn84a.h>
++#elif defined (__AVR_ATtiny841__)
++# include <avr/iotn841.h>
+ #elif defined (__AVR_ATtiny261__)
+ # include <avr/iotn261.h>
+ #elif defined (__AVR_ATtiny261A__)
+@@ -452,6 +464,18 @@
+ # include <avr/iotn1634.h>
+ #elif defined (__AVR_AT90SCR100__)
+ # include <avr/io90scr100.h>
++#elif defined (__AVR_ATMXT112SL__)
++# include <avr/iomxt112sl.h>
++#elif defined (__AVR_ATMXT224__)
++# include <avr/iomxt224.h>
++#elif defined (__AVR_ATMXT224E__)
++# include <avr/iomxt224e.h>
++#elif defined (__AVR_ATMXT336S__)
++# include <avr/iomxt336s.h>
++#elif defined (__AVR_ATMXT540S__)
++# include <avr/iomxt540s.h>
++#elif defined (__AVR_ATMXT540SREVA__)
++# include <avr/iomxt540sreva.h>
+ #elif defined (__AVR_ATxmega16A4__)
+ # include <avr/iox16a4.h>
+ #elif defined (__AVR_ATxmega16A4U__)
+@@ -468,5 +492,7 @@
+ #elif defined (__AVR_ATxmega32E5__)
+ # include <avr/iox32e5.h>
++#elif defined (__AVR_ATxmega32X1__)
++# include <avr/iox32x1.h>
+ #elif defined (__AVR_ATxmega64A1__)
+ # include <avr/iox64a1.h>
+ #elif defined (__AVR_ATxmega64A1U__)
+@@ -540,12 +562,16 @@
+ # include <avr/iox384d3.h>
+ #elif defined (__AVR_ATA5790__)
+ # include <avr/ioa5790.h>
++#elif defined (__AVR_ATA5790N__)
++# include <avr/ioa5790n.h>
+ #elif defined (__AVR_ATA5272__)
+ # include <avr/ioa5272.h>
+ #elif defined (__AVR_ATA5505__)
+ # include <avr/ioa5505.h>
+ #elif defined (__AVR_ATA5795__)
+ # include <avr/ioa5795.h>
++#elif defined (__AVR_ATA5831__)
++# include <avr/ioa5831.h>
+ #elif defined (__AVR_ATA6285__)
+ # include <avr/ioa6285.h>
+ #elif defined (__AVR_ATA6286__)
+diff -urN avr-libc-1.8.0.orig/include/avr/iom103.h avr-libc-1.8.0/include/avr/iom103.h
+--- avr-libc-1.8.0.orig/include/avr/iom103.h 2011-12-29 09:51:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom103.h 2013-01-18 09:50:25.000000000 +0100
+@@ -202,7 +202,7 @@
+ /* Timer/Counter Interrupt MaSK register */
+ #define TIMSK _SFR_IO8(0x37)
+
+-/* Èxternal Interrupt Flag Register */
++/* �xternal Interrupt Flag Register */
+ #define EIFR _SFR_IO8(0x38)
+
+ /* External Interrupt MaSK register */
+@@ -377,7 +377,7 @@
+ #define INT1 1
+ #define INT0 0
+
+-/* Èxternal Interrupt Flag Register */
++/* �xternal Interrupt Flag Register */
+ #define INTF7 7
+ #define INTF6 6
+ #define INTF5 5
+diff -urN avr-libc-1.8.0.orig/include/avr/iom1284.h avr-libc-1.8.0/include/avr/iom1284.h
+--- avr-libc-1.8.0.orig/include/avr/iom1284.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom1284.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,997 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA1284_H_INCLUDED
++#define _AVR_ATMEGA1284_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom1284.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++#define TIFR3 _SFR_IO8(0x18)
++#define TOV3 0
++#define OCF3A 1
++#define OCF3B 2
++#define ICF3 5
++
++/* Reserved [0x19..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++#define PCIF3 3
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3A] */
++
++#define RAMPZ _SFR_IO8(0x3B)
++
++/* Reserved [0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRSPI 2
++#define PRTIM1 3
++#define PRUSART0 1
++#define PRUSART1 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++#define PRR1 _SFR_MEM8(0x65)
++#define PRTIM3 0
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++#define PCIE3 3
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++#define TIMSK3 _SFR_MEM8(0x71)
++#define TOIE3 0
++#define OCIE3A 1
++#define OCIE3B 2
++#define ICIE3 5
++
++/* Reserved [0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++#define PCINT24 0
++#define PCINT25 1
++#define PCINT26 2
++#define PCINT27 3
++#define PCINT28 4
++#define PCINT29 5
++#define PCINT30 6
++#define PCINT31 7
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0x8F] */
++
++#define TCCR3A _SFR_MEM8(0x90)
++#define WGM30 0
++#define WGM31 1
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3B _SFR_MEM8(0x91)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3C _SFR_MEM8(0x92)
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x93] */
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x94)
++
++#define TCNT3L _SFR_MEM8(0x94)
++#define TCNT3H _SFR_MEM8(0x95)
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x96)
++
++#define ICR3L _SFR_MEM8(0x96)
++#define ICR3H _SFR_MEM8(0x97)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x98)
++
++#define OCR3AL _SFR_MEM8(0x98)
++#define OCR3AH _SFR_MEM8(0x99)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x9A)
++
++#define OCR3BL _SFR_MEM8(0x9A)
++#define OCR3BH _SFR_MEM8(0x9B)
++
++/* Reserved [0x9C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(4)
++#define PCINT0_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(5)
++#define PCINT1_vect_num 5
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(6)
++#define PCINT2_vect_num 6
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(7)
++#define PCINT3_vect_num 7
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(8)
++#define WDT_vect_num 8
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(9)
++#define TIMER2_COMPA_vect_num 9
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(10)
++#define TIMER2_COMPB_vect_num 10
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(11)
++#define TIMER2_OVF_vect_num 11
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(12)
++#define TIMER1_CAPT_vect_num 12
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(13)
++#define TIMER1_COMPA_vect_num 13
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(14)
++#define TIMER1_COMPB_vect_num 14
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(15)
++#define TIMER1_OVF_vect_num 15
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(16)
++#define TIMER0_COMPA_vect_num 16
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(17)
++#define TIMER0_COMPB_vect_num 17
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(18)
++#define TIMER0_OVF_vect_num 18
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(19)
++#define SPI__STC_vect_num 19
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(20)
++#define USART0__RX_vect_num 20
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(21)
++#define USART0__UDRE_vect_num 21
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(22)
++#define USART0__TX_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(24)
++#define ADC_vect_num 24
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(25)
++#define EE_READY_vect_num 25
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(26)
++#define TWI_vect_num 26
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(27)
++#define SPM_READY_vect_num 27
++
++/* USART1 RX complete */
++#define USART1_RX_vect _VECTOR(28)
++#define USART1_RX_vect_num 28
++
++/* USART1 Data Register Empty */
++#define USART1_UDRE_vect _VECTOR(29)
++#define USART1_UDRE_vect_num 29
++
++/* USART1 TX complete */
++#define USART1_TX_vect _VECTOR(30)
++#define USART1_TX_vect_num 30
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(31)
++#define TIMER3_CAPT_vect_num 31
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(32)
++#define TIMER3_COMPA_vect_num 32
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(33)
++#define TIMER3_COMPB_vect_num 33
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(34)
++#define TIMER3_OVF_vect_num 34
++
++#define _VECTORS_SIZE 140
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHEND 0x1FFFF
++#define RAMSTART 0x0100
++#define RAMSIZE 16384
++#define RAMEND 0x40FF
++#define E2START 0
++#define E2SIZE 4096
++#define E2PAGESIZE 8
++#define E2END 0x0FFF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x06
++
++
++#endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom128a.h avr-libc-1.8.0/include/avr/iom128a.h
+--- avr-libc-1.8.0.orig/include/avr/iom128a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom128a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,956 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA128A_H_INCLUDED
++#define _AVR_ATMEGA128A_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom128a.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINF _SFR_IO8(0x00)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define PINE _SFR_IO8(0x01)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x02)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x03)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x04)
++#endif
++#define ADCW _SFR_IO16(0x04)
++
++#define ADCL _SFR_IO8(0x04)
++#define ADCH _SFR_IO8(0x05)
++
++#define ADCSRA _SFR_IO8(0x06)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADFR 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADMUX _SFR_IO8(0x07)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define ACSR _SFR_IO8(0x08)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define UBRR0L _SFR_IO8(0x09)
++
++#define UCSR0B _SFR_IO8(0x0A)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0A _SFR_IO8(0x0B)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UDR0 _SFR_IO8(0x0C)
++
++#define SPCR _SFR_IO8(0x0D)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x0E)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x0F)
++
++#define PIND _SFR_IO8(0x10)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x11)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x12)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINC _SFR_IO8(0x13)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x14)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x15)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PINB _SFR_IO8(0x16)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x17)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x18)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINA _SFR_IO8(0x19)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x1A)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x1B)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x1D)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x1E)
++
++#define EEARL _SFR_IO8(0x1E)
++#define EEARH _SFR_IO8(0x1F)
++
++#define SFIOR _SFR_IO8(0x20)
++#define ACME 3
++#define PSR321 0
++#define PSR0 1
++#define PUD 2
++#define TSM 7
++
++#define WDTCR _SFR_IO8(0x21)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define OCDR _SFR_IO8(0x22)
++#define OCDR0 0
++#define OCDR1 1
++#define OCDR2 2
++#define OCDR3 3
++#define OCDR4 4
++#define OCDR5 5
++#define OCDR6 6
++#define OCDR7 7
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++#define OCR2 _SFR_IO8(0x23)
++
++#define TCNT2 _SFR_IO8(0x24)
++
++#define TCCR2 _SFR_IO8(0x25)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM20 4
++#define COM21 5
++#define WGM20 6
++#define FOC2 7
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_IO16(0x26)
++
++#define ICR1L _SFR_IO8(0x26)
++#define ICR1H _SFR_IO8(0x27)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_IO16(0x28)
++
++#define OCR1BL _SFR_IO8(0x28)
++#define OCR1BH _SFR_IO8(0x29)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_IO16(0x2A)
++
++#define OCR1AL _SFR_IO8(0x2A)
++#define OCR1AH _SFR_IO8(0x2B)
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_IO16(0x2C)
++
++#define TCNT1L _SFR_IO8(0x2C)
++#define TCNT1H _SFR_IO8(0x2D)
++
++#define TCCR1B _SFR_IO8(0x2E)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1A _SFR_IO8(0x2F)
++#define WGM10 0
++#define WGM11 1
++#define COM1C0 2
++#define COM1C1 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define ASSR _SFR_IO8(0x30)
++#define TCR0UB 0
++#define OCR0UB 1
++#define TCN0UB 2
++#define AS0 3
++
++#define OCR0 _SFR_IO8(0x31)
++
++#define TCNT0 _SFR_IO8(0x32)
++
++#define TCCR0 _SFR_IO8(0x33)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM00 4
++#define COM01 5
++#define WGM00 6
++#define FOC0 7
++
++#define MCUCSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define JTRF 4
++#define JTD 7
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define SM2 2
++#define SM0 3
++#define SM1 4
++#define SE 5
++#define SRW10 6
++#define SRE 7
++
++#define TIFR _SFR_IO8(0x36)
++#define TOV0 0
++#define OCF0 1
++#define TOV1 2
++#define OCF1B 3
++#define OCF1A 4
++#define ICF1 5
++#define TOV2 6
++#define OCF2 7
++
++#define TIMSK _SFR_IO8(0x37)
++#define TOIE0 0
++#define OCIE0 1
++#define TOIE1 2
++#define OCIE1B 3
++#define OCIE1A 4
++#define TICIE1 5
++#define TOIE2 6
++#define OCIE2 7
++
++#define EIFR _SFR_IO8(0x38)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++#define INTF3 3
++#define INTF4 4
++#define INTF5 5
++#define INTF6 6
++#define INTF7 7
++
++#define EIMSK _SFR_IO8(0x39)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++#define INT3 3
++#define INT4 4
++#define INT5 5
++#define INT6 6
++#define INT7 7
++
++#define EICRB _SFR_IO8(0x3A)
++#define ISC40 0
++#define ISC41 1
++#define ISC50 2
++#define ISC51 3
++#define ISC60 4
++#define ISC61 5
++#define ISC70 6
++#define ISC71 7
++
++#define RAMPZ _SFR_IO8(0x3B)
++#define RAMPZ0 0
++
++#define XDIV _SFR_IO8(0x3C)
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++/* Reserved [0x40..0x60] */
++
++#define DDRF _SFR_MEM8(0x61)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_MEM8(0x62)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_MEM8(0x63)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_MEM8(0x64)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_MEM8(0x65)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++/* Reserved [0x66..0x67] */
++
++#define SPMCSR _SFR_MEM8(0x68)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x69] */
++
++#define EICRA _SFR_MEM8(0x6A)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++#define ISC30 6
++#define ISC31 7
++
++/* Reserved [0x6B] */
++
++#define XMCRB _SFR_MEM8(0x6C)
++#define XMM0 0
++#define XMM1 1
++#define XMM2 2
++#define XMBK 7
++
++#define XMCRA _SFR_MEM8(0x6D)
++#define SRW11 1
++#define SRW00 2
++#define SRW01 3
++#define SRL0 4
++#define SRL1 5
++#define SRL2 6
++
++/* Reserved [0x6E] */
++
++#define OSCCAL _SFR_MEM8(0x6F)
++
++#define TWBR _SFR_MEM8(0x70)
++
++#define TWSR _SFR_MEM8(0x71)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0x72)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0x73)
++
++#define TWCR _SFR_MEM8(0x74)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++/* Reserved [0x75..0x77] */
++
++/* Combine OCR1CL and OCR1CH */
++#define OCR1C _SFR_MEM16(0x78)
++
++#define OCR1CL _SFR_MEM8(0x78)
++#define OCR1CH _SFR_MEM8(0x79)
++
++#define TCCR1C _SFR_MEM8(0x7A)
++#define FOC1C 5
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x7B] */
++
++#define ETIFR _SFR_MEM8(0x7C)
++#define OCF1C 0
++#define OCF3C 1
++#define TOV3 2
++#define OCF3B 3
++#define OCF3A 4
++#define ICF3 5
++
++#define ETIMSK _SFR_MEM8(0x7D)
++#define OCIE1C 0
++#define OCIE3C 1
++#define TOIE3 2
++#define OCIE3B 3
++#define OCIE3A 4
++#define TICIE3 5
++
++/* Reserved [0x7E..0x7F] */
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x80)
++
++#define ICR3L _SFR_MEM8(0x80)
++#define ICR3H _SFR_MEM8(0x81)
++
++/* Combine OCR3CL and OCR3CH */
++#define OCR3C _SFR_MEM16(0x82)
++
++#define OCR3CL _SFR_MEM8(0x82)
++#define OCR3CH _SFR_MEM8(0x83)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x84)
++
++#define OCR3BL _SFR_MEM8(0x84)
++#define OCR3BH _SFR_MEM8(0x85)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x86)
++
++#define OCR3AL _SFR_MEM8(0x86)
++#define OCR3AH _SFR_MEM8(0x87)
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x88)
++
++#define TCNT3L _SFR_MEM8(0x88)
++#define TCNT3H _SFR_MEM8(0x89)
++
++#define TCCR3B _SFR_MEM8(0x8A)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3A _SFR_MEM8(0x8B)
++#define WGM30 0
++#define WGM31 1
++#define COM3C0 2
++#define COM3C1 3
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3C _SFR_MEM8(0x8C)
++#define FOC3C 5
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x8D..0x8F] */
++
++#define UBRR0H _SFR_MEM8(0x90)
++
++/* Reserved [0x91..0x94] */
++
++#define UCSR0C _SFR_MEM8(0x95)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0x96..0x97] */
++
++#define UBRR1H _SFR_MEM8(0x98)
++
++#define UBRR1L _SFR_MEM8(0x99)
++
++#define UCSR1B _SFR_MEM8(0x9A)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1A _SFR_MEM8(0x9B)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UDR1 _SFR_MEM8(0x9C)
++
++#define UCSR1C _SFR_MEM8(0x9D)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL1 6
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* External Interrupt Request 3 */
++#define INT3_vect _VECTOR(4)
++#define INT3_vect_num 4
++
++/* External Interrupt Request 4 */
++#define INT4_vect _VECTOR(5)
++#define INT4_vect_num 5
++
++/* External Interrupt Request 5 */
++#define INT5_vect _VECTOR(6)
++#define INT5_vect_num 6
++
++/* External Interrupt Request 6 */
++#define INT6_vect _VECTOR(7)
++#define INT6_vect_num 7
++
++/* External Interrupt Request 7 */
++#define INT7_vect _VECTOR(8)
++#define INT7_vect_num 8
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(9)
++#define TIMER2_COMP_vect_num 9
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(10)
++#define TIMER2_OVF_vect_num 10
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(11)
++#define TIMER1_CAPT_vect_num 11
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(12)
++#define TIMER1_COMPA_vect_num 12
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(13)
++#define TIMER1_COMPB_vect_num 13
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(14)
++#define TIMER1_OVF_vect_num 14
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(15)
++#define TIMER0_COMP_vect_num 15
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(16)
++#define TIMER0_OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(17)
++#define SPI__STC_vect_num 17
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(18)
++#define USART0__RX_vect_num 18
++
++/* USART0 Data Register Empty */
++#define USART0__UDRE_vect _VECTOR(19)
++#define USART0__UDRE_vect_num 19
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(20)
++#define USART0__TX_vect_num 20
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(21)
++#define ADC_vect_num 21
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(22)
++#define EE_READY_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* Timer/Counter1 Compare Match C */
++#define TIMER1_COMPC_vect _VECTOR(24)
++#define TIMER1_COMPC_vect_num 24
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(25)
++#define TIMER3_CAPT_vect_num 25
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(26)
++#define TIMER3_COMPA_vect_num 26
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(27)
++#define TIMER3_COMPB_vect_num 27
++
++/* Timer/Counter3 Compare Match C */
++#define TIMER3_COMPC_vect _VECTOR(28)
++#define TIMER3_COMPC_vect_num 28
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(29)
++#define TIMER3_OVF_vect_num 29
++
++/* USART1, Rx Complete */
++#define USART1__RX_vect _VECTOR(30)
++#define USART1__RX_vect_num 30
++
++/* USART1, Data Register Empty */
++#define USART1__UDRE_vect _VECTOR(31)
++#define USART1__UDRE_vect_num 31
++
++/* USART1, Tx Complete */
++#define USART1__TX_vect _VECTOR(32)
++#define USART1__TX_vect_num 32
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(33)
++#define TWI_vect_num 33
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(34)
++#define SPM_READY_vect_num 34
++
++#define _VECTORS_SIZE 140
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHEND 0x1FFFF
++#define RAMSTART 0x0100
++#define RAMSIZE 4096
++#define RAMEND 0x10FF
++#define E2START 0
++#define E2SIZE 4096
++#define E2PAGESIZE 8
++#define E2END 0x0FFF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_BODEN (unsigned char)~_BV(6)
++#define FUSE_BODLEVEL (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_CKOPT (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_WDTON (unsigned char)~_BV(0)
++#define FUSE_M103C (unsigned char)~_BV(1)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom164a.h avr-libc-1.8.0/include/avr/iom164a.h
+--- avr-libc-1.8.0.orig/include/avr/iom164a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom164a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom164.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom164pa.h avr-libc-1.8.0/include/avr/iom164pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom164pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom164pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,917 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA164PA_H_INCLUDED
++#define _AVR_ATMEGA164PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom164pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++/* Reserved [0x18..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++#define PCIF3 3
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR0 _SFR_IO8(0x2C)
++#define SPR00 0
++#define SPR10 1
++#define CPHA0 2
++#define CPOL0 3
++#define MSTR0 4
++#define DORD0 5
++#define SPE0 6
++#define SPIE0 7
++
++#define SPSR0 _SFR_IO8(0x2D)
++#define SPI2X0 0
++#define WCOL0 6
++#define SPIF0 7
++
++#define SPDR0 _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRSPI 2
++#define PRTIM1 3
++#define PRUSART0 1
++#define PRUSART1 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++#define PCIE3 3
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++/* Reserved [0x71..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++#define PCINT24 0
++#define PCINT25 1
++#define PCINT26 2
++#define PCINT27 3
++#define PCINT28 4
++#define PCINT29 5
++#define PCINT30 6
++#define PCINT31 7
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(4)
++#define PCINT0_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(5)
++#define PCINT1_vect_num 5
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(6)
++#define PCINT2_vect_num 6
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(7)
++#define PCINT3_vect_num 7
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(8)
++#define WDT_vect_num 8
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(9)
++#define TIMER2_COMPA_vect_num 9
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(10)
++#define TIMER2_COMPB_vect_num 10
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(11)
++#define TIMER2_OVF_vect_num 11
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(12)
++#define TIMER1_CAPT_vect_num 12
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(13)
++#define TIMER1_COMPA_vect_num 13
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(14)
++#define TIMER1_COMPB_vect_num 14
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(15)
++#define TIMER1_OVF_vect_num 15
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(16)
++#define TIMER0_COMPA_vect_num 16
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(17)
++#define TIMER0_COMPB_vect_num 17
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(18)
++#define TIMER0_OVF_vect_num 18
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(19)
++#define SPI__STC_vect_num 19
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(20)
++#define USART0__RX_vect_num 20
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(21)
++#define USART0__UDRE_vect_num 21
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(22)
++#define USART0__TX_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(24)
++#define ADC_vect_num 24
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(25)
++#define EE_READY_vect_num 25
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(26)
++#define TWI_vect_num 26
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(27)
++#define SPM_READY_vect_num 27
++
++/* USART1 RX complete */
++#define USART1_RX_vect _VECTOR(28)
++#define USART1_RX_vect_num 28
++
++/* USART1 Data Register Empty */
++#define USART1_UDRE_vect _VECTOR(29)
++#define USART1_UDRE_vect_num 29
++
++/* USART1 TX complete */
++#define USART1_TX_vect _VECTOR(30)
++#define USART1_TX_vect_num 30
++
++#define _VECTORS_SIZE 124
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 1024
++#define RAMEND 0x04FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x0A
++
++
++#endif /* #ifdef _AVR_ATMEGA164PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom164p.h avr-libc-1.8.0/include/avr/iom164p.h
+--- avr-libc-1.8.0.orig/include/avr/iom164p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom164p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom164.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom165a.h avr-libc-1.8.0/include/avr/iom165a.h
+--- avr-libc-1.8.0.orig/include/avr/iom165a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom165a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom165.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom165pa.h avr-libc-1.8.0/include/avr/iom165pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom165pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom165pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,820 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA165PA_H_INCLUDED
++#define _AVR_ATMEGA165PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom165pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++
++/* Reserved [0x18..0x1B] */
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define PCIF0 4
++#define PCIF1 5
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define PCIE0 4
++#define PCIE1 5
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR310 0
++#define TSM 7
++#define PSR2 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM0A0 4
++#define COM0A1 5
++#define WGM00 6
++#define FOC0A 7
++
++/* Reserved [0x25] */
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++/* Reserved [0x28..0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6D] */
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++
++/* Reserved [0x71..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM2A0 4
++#define COM2A1 5
++#define WGM20 6
++#define FOC2A 7
++
++/* Reserved [0xB1] */
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++/* Reserved [0xB4..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++#define EXCLK 4
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++/* Reserved [0xBB..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(13)
++#define USART0__RX_vect_num 13
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(14)
++#define USART0__UDRE_vect_num 14
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(15)
++#define USART0__TX_vect_num 15
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(16)
++#define USI_START_vect_num 16
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(17)
++#define USI_OVERFLOW_vect_num 17
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(18)
++#define ANALOG_COMP_vect_num 18
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(19)
++#define ADC_vect_num 19
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(20)
++#define EE_READY_vect_num 20
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(21)
++#define SPM_READY_vect_num 21
++
++#define _VECTORS_SIZE 88
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 1024
++#define RAMEND 0x04FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_RSTDISBL (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x07
++
++
++#endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom168a.h avr-libc-1.8.0/include/avr/iom168a.h
+--- avr-libc-1.8.0.orig/include/avr/iom168a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom168a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom168.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom168pa.h avr-libc-1.8.0/include/avr/iom168pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom168pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom168pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,765 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA168PA_H_INCLUDED
++#define _AVR_ATMEGA168PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom168pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++/* Reserved [0x18..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++/* Reserved [0x31..0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SELFPRGEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++/* Reserved [0x71..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ACME 6
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT2_vect _VECTOR(5)
++#define PCINT2_vect_num 5
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(6)
++#define WDT_vect_num 6
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(7)
++#define TIMER2_COMPA_vect_num 7
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPB_vect _VECTOR(8)
++#define TIMER2_COMPB_vect_num 8
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(9)
++#define TIMER2_OVF_vect_num 9
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(10)
++#define TIMER1_CAPT_vect_num 10
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(11)
++#define TIMER1_COMPA_vect_num 11
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(12)
++#define TIMER1_COMPB_vect_num 12
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(13)
++#define TIMER1_OVF_vect_num 13
++
++/* TimerCounter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(14)
++#define TIMER0_COMPA_vect_num 14
++
++/* TimerCounter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(15)
++#define TIMER0_COMPB_vect_num 15
++
++/* Timer/Couner0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(16)
++#define TIMER0_OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(17)
++#define SPI__STC_vect_num 17
++
++/* USART Rx Complete */
++#define USART__RX_vect _VECTOR(18)
++#define USART__RX_vect_num 18
++
++/* USART, Data Register Empty */
++#define USART__UDRE_vect _VECTOR(19)
++#define USART__UDRE_vect_num 19
++
++/* USART Tx Complete */
++#define USART__TX_vect _VECTOR(20)
++#define USART__TX_vect_num 20
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(21)
++#define ADC_vect_num 21
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(22)
++#define EE_READY_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* Two-wire Serial Interface */
++#define TWI_vect _VECTOR(24)
++#define TWI_vect_num 24
++
++/* Store Program Memory Read */
++#define SPM_Ready_vect _VECTOR(25)
++#define SPM_Ready_vect_num 25
++
++#define _VECTORS_SIZE 104
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 1024
++#define RAMEND 0x04FF
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x0B
++
++
++#endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom169a.h avr-libc-1.8.0/include/avr/iom169a.h
+--- avr-libc-1.8.0.orig/include/avr/iom169a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom169a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom169.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom324a.h avr-libc-1.8.0/include/avr/iom324a.h
+--- avr-libc-1.8.0.orig/include/avr/iom324a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom324a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,915 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA324A_H_INCLUDED
++#define _AVR_ATMEGA324A_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom324a.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++/* Reserved [0x18..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++#define PCIF3 3
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR0 _SFR_IO8(0x2C)
++#define SPR00 0
++#define SPR10 1
++#define CPHA0 2
++#define CPOL0 3
++#define MSTR0 4
++#define DORD0 5
++#define SPE0 6
++#define SPIE0 7
++
++#define SPSR0 _SFR_IO8(0x2D)
++#define SPI2X0 0
++#define WCOL0 6
++#define SPIF0 7
++
++#define SPDR0 _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRUSART1 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++#define PCIE3 3
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++/* Reserved [0x71..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++#define PCINT24 0
++#define PCINT25 1
++#define PCINT26 2
++#define PCINT27 3
++#define PCINT28 4
++#define PCINT29 5
++#define PCINT30 6
++#define PCINT31 7
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(4)
++#define PCINT0_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(5)
++#define PCINT1_vect_num 5
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(6)
++#define PCINT2_vect_num 6
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(7)
++#define PCINT3_vect_num 7
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(8)
++#define WDT_vect_num 8
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(9)
++#define TIMER2_COMPA_vect_num 9
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(10)
++#define TIMER2_COMPB_vect_num 10
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(11)
++#define TIMER2_OVF_vect_num 11
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(12)
++#define TIMER1_CAPT_vect_num 12
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(13)
++#define TIMER1_COMPA_vect_num 13
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(14)
++#define TIMER1_COMPB_vect_num 14
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(15)
++#define TIMER1_OVF_vect_num 15
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(16)
++#define TIMER0_COMPA_vect_num 16
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(17)
++#define TIMER0_COMPB_vect_num 17
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(18)
++#define TIMER0_OVF_vect_num 18
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(19)
++#define SPI__STC_vect_num 19
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(20)
++#define USART0__RX_vect_num 20
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(21)
++#define USART0__UDRE_vect_num 21
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(22)
++#define USART0__TX_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(24)
++#define ADC_vect_num 24
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(25)
++#define EE_READY_vect_num 25
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(26)
++#define TWI_vect_num 26
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(27)
++#define SPM_READY_vect_num 27
++
++/* USART1 RX complete */
++#define USART1_RX_vect _VECTOR(28)
++#define USART1_RX_vect_num 28
++
++/* USART1 Data Register Empty */
++#define USART1_UDRE_vect _VECTOR(29)
++#define USART1_UDRE_vect_num 29
++
++/* USART1 TX complete */
++#define USART1_TX_vect _VECTOR(30)
++#define USART1_TX_vect_num 30
++
++#define _VECTORS_SIZE 124
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x15
++
++
++#endif /* #ifdef _AVR_ATMEGA324A_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom324p.h avr-libc-1.8.0/include/avr/iom324p.h
+--- avr-libc-1.8.0.orig/include/avr/iom324p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom324p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,917 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA324P_H_INCLUDED
++#define _AVR_ATMEGA324P_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom324p.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++/* Reserved [0x18..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++#define PCIF3 3
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR0 _SFR_IO8(0x2C)
++#define SPR00 0
++#define SPR10 1
++#define CPHA0 2
++#define CPOL0 3
++#define MSTR0 4
++#define DORD0 5
++#define SPE0 6
++#define SPIE0 7
++
++#define SPSR0 _SFR_IO8(0x2D)
++#define SPI2X0 0
++#define WCOL0 6
++#define SPIF0 7
++
++#define SPDR0 _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRUSART1 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++#define PCIE3 3
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++/* Reserved [0x71..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++#define PCINT24 0
++#define PCINT25 1
++#define PCINT26 2
++#define PCINT27 3
++#define PCINT28 4
++#define PCINT29 5
++#define PCINT30 6
++#define PCINT31 7
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(4)
++#define PCINT0_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(5)
++#define PCINT1_vect_num 5
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(6)
++#define PCINT2_vect_num 6
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(7)
++#define PCINT3_vect_num 7
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(8)
++#define WDT_vect_num 8
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(9)
++#define TIMER2_COMPA_vect_num 9
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(10)
++#define TIMER2_COMPB_vect_num 10
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(11)
++#define TIMER2_OVF_vect_num 11
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(12)
++#define TIMER1_CAPT_vect_num 12
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(13)
++#define TIMER1_COMPA_vect_num 13
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(14)
++#define TIMER1_COMPB_vect_num 14
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(15)
++#define TIMER1_OVF_vect_num 15
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(16)
++#define TIMER0_COMPA_vect_num 16
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(17)
++#define TIMER0_COMPB_vect_num 17
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(18)
++#define TIMER0_OVF_vect_num 18
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(19)
++#define SPI__STC_vect_num 19
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(20)
++#define USART0__RX_vect_num 20
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(21)
++#define USART0__UDRE_vect_num 21
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(22)
++#define USART0__TX_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(24)
++#define ADC_vect_num 24
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(25)
++#define EE_READY_vect_num 25
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(26)
++#define TWI_vect_num 26
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(27)
++#define SPM_READY_vect_num 27
++
++/* USART1 RX complete */
++#define USART1_RX_vect _VECTOR(28)
++#define USART1_RX_vect_num 28
++
++/* USART1 Data Register Empty */
++#define USART1_UDRE_vect _VECTOR(29)
++#define USART1_UDRE_vect_num 29
++
++/* USART1 TX complete */
++#define USART1_TX_vect _VECTOR(30)
++#define USART1_TX_vect_num 30
++
++#define _VECTORS_SIZE 124
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x08
++
++
++#endif /* #ifdef _AVR_ATMEGA324P_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3250a.h avr-libc-1.8.0/include/avr/iom3250a.h
+--- avr-libc-1.8.0.orig/include/avr/iom3250a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3250a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom3250.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3250pa.h avr-libc-1.8.0/include/avr/iom3250pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom3250pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3250pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,886 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA3250PA_H_INCLUDED
++#define _AVR_ATMEGA3250PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom3250pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++
++/* Reserved [0x18..0x1B] */
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define PCIF0 4
++#define PCIF1 5
++#define PCIF2 6
++#define PCIF3 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define PCIE0 4
++#define PCIE1 5
++#define PCIE2 6
++#define PCIE3 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR310 0
++#define TSM 7
++#define PSR2 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM0A0 4
++#define COM0A1 5
++#define WGM00 6
++#define FOC0A 7
++
++/* Reserved [0x25] */
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++/* Reserved [0x28..0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRLCD 4
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++
++/* Reserved [0x71..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM2A0 4
++#define COM2A1 5
++#define WGM20 6
++#define FOC2A 7
++
++/* Reserved [0xB1] */
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++/* Reserved [0xB4..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++#define EXCLK 4
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++/* Reserved [0xBB..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7..0xD7] */
++
++#define PINH _SFR_MEM8(0xD8)
++#define PINH7 7
++#define PINH6 6
++#define PINH5 5
++#define PINH4 4
++#define PINH3 3
++#define PINH2 2
++#define PINH1 1
++#define PINH0 0
++
++#define DDRH _SFR_MEM8(0xD9)
++#define DDRH7 7
++#define DDRH6 6
++#define DDRH5 5
++#define DDRH4 4
++#define DDRH3 3
++#define DDRH2 2
++#define DDRH1 1
++#define DDRH0 0
++
++#define PORTH _SFR_MEM8(0xDA)
++#define PORTH7 7
++#define PORTH6 6
++#define PORTH5 5
++#define PORTH4 4
++#define PORTH3 3
++#define PORTH2 2
++#define PORTH1 1
++#define PORTH0 0
++
++#define PINJ _SFR_MEM8(0xDB)
++#define PINJ7 7
++#define PINJ6 6
++#define PINJ5 5
++#define PINJ4 4
++#define PINJ3 3
++#define PINJ2 2
++#define PINJ1 1
++#define PINJ0 0
++
++#define DDRJ _SFR_MEM8(0xDC)
++#define DDRJ7 7
++#define DDRJ6 6
++#define DDRJ5 5
++#define DDRJ4 4
++#define DDRJ3 3
++#define DDRJ2 2
++#define DDRJ1 1
++#define DDRJ0 0
++
++#define PORTJ _SFR_MEM8(0xDD)
++#define PORTJ7 7
++#define PORTJ6 6
++#define PORTJ5 5
++#define PORTJ4 4
++#define PORTJ3 3
++#define PORTJ2 2
++#define PORTJ1 1
++#define PORTJ0 0
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART, Rx Complete */
++#define USART__RX_vect _VECTOR(13)
++#define USART__RX_vect_num 13
++
++/* USART Data register Empty */
++#define USART__UDRE_vect _VECTOR(14)
++#define USART__UDRE_vect_num 14
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(15)
++#define USART0__TX_vect_num 15
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(16)
++#define USI_START_vect_num 16
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(17)
++#define USI_OVERFLOW_vect_num 17
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(18)
++#define ANALOG_COMP_vect_num 18
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(19)
++#define ADC_vect_num 19
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(20)
++#define EE_READY_vect_num 20
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(21)
++#define SPM_READY_vect_num 21
++
++/* RESERVED */
++#define NOT_USED_vect _VECTOR(22)
++#define NOT_USED_vect_num 22
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(23)
++#define PCINT2_vect_num 23
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(24)
++#define PCINT3_vect_num 24
++
++#define _VECTORS_SIZE 100
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_RSTDISBL (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x0E
++
++
++#endif /* #ifdef _AVR_ATMEGA3250PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3250p.h avr-libc-1.8.0/include/avr/iom3250p.h
+--- avr-libc-1.8.0.orig/include/avr/iom3250p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3250p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom3250.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom325a.h avr-libc-1.8.0/include/avr/iom325a.h
+--- avr-libc-1.8.0.orig/include/avr/iom325a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom325a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom325.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom325pa.h avr-libc-1.8.0/include/avr/iom325pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom325pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom325pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,808 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA325PA_H_INCLUDED
++#define _AVR_ATMEGA325PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom325pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++
++/* Reserved [0x18..0x1B] */
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define PCIF0 4
++#define PCIF1 5
++#define PCIF2 6
++#define PCIF3 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define PCIE0 4
++#define PCIE1 5
++#define PCIE2 6
++#define PCIE3 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR310 0
++#define TSM 7
++#define PSR2 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM0A0 4
++#define COM0A1 5
++#define WGM00 6
++#define FOC0A 7
++
++/* Reserved [0x25] */
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++/* Reserved [0x28..0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRLCD 4
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++
++/* Reserved [0x6D] */
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++
++/* Reserved [0x71..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ACME 6
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM2A0 4
++#define COM2A1 5
++#define WGM20 6
++#define FOC2A 7
++
++/* Reserved [0xB1] */
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++/* Reserved [0xB4..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++#define EXCLK 4
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++/* Reserved [0xBB..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(13)
++#define USART0__RX_vect_num 13
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(14)
++#define USART0__UDRE_vect_num 14
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(15)
++#define USART0__TX_vect_num 15
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(16)
++#define USI_START_vect_num 16
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(17)
++#define USI_OVERFLOW_vect_num 17
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(18)
++#define ANALOG_COMP_vect_num 18
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(19)
++#define ADC_vect_num 19
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(20)
++#define EE_READY_vect_num 20
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(21)
++#define SPM_READY_vect_num 21
++
++#define _VECTORS_SIZE 88
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_RSTDISBL (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x0D
++
++
++#endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom325p.h avr-libc-1.8.0/include/avr/iom325p.h
+--- avr-libc-1.8.0.orig/include/avr/iom325p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom325p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom325.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom328.h avr-libc-1.8.0/include/avr/iom328.h
+--- avr-libc-1.8.0.orig/include/avr/iom328.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom328.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom328p.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3290a.h avr-libc-1.8.0/include/avr/iom3290a.h
+--- avr-libc-1.8.0.orig/include/avr/iom3290a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3290a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom3290.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3290pa.h avr-libc-1.8.0/include/avr/iom3290pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom3290pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3290pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,967 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA3290PA_H_INCLUDED
++#define _AVR_ATMEGA3290PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom3290pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++
++/* Reserved [0x18..0x1B] */
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define PCIF0 4
++#define PCIF1 5
++#define PCIF2 6
++#define PCIF3 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define PCIE0 4
++#define PCIE1 5
++#define PCIE2 6
++#define PCIE3 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR310 0
++#define TSM 7
++#define PSR2 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM0A0 4
++#define COM0A1 5
++#define WGM00 6
++#define FOC0A 7
++
++/* Reserved [0x25] */
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++/* Reserved [0x28..0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRLCD 4
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++
++/* Reserved [0x71..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM2A0 4
++#define COM2A1 5
++#define WGM20 6
++#define FOC2A 7
++
++/* Reserved [0xB1] */
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++/* Reserved [0xB4..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++#define EXCLK 4
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++/* Reserved [0xBB..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7..0xD7] */
++
++#define PINH _SFR_MEM8(0xD8)
++#define PINH7 7
++#define PINH6 6
++#define PINH5 5
++#define PINH4 4
++#define PINH3 3
++#define PINH2 2
++#define PINH1 1
++#define PINH0 0
++
++#define DDRH _SFR_MEM8(0xD9)
++#define DDRH7 7
++#define DDRH6 6
++#define DDRH5 5
++#define DDRH4 4
++#define DDRH3 3
++#define DDRH2 2
++#define DDRH1 1
++#define DDRH0 0
++
++#define PORTH _SFR_MEM8(0xDA)
++#define PORTH7 7
++#define PORTH6 6
++#define PORTH5 5
++#define PORTH4 4
++#define PORTH3 3
++#define PORTH2 2
++#define PORTH1 1
++#define PORTH0 0
++
++#define PINJ _SFR_MEM8(0xDB)
++#define PINJ7 7
++#define PINJ6 6
++#define PINJ5 5
++#define PINJ4 4
++#define PINJ3 3
++#define PINJ2 2
++#define PINJ1 1
++#define PINJ0 0
++
++#define DDRJ _SFR_MEM8(0xDC)
++#define DDRJ7 7
++#define DDRJ6 6
++#define DDRJ5 5
++#define DDRJ4 4
++#define DDRJ3 3
++#define DDRJ2 2
++#define DDRJ1 1
++#define DDRJ0 0
++
++#define PORTJ _SFR_MEM8(0xDD)
++#define PORTJ7 7
++#define PORTJ6 6
++#define PORTJ5 5
++#define PORTJ4 4
++#define PORTJ3 3
++#define PORTJ2 2
++#define PORTJ1 1
++#define PORTJ0 0
++
++/* Reserved [0xDE..0xE3] */
++
++#define LCDCRA _SFR_MEM8(0xE4)
++#define LCDBL 0
++#define LCDCCD 1
++#define LCDBD 2
++#define LCDIE 3
++#define LCDIF 4
++#define LCDAB 6
++#define LCDEN 7
++
++#define LCDCRB _SFR_MEM8(0xE5)
++#define LCDPM0 0
++#define LCDPM1 1
++#define LCDPM2 2
++#define LCDPM3 3
++#define LCDMUX0 4
++#define LCDMUX1 5
++#define LCD2B 6
++#define LCDCS 7
++
++#define LCDFRR _SFR_MEM8(0xE6)
++#define LCDCD0 0
++#define LCDCD1 1
++#define LCDCD2 2
++#define LCDPS0 4
++#define LCDPS1 5
++#define LCDPS2 6
++
++#define LCDCCR _SFR_MEM8(0xE7)
++#define LCDCC0 0
++#define LCDCC1 1
++#define LCDCC2 2
++#define LCDCC3 3
++#define LCDMDT 4
++#define LCDDC0 5
++#define LCDDC1 6
++#define LCDDC2 7
++
++/* Reserved [0xE8..0xEB] */
++
++#define LCDDR0 _SFR_MEM8(0xEC)
++
++#define LCDDR1 _SFR_MEM8(0xED)
++
++#define LCDDR2 _SFR_MEM8(0xEE)
++
++#define LCDDR3 _SFR_MEM8(0xEF)
++
++#define LCDDR4 _SFR_MEM8(0xF0)
++
++#define LCDDR5 _SFR_MEM8(0xF1)
++
++#define LCDDR6 _SFR_MEM8(0xF2)
++
++#define LCDDR7 _SFR_MEM8(0xF3)
++
++#define LCDDR8 _SFR_MEM8(0xF4)
++
++#define LCDDR9 _SFR_MEM8(0xF5)
++
++#define LCDDR10 _SFR_MEM8(0xF6)
++
++#define LCDDR11 _SFR_MEM8(0xF7)
++
++#define LCDDR12 _SFR_MEM8(0xF8)
++
++#define LCDDR13 _SFR_MEM8(0xF9)
++
++#define LCDDR14 _SFR_MEM8(0xFA)
++
++#define LCDDR15 _SFR_MEM8(0xFB)
++
++#define LCDDR16 _SFR_MEM8(0xFC)
++
++#define LCDDR17 _SFR_MEM8(0xFD)
++
++#define LCDDR18 _SFR_MEM8(0xFE)
++
++#define LCDDR19 _SFR_MEM8(0xFF)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART, Rx Complete */
++#define USART__RX_vect _VECTOR(13)
++#define USART__RX_vect_num 13
++
++/* USART Data register Empty */
++#define USART__UDRE_vect _VECTOR(14)
++#define USART__UDRE_vect_num 14
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(15)
++#define USART0__TX_vect_num 15
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(16)
++#define USI_START_vect_num 16
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(17)
++#define USI_OVERFLOW_vect_num 17
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(18)
++#define ANALOG_COMP_vect_num 18
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(19)
++#define ADC_vect_num 19
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(20)
++#define EE_READY_vect_num 20
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(21)
++#define SPM_READY_vect_num 21
++
++/* LCD Start of Frame */
++#define LCD_vect _VECTOR(22)
++#define LCD_vect_num 22
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(23)
++#define PCINT2_vect_num 23
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(24)
++#define PCINT3_vect_num 24
++
++#define _VECTORS_SIZE 100
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_RSTDISBL (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x0C
++
++
++#endif /* #ifdef _AVR_ATMEGA3290PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom329a.h avr-libc-1.8.0/include/avr/iom329a.h
+--- avr-libc-1.8.0.orig/include/avr/iom329a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom329a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom329.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom329pa.h avr-libc-1.8.0/include/avr/iom329pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom329pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom329pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom329.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom329p.h avr-libc-1.8.0/include/avr/iom329p.h
+--- avr-libc-1.8.0.orig/include/avr/iom329p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom329p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,1034 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA329P_H_INCLUDED
++#define _AVR_ATMEGA329P_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom329p.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++
++/* Reserved [0x18..0x1B] */
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define PCIF0 4
++#define PCIF1 5
++#define PCIF2 6
++#define PCIF3 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define PCIE0 4
++#define PCIE1 5
++#define PCIE2 6
++#define PCIE3 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSR310 0
++#define TSM 7
++#define PSR2 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM0A0 4
++#define COM0A1 5
++#define WGM00 6
++#define FOC0A 7
++
++/* Reserved [0x25] */
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++/* Reserved [0x28..0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCR _SFR_MEM8(0x60)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRLCD 4
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67..0x68] */
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++/* Reserved [0x6D] */
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++
++/* Reserved [0x71..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM2A0 4
++#define COM2A1 5
++#define WGM20 6
++#define FOC2A 7
++
++/* Reserved [0xB1] */
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++/* Reserved [0xB4..0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++#define EXCLK 4
++
++/* Reserved [0xB7] */
++
++#define USICR _SFR_MEM8(0xB8)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_MEM8(0xB9)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_MEM8(0xBA)
++
++/* Reserved [0xBB..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7..0xE3] */
++
++#define LCDCRA _SFR_MEM8(0xE4)
++#define LCDBL 0
++#define LCDCCD 1
++#define LCDBD 2
++#define LCDIE 3
++#define LCDIF 4
++#define LCDAB 6
++#define LCDEN 7
++
++#define LCDCRB _SFR_MEM8(0xE5)
++#define LCDPM0 0
++#define LCDPM1 1
++#define LCDPM2 2
++#define LCDPM3 3
++#define LCDMUX0 4
++#define LCDMUX1 5
++#define LCD2B 6
++#define LCDCS 7
++
++#define LCDFRR _SFR_MEM8(0xE6)
++#define LCDCD0 0
++#define LCDCD1 1
++#define LCDCD2 2
++#define LCDPS0 4
++#define LCDPS1 5
++#define LCDPS2 6
++
++#define LCDCCR _SFR_MEM8(0xE7)
++#define LCDCC0 0
++#define LCDCC1 1
++#define LCDCC2 2
++#define LCDCC3 3
++#define LCDMDT 4
++#define LCDDC0 5
++#define LCDDC1 6
++#define LCDDC2 7
++
++/* Reserved [0xE8..0xEB] */
++
++#define LCDDR0 _SFR_MEM8(0xEC)
++#define SEG000 0
++#define SEG001 1
++#define SEG002 2
++#define SEG003 3
++#define SEG004 4
++#define SEG005 5
++#define SEG006 6
++#define SEG007 7
++
++#define LCDDR1 _SFR_MEM8(0xED)
++#define SEG008 0
++#define SEG009 1
++#define SEG010 2
++#define SEG011 3
++#define SEG012 4
++#define SEG013 5
++#define SEG014 6
++#define SEG015 7
++
++#define LCDDR2 _SFR_MEM8(0xEE)
++#define SEG016 0
++#define SEG017 1
++#define SEG018 2
++#define SEG019 3
++#define SEG020 4
++#define SEG021 5
++#define SEG022 6
++#define SEG023 7
++
++#define LCDDR3 _SFR_MEM8(0xEF)
++#define SEG024 0
++#define SEG025 1
++#define SEG026 2
++#define SEG027 3
++#define SEG028 4
++#define SEG029 5
++#define SEG030 6
++#define SEG031 7
++
++/* Reserved [0xF0] */
++
++#define LCDDR5 _SFR_MEM8(0xF1)
++#define SEG100 0
++#define SEG101 1
++#define SEG102 2
++#define SEG103 3
++#define SEG104 4
++#define SEG105 5
++#define SEG106 6
++#define SEG107 7
++
++#define LCDDR6 _SFR_MEM8(0xF2)
++#define SEG108 0
++#define SEG109 1
++#define SEG110 2
++#define SEG111 3
++#define SEG112 4
++#define SEG113 5
++#define SEG114 6
++#define SEG115 7
++
++#define LCDDR7 _SFR_MEM8(0xF3)
++#define SEG116 0
++#define SEG117 1
++#define SEG118 2
++#define SEG119 3
++#define SEG120 4
++#define SEG121 5
++#define SEG122 6
++#define SEG123 7
++
++#define LCDDR8 _SFR_MEM8(0xF4)
++#define SEG124 0
++#define SEG125 1
++#define SEG126 2
++#define SEG127 3
++#define SEG128 4
++#define SEG129 5
++#define SEG130 6
++#define SEG131 7
++
++/* Reserved [0xF5] */
++
++#define LCDDR10 _SFR_MEM8(0xF6)
++#define SEG200 0
++#define SEG201 1
++#define SEG202 2
++#define SEG203 3
++#define SEG204 4
++#define SEG205 5
++#define SEG206 6
++#define SEG207 7
++
++#define LCDDR11 _SFR_MEM8(0xF7)
++#define SEG208 0
++#define SEG209 1
++#define SEG210 2
++#define SEG211 3
++#define SEG212 4
++#define SEG213 5
++#define SEG214 6
++#define SEG215 7
++
++#define LCDDR12 _SFR_MEM8(0xF8)
++#define SEG216 0
++#define SEG217 1
++#define SEG218 2
++#define SEG219 3
++#define SEG220 4
++#define SEG221 5
++#define SEG222 6
++#define SEG223 7
++
++#define LCDDR13 _SFR_MEM8(0xF9)
++#define SEG224 0
++#define SEG225 1
++#define SEG226 2
++#define SEG227 3
++#define SEG228 4
++#define SEG229 5
++#define SEG230 6
++#define SEG231 7
++
++/* Reserved [0xFA] */
++
++#define LCDDR15 _SFR_MEM8(0xFB)
++#define SEG300 0
++#define SEG301 1
++#define SEG302 2
++#define SEG304 4
++#define SEG305 5
++#define SEG306 6
++#define SEG307 7
++
++#define LCDDR16 _SFR_MEM8(0xFC)
++#define SEG308 0
++#define SEG309 1
++#define SEG310 2
++#define SEG311 3
++#define SEG312 4
++#define SEG313 5
++#define SEG314 6
++#define SEG315 7
++
++#define LCDDR17 _SFR_MEM8(0xFD)
++#define SEG316 0
++#define SEG317 1
++#define SEG318 2
++#define SEG319 3
++#define SEG320 4
++#define SEG321 5
++#define SEG322 6
++#define SEG323 7
++
++#define LCDDR18 _SFR_MEM8(0xFE)
++#define SEG324 0
++#define SEG325 1
++#define SEG326 2
++#define SEG327 3
++#define SEG328 4
++#define SEG329 5
++#define SEG330 6
++#define SEG331 7
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(13)
++#define USART0__RX_vect_num 13
++
++/* USART0 Data register Empty */
++#define USART0__UDRE_vect _VECTOR(14)
++#define USART0__UDRE_vect_num 14
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(15)
++#define USART0__TX_vect_num 15
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(16)
++#define USI_START_vect_num 16
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(17)
++#define USI_OVERFLOW_vect_num 17
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(18)
++#define ANALOG_COMP_vect_num 18
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(19)
++#define ADC_vect_num 19
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(20)
++#define EE_READY_vect_num 20
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(21)
++#define SPM_READY_vect_num 21
++
++/* LCD Start of Frame */
++#define LCD_vect _VECTOR(22)
++#define LCD_vect_num 22
++
++#define _VECTORS_SIZE 92
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 2048
++#define RAMEND 0x08FF
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_RSTDISBL (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x0B
++
++
++#endif /* #ifdef _AVR_ATMEGA329P_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom32a.h avr-libc-1.8.0/include/avr/iom32a.h
+--- avr-libc-1.8.0.orig/include/avr/iom32a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom32a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,596 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA32A_H_INCLUDED
++#define _AVR_ATMEGA32A_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom32a.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define TWBR _SFR_IO8(0x00)
++
++#define TWSR _SFR_IO8(0x01)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_IO8(0x02)
++
++#define TWDR _SFR_IO8(0x03)
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x04)
++#endif
++#define ADCW _SFR_IO16(0x04)
++
++#define ADCL _SFR_IO8(0x04)
++#define ADCH _SFR_IO8(0x05)
++
++#define ADCSRA _SFR_IO8(0x06)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADMUX _SFR_IO8(0x07)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define ACSR _SFR_IO8(0x08)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define UBRRL _SFR_IO8(0x09)
++
++#define UCSRB _SFR_IO8(0x0A)
++#define TXB8 0
++#define RXB8 1
++#define UCSZ2 2
++#define TXEN 3
++#define RXEN 4
++#define UDRIE 5
++#define TXCIE 6
++#define RXCIE 7
++
++#define UCSRA _SFR_IO8(0x0B)
++#define MPCM 0
++#define U2X 1
++#define UPE 2
++#define DOR 3
++#define FE 4
++#define UDRE 5
++#define TXC 6
++#define RXC 7
++
++#define UDR _SFR_IO8(0x0C)
++
++#define SPCR _SFR_IO8(0x0D)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x0E)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x0F)
++
++#define PIND _SFR_IO8(0x10)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x11)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x12)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINC _SFR_IO8(0x13)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x14)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x15)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PINB _SFR_IO8(0x16)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x17)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x18)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINA _SFR_IO8(0x19)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x1A)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x1B)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x1D)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x1E)
++
++#define EEARL _SFR_IO8(0x1E)
++#define EEARH _SFR_IO8(0x1F)
++
++#define UCSRC _SFR_IO8(0x20)
++#define UCPOL 0
++#define UCSZ0 1
++#define UCSZ1 2
++#define USBS 3
++#define UPM0 4
++#define UPM1 5
++#define UMSEL 6
++#define URSEL 7
++
++#define UBRRH _SFR_IO8(0x20)
++
++#define WDTCR _SFR_IO8(0x21)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDTOE 4
++
++#define ASSR _SFR_IO8(0x22)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++
++#define OCR2 _SFR_IO8(0x23)
++
++#define TCNT2 _SFR_IO8(0x24)
++
++#define TCCR2 _SFR_IO8(0x25)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM20 4
++#define COM21 5
++#define WGM20 6
++#define FOC2 7
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_IO16(0x26)
++
++#define ICR1L _SFR_IO8(0x26)
++#define ICR1H _SFR_IO8(0x27)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_IO16(0x28)
++
++#define OCR1BL _SFR_IO8(0x28)
++#define OCR1BH _SFR_IO8(0x29)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_IO16(0x2A)
++
++#define OCR1AL _SFR_IO8(0x2A)
++#define OCR1AH _SFR_IO8(0x2B)
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_IO16(0x2C)
++
++#define TCNT1L _SFR_IO8(0x2C)
++#define TCNT1H _SFR_IO8(0x2D)
++
++#define TCCR1B _SFR_IO8(0x2E)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1A _SFR_IO8(0x2F)
++#define WGM10 0
++#define WGM11 1
++#define FOC1B 2
++#define FOC1A 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define SFIOR _SFR_IO8(0x30)
++#define ACME 3
++#define ADTS0 5
++#define ADTS1 6
++#define ADTS2 7
++
++#define OSCCAL _SFR_IO8(0x31)
++
++#define TCNT0 _SFR_IO8(0x32)
++
++#define TCCR0 _SFR_IO8(0x33)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM00 4
++#define COM01 5
++#define WGM00 6
++#define FOC0 7
++
++#define MCUCSR _SFR_IO8(0x34)
++#define ISC2 6
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define JTRF 4
++#define JTD 7
++
++#define MCUCR _SFR_IO8(0x35)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define SM0 4
++#define SM1 5
++#define SM2 6
++#define SE 7
++
++#define TWCR _SFR_IO8(0x36)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define SPMCR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++#define TIFR _SFR_IO8(0x38)
++#define TOV0 0
++#define OCF0 1
++#define TOV2 6
++#define OCF2 7
++#define TOV1 2
++#define OCF1B 3
++#define OCF1A 4
++#define ICF1 5
++
++#define TIMSK _SFR_IO8(0x39)
++#define TOIE0 0
++#define OCIE0 1
++#define TOIE2 6
++#define OCIE2 7
++#define TOIE1 2
++#define OCIE1B 3
++#define OCIE1A 4
++#define TICIE1 5
++
++#define GIFR _SFR_IO8(0x3A)
++#define INTF2 5
++#define INTF0 6
++#define INTF1 7
++
++#define GICR _SFR_IO8(0x3B)
++#define IVCE 0
++#define IVSEL 1
++#define INT2 5
++#define INT0 6
++#define INT1 7
++
++#define OCR0 _SFR_IO8(0x3C)
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(4)
++#define TIMER2_COMP_vect_num 4
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(5)
++#define TIMER2_OVF_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(10)
++#define TIMER0_COMP_vect_num 10
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(11)
++#define TIMER0_OVF_vect_num 11
++
++/* Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(12)
++#define SPI__STC_vect_num 12
++
++/* USART, Rx Complete */
++#define USART__RXC_vect _VECTOR(13)
++#define USART__RXC_vect_num 13
++
++/* USART Data Register Empty */
++#define USART__UDRE_vect _VECTOR(14)
++#define USART__UDRE_vect_num 14
++
++/* USART, Tx Complete */
++#define USART__TXC_vect _VECTOR(15)
++#define USART__TXC_vect_num 15
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(16)
++#define ADC_vect_num 16
++
++/* EEPROM Ready */
++#define EE_RDY_vect _VECTOR(17)
++#define EE_RDY_vect_num 17
++
++/* Analog Comparator */
++#define ANA_COMP_vect _VECTOR(18)
++#define ANA_COMP_vect_num 18
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(19)
++#define TWI_vect_num 19
++
++/* Store Program Memory Ready */
++#define SPM_RDY_vect _VECTOR(20)
++#define SPM_RDY_vect_num 20
++
++#define _VECTORS_SIZE 84
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 128
++#define FLASHEND 0x7FFF
++#define RAMSTART 0x0060
++#define RAMSIZE 2048
++#define RAMEND 0x085F
++#define E2START 0
++#define E2SIZE 1024
++#define E2PAGESIZE 4
++#define E2END 0x03FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 2
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_BODEN (unsigned char)~_BV(6)
++#define FUSE_BODLEVEL (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_CKOPT (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom48a.h avr-libc-1.8.0/include/avr/iom48a.h
+--- avr-libc-1.8.0.orig/include/avr/iom48a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom48a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom48.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom48pa.h avr-libc-1.8.0/include/avr/iom48pa.h
+--- avr-libc-1.8.0.orig/include/avr/iom48pa.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom48pa.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,757 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA48PA_H_INCLUDED
++#define _AVR_ATMEGA48PA_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom48pa.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++/* Reserved [0x0C..0x14] */
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++/* Reserved [0x18..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++#define EEARL _SFR_IO8(0x21)
++
++/* Reserved [0x22] */
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++#define PSRASY 1
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++/* Reserved [0x31..0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define PUD 4
++#define BODSE 5
++#define BODS 6
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SELFPRGEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++/* Reserved [0x71..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ACME 6
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++/* Reserved [0x7D] */
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT2_vect _VECTOR(5)
++#define PCINT2_vect_num 5
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(6)
++#define WDT_vect_num 6
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(7)
++#define TIMER2_COMPA_vect_num 7
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPB_vect _VECTOR(8)
++#define TIMER2_COMPB_vect_num 8
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(9)
++#define TIMER2_OVF_vect_num 9
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(10)
++#define TIMER1_CAPT_vect_num 10
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(11)
++#define TIMER1_COMPA_vect_num 11
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(12)
++#define TIMER1_COMPB_vect_num 12
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(13)
++#define TIMER1_OVF_vect_num 13
++
++/* TimerCounter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(14)
++#define TIMER0_COMPA_vect_num 14
++
++/* TimerCounter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(15)
++#define TIMER0_COMPB_vect_num 15
++
++/* Timer/Couner0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(16)
++#define TIMER0_OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(17)
++#define SPI__STC_vect_num 17
++
++/* USART Rx Complete */
++#define USART__RX_vect _VECTOR(18)
++#define USART__RX_vect_num 18
++
++/* USART, Data Register Empty */
++#define USART__UDRE_vect _VECTOR(19)
++#define USART__UDRE_vect_num 19
++
++/* USART Tx Complete */
++#define USART__TX_vect _VECTOR(20)
++#define USART__TX_vect_num 20
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(21)
++#define ADC_vect_num 21
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(22)
++#define EE_READY_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* Two-wire Serial Interface */
++#define TWI_vect _VECTOR(24)
++#define TWI_vect_num 24
++
++/* Store Program Memory Read */
++#define SPM_Ready_vect _VECTOR(25)
++#define SPM_Ready_vect_num 25
++
++#define _VECTORS_SIZE 52
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x0FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 256
++#define E2PAGESIZE 4
++#define E2END 0x00FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x92
++#define SIGNATURE_2 0x0A
++
++
++#endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom644a.h avr-libc-1.8.0/include/avr/iom644a.h
+--- avr-libc-1.8.0.orig/include/avr/iom644a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom644a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom644.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom6450a.h avr-libc-1.8.0/include/avr/iom6450a.h
+--- avr-libc-1.8.0.orig/include/avr/iom6450a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom6450a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom6450.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom6450p.h avr-libc-1.8.0/include/avr/iom6450p.h
+--- avr-libc-1.8.0.orig/include/avr/iom6450p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom6450p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom6450.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom645a.h avr-libc-1.8.0/include/avr/iom645a.h
+--- avr-libc-1.8.0.orig/include/avr/iom645a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom645a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom645.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom645p.h avr-libc-1.8.0/include/avr/iom645p.h
+--- avr-libc-1.8.0.orig/include/avr/iom645p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom645p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom645.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom6490a.h avr-libc-1.8.0/include/avr/iom6490a.h
+--- avr-libc-1.8.0.orig/include/avr/iom6490a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom6490a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom6490.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom6490p.h avr-libc-1.8.0/include/avr/iom6490p.h
+--- avr-libc-1.8.0.orig/include/avr/iom6490p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom6490p.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom6490.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom649a.h avr-libc-1.8.0/include/avr/iom649a.h
+--- avr-libc-1.8.0.orig/include/avr/iom649a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom649a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom649.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom64a.h avr-libc-1.8.0/include/avr/iom64a.h
+--- avr-libc-1.8.0.orig/include/avr/iom64a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom64a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,970 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA64A_H_INCLUDED
++#define _AVR_ATMEGA64A_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom64a.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINF _SFR_IO8(0x00)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define PINE _SFR_IO8(0x01)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x02)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x03)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x04)
++#endif
++#define ADCW _SFR_IO16(0x04)
++
++#define ADCL _SFR_IO8(0x04)
++#define ADCH _SFR_IO8(0x05)
++
++#define ADCSRA _SFR_IO8(0x06)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADMUX _SFR_IO8(0x07)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define ACSR _SFR_IO8(0x08)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define UBRR0L _SFR_IO8(0x09)
++
++#define UCSR0B _SFR_IO8(0x0A)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0A _SFR_IO8(0x0B)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UDR0 _SFR_IO8(0x0C)
++
++#define SPCR _SFR_IO8(0x0D)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x0E)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x0F)
++
++#define PIND _SFR_IO8(0x10)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x11)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x12)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINC _SFR_IO8(0x13)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x14)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x15)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PINB _SFR_IO8(0x16)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x17)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x18)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINA _SFR_IO8(0x19)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x1A)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x1B)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x1D)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x1E)
++
++#define EEARL _SFR_IO8(0x1E)
++#define EEARH _SFR_IO8(0x1F)
++
++#define SFIOR _SFR_IO8(0x20)
++#define ACME 3
++#define PSR321 0
++#define PSR0 1
++#define PUD 2
++#define TSM 7
++
++#define WDTCR _SFR_IO8(0x21)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define OCDR _SFR_IO8(0x22)
++#define OCDR0 0
++#define OCDR1 1
++#define OCDR2 2
++#define OCDR3 3
++#define OCDR4 4
++#define OCDR5 5
++#define OCDR6 6
++#define OCDR7 7
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++#define OCR2 _SFR_IO8(0x23)
++
++#define TCNT2 _SFR_IO8(0x24)
++
++#define TCCR2 _SFR_IO8(0x25)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM20 4
++#define COM21 5
++#define WGM20 6
++#define FOC2 7
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_IO16(0x26)
++
++#define ICR1L _SFR_IO8(0x26)
++#define ICR1H _SFR_IO8(0x27)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_IO16(0x28)
++
++#define OCR1BL _SFR_IO8(0x28)
++#define OCR1BH _SFR_IO8(0x29)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_IO16(0x2A)
++
++#define OCR1AL _SFR_IO8(0x2A)
++#define OCR1AH _SFR_IO8(0x2B)
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_IO16(0x2C)
++
++#define TCNT1L _SFR_IO8(0x2C)
++#define TCNT1H _SFR_IO8(0x2D)
++
++#define TCCR1B _SFR_IO8(0x2E)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1A _SFR_IO8(0x2F)
++#define WGM10 0
++#define WGM11 1
++#define COM1C0 2
++#define COM1C1 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define ASSR _SFR_IO8(0x30)
++#define TCR0UB 0
++#define OCR0UB 1
++#define TCN0UB 2
++#define AS0 3
++
++#define OCR0 _SFR_IO8(0x31)
++
++#define TCNT0 _SFR_IO8(0x32)
++
++#define TCCR0 _SFR_IO8(0x33)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM01 3
++#define COM00 4
++#define COM01 5
++#define WGM00 6
++#define FOC0 7
++
++#define MCUCSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++#define JTRF 4
++#define JTD 7
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVCE 0
++#define IVSEL 1
++#define SM2 2
++#define SM0 3
++#define SM1 4
++#define SE 5
++#define SRW10 6
++#define SRE 7
++
++#define TIFR _SFR_IO8(0x36)
++#define TOV0 0
++#define OCF0 1
++#define TOV1 2
++#define OCF1B 3
++#define OCF1A 4
++#define ICF1 5
++#define TOV2 6
++#define OCF2 7
++
++#define TIMSK _SFR_IO8(0x37)
++#define TOIE0 0
++#define OCIE0 1
++#define TOIE1 2
++#define OCIE1B 3
++#define OCIE1A 4
++#define TICIE1 5
++#define TOIE2 6
++#define OCIE2 7
++
++#define EIFR _SFR_IO8(0x38)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++#define INTF3 3
++#define INTF4 4
++#define INTF5 5
++#define INTF6 6
++#define INTF7 7
++
++#define EIMSK _SFR_IO8(0x39)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++#define INT3 3
++#define INT4 4
++#define INT5 5
++#define INT6 6
++#define INT7 7
++
++#define EICRB _SFR_IO8(0x3A)
++#define ISC40 0
++#define ISC41 1
++#define ISC50 2
++#define ISC51 3
++#define ISC60 4
++#define ISC61 5
++#define ISC70 6
++#define ISC71 7
++
++/* Reserved [0x3B] */
++
++#define XDIV _SFR_IO8(0x3C)
++#define XDIV0 0
++#define XDIV1 1
++#define XDIV2 2
++#define XDIV3 3
++#define XDIV4 4
++#define XDIV5 5
++#define XDIV6 6
++#define XDIVEN 7
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++/* Reserved [0x40..0x60] */
++
++#define DDRF _SFR_MEM8(0x61)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_MEM8(0x62)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_MEM8(0x63)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_MEM8(0x64)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_MEM8(0x65)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++/* Reserved [0x66..0x67] */
++
++#define SPMCSR _SFR_MEM8(0x68)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x69] */
++
++#define EICRA _SFR_MEM8(0x6A)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++#define ISC30 6
++#define ISC31 7
++
++/* Reserved [0x6B] */
++
++#define XMCRB _SFR_MEM8(0x6C)
++#define XMM0 0
++#define XMM1 1
++#define XMM2 2
++#define XMBK 7
++
++#define XMCRA _SFR_MEM8(0x6D)
++#define SRW11 1
++#define SRW00 2
++#define SRW01 3
++#define SRL0 4
++#define SRL1 5
++#define SRL2 6
++
++/* Reserved [0x6E] */
++
++#define OSCCAL _SFR_MEM8(0x6F)
++
++#define TWBR _SFR_MEM8(0x70)
++
++#define TWSR _SFR_MEM8(0x71)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0x72)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0x73)
++
++#define TWCR _SFR_MEM8(0x74)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++/* Reserved [0x75..0x77] */
++
++/* Combine OCR1CL and OCR1CH */
++#define OCR1C _SFR_MEM16(0x78)
++
++#define OCR1CL _SFR_MEM8(0x78)
++#define OCR1CH _SFR_MEM8(0x79)
++
++#define TCCR1C _SFR_MEM8(0x7A)
++#define FOC1C 5
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x7B] */
++
++#define ETIFR _SFR_MEM8(0x7C)
++#define OCF1C 0
++#define OCF3C 1
++#define TOV3 2
++#define OCF3B 3
++#define OCF3A 4
++#define ICF3 5
++
++#define ETIMSK _SFR_MEM8(0x7D)
++#define OCIE1C 0
++#define OCIE3C 1
++#define TOIE3 2
++#define OCIE3B 3
++#define OCIE3A 4
++#define TICIE3 5
++
++/* Reserved [0x7E..0x7F] */
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x80)
++
++#define ICR3L _SFR_MEM8(0x80)
++#define ICR3H _SFR_MEM8(0x81)
++
++/* Combine OCR3CL and OCR3CH */
++#define OCR3C _SFR_MEM16(0x82)
++
++#define OCR3CL _SFR_MEM8(0x82)
++#define OCR3CH _SFR_MEM8(0x83)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x84)
++
++#define OCR3BL _SFR_MEM8(0x84)
++#define OCR3BH _SFR_MEM8(0x85)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x86)
++
++#define OCR3AL _SFR_MEM8(0x86)
++#define OCR3AH _SFR_MEM8(0x87)
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x88)
++
++#define TCNT3L _SFR_MEM8(0x88)
++#define TCNT3H _SFR_MEM8(0x89)
++
++#define TCCR3B _SFR_MEM8(0x8A)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3A _SFR_MEM8(0x8B)
++#define WGM30 0
++#define WGM31 1
++#define COM3C0 2
++#define COM3C1 3
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3C _SFR_MEM8(0x8C)
++#define FOC3C 5
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x8D] */
++
++#define ADCSRB _SFR_MEM8(0x8E)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++
++/* Reserved [0x8F] */
++
++#define UBRR0H _SFR_MEM8(0x90)
++
++/* Reserved [0x91..0x94] */
++
++#define UCSR0C _SFR_MEM8(0x95)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL0 6
++
++/* Reserved [0x96..0x97] */
++
++#define UBRR1H _SFR_MEM8(0x98)
++
++#define UBRR1L _SFR_MEM8(0x99)
++
++#define UCSR1B _SFR_MEM8(0x9A)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1A _SFR_MEM8(0x9B)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UDR1 _SFR_MEM8(0x9C)
++
++#define UCSR1C _SFR_MEM8(0x9D)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL1 6
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* External Interrupt Request 3 */
++#define INT3_vect _VECTOR(4)
++#define INT3_vect_num 4
++
++/* External Interrupt Request 4 */
++#define INT4_vect _VECTOR(5)
++#define INT4_vect_num 5
++
++/* External Interrupt Request 5 */
++#define INT5_vect _VECTOR(6)
++#define INT5_vect_num 6
++
++/* External Interrupt Request 6 */
++#define INT6_vect _VECTOR(7)
++#define INT6_vect_num 7
++
++/* External Interrupt Request 7 */
++#define INT7_vect _VECTOR(8)
++#define INT7_vect_num 8
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(9)
++#define TIMER2_COMP_vect_num 9
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(10)
++#define TIMER2_OVF_vect_num 10
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(11)
++#define TIMER1_CAPT_vect_num 11
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(12)
++#define TIMER1_COMPA_vect_num 12
++
++/* Timer/Counter Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(13)
++#define TIMER1_COMPB_vect_num 13
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(14)
++#define TIMER1_OVF_vect_num 14
++
++/* Timer/Counter0 Compare Match */
++#define TIMER0_COMP_vect _VECTOR(15)
++#define TIMER0_COMP_vect_num 15
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(16)
++#define TIMER0_OVF_vect_num 16
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(17)
++#define SPI__STC_vect_num 17
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(18)
++#define USART0__RX_vect_num 18
++
++/* USART0 Data Register Empty */
++#define USART0__UDRE_vect _VECTOR(19)
++#define USART0__UDRE_vect_num 19
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(20)
++#define USART0__TX_vect_num 20
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(21)
++#define ADC_vect_num 21
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(22)
++#define EE_READY_vect_num 22
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(23)
++#define ANALOG_COMP_vect_num 23
++
++/* Timer/Counter1 Compare Match C */
++#define TIMER1_COMPC_vect _VECTOR(24)
++#define TIMER1_COMPC_vect_num 24
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(25)
++#define TIMER3_CAPT_vect_num 25
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(26)
++#define TIMER3_COMPA_vect_num 26
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(27)
++#define TIMER3_COMPB_vect_num 27
++
++/* Timer/Counter3 Compare Match C */
++#define TIMER3_COMPC_vect _VECTOR(28)
++#define TIMER3_COMPC_vect_num 28
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(29)
++#define TIMER3_OVF_vect_num 29
++
++/* USART1, Rx Complete */
++#define USART1__RX_vect _VECTOR(30)
++#define USART1__RX_vect_num 30
++
++/* USART1, Data Register Empty */
++#define USART1__UDRE_vect _VECTOR(31)
++#define USART1__UDRE_vect_num 31
++
++/* USART1, Tx Complete */
++#define USART1__TX_vect _VECTOR(32)
++#define USART1__TX_vect_num 32
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(33)
++#define TWI_vect_num 33
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(34)
++#define SPM_READY_vect_num 34
++
++#define _VECTORS_SIZE 140
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHEND 0xFFFF
++#define RAMSTART 0x0100
++#define RAMSIZE 4096
++#define RAMEND 0x10FF
++#define E2START 0
++#define E2SIZE 2048
++#define E2PAGESIZE 8
++#define E2END 0x07FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_BODEN (unsigned char)~_BV(6)
++#define FUSE_BODLEVEL (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_CKOPT (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_WDTON (unsigned char)~_BV(0)
++#define FUSE_CompMode (unsigned char)~_BV(1)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom88a.h avr-libc-1.8.0/include/avr/iom88a.h
+--- avr-libc-1.8.0.orig/include/avr/iom88a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom88a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom88.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom8a.h avr-libc-1.8.0/include/avr/iom8a.h
+--- avr-libc-1.8.0.orig/include/avr/iom8a.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom8a.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,556 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA8A_H_INCLUDED
++#define _AVR_ATMEGA8A_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom8a.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define TWBR _SFR_IO8(0x00)
++
++#define TWSR _SFR_IO8(0x01)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_IO8(0x02)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_IO8(0x03)
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x04)
++#endif
++#define ADCW _SFR_IO16(0x04)
++
++#define ADCL _SFR_IO8(0x04)
++#define ADCH _SFR_IO8(0x05)
++
++#define ADCSRA _SFR_IO8(0x06)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADFR 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADMUX _SFR_IO8(0x07)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define ACSR _SFR_IO8(0x08)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define UBRRL _SFR_IO8(0x09)
++
++#define UCSRB _SFR_IO8(0x0A)
++#define TXB8 0
++#define RXB8 1
++#define UCSZ2 2
++#define TXEN 3
++#define RXEN 4
++#define UDRIE 5
++#define TXCIE 6
++#define RXCIE 7
++
++#define UCSRA _SFR_IO8(0x0B)
++#define MPCM 0
++#define U2X 1
++#define UPE 2
++#define DOR 3
++#define FE 4
++#define UDRE 5
++#define TXC 6
++#define RXC 7
++
++#define UDR _SFR_IO8(0x0C)
++
++#define SPCR _SFR_IO8(0x0D)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x0E)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x0F)
++
++#define PIND _SFR_IO8(0x10)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x11)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x12)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINC _SFR_IO8(0x13)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x14)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x15)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PINB _SFR_IO8(0x16)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x17)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x18)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++/* Reserved [0x19..0x1B] */
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEWE 1
++#define EEMWE 2
++#define EERIE 3
++
++#define EEDR _SFR_IO8(0x1D)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x1E)
++
++#define EEARL _SFR_IO8(0x1E)
++#define EEARH _SFR_IO8(0x1F)
++
++#define UCSRC _SFR_IO8(0x20)
++#define UCPOL 0
++#define UCSZ0 1
++#define UCSZ1 2
++#define USBS 3
++#define UPM0 4
++#define UPM1 5
++#define UMSEL 6
++#define URSEL 7
++
++#define UBRRH _SFR_IO8(0x20)
++
++#define WDTCR _SFR_IO8(0x21)
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDE 3
++#define WDCE 4
++
++#define ASSR _SFR_IO8(0x22)
++#define TCR2UB 0
++#define OCR2UB 1
++#define TCN2UB 2
++#define AS2 3
++
++#define OCR2 _SFR_IO8(0x23)
++
++#define TCNT2 _SFR_IO8(0x24)
++
++#define TCCR2 _SFR_IO8(0x25)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM21 3
++#define COM20 4
++#define COM21 5
++#define WGM20 6
++#define FOC2 7
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_IO16(0x26)
++
++#define ICR1L _SFR_IO8(0x26)
++#define ICR1H _SFR_IO8(0x27)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_IO16(0x28)
++
++#define OCR1BL _SFR_IO8(0x28)
++#define OCR1BH _SFR_IO8(0x29)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_IO16(0x2A)
++
++#define OCR1AL _SFR_IO8(0x2A)
++#define OCR1AH _SFR_IO8(0x2B)
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_IO16(0x2C)
++
++#define TCNT1L _SFR_IO8(0x2C)
++#define TCNT1H _SFR_IO8(0x2D)
++
++#define TCCR1B _SFR_IO8(0x2E)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1A _SFR_IO8(0x2F)
++#define WGM10 0
++#define WGM11 1
++#define FOC1B 2
++#define FOC1A 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define SFIOR _SFR_IO8(0x30)
++#define ACME 3
++#define PSR2 1
++#define PSR10 0
++#define PUD 2
++#define ADHSM 4
++
++#define OSCCAL _SFR_IO8(0x31)
++
++#define TCNT0 _SFR_IO8(0x32)
++
++#define TCCR0 _SFR_IO8(0x33)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++
++#define MCUCSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define SM0 4
++#define SM1 5
++#define SM2 6
++#define SE 7
++
++#define TWCR _SFR_IO8(0x36)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define SPMCR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define RWWSB 6
++#define SPMIE 7
++
++#define TIFR _SFR_IO8(0x38)
++#define TOV0 0
++#define TOV1 2
++#define OCF1B 3
++#define OCF1A 4
++#define ICF1 5
++#define TOV2 6
++#define OCF2 7
++
++#define TIMSK _SFR_IO8(0x39)
++#define TOIE0 0
++#define TOIE1 2
++#define OCIE1B 3
++#define OCIE1A 4
++#define TICIE1 5
++#define TOIE2 6
++#define OCIE2 7
++
++#define GIFR _SFR_IO8(0x3A)
++#define INTF0 6
++#define INTF1 7
++
++#define GICR _SFR_IO8(0x3B)
++#define IVCE 0
++#define IVSEL 1
++#define INT0 6
++#define INT1 7
++
++/* Reserved [0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Timer/Counter2 Compare Match */
++#define TIMER2_COMP_vect _VECTOR(3)
++#define TIMER2_COMP_vect_num 3
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(4)
++#define TIMER2_OVF_vect_num 4
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(5)
++#define TIMER1_CAPT_vect_num 5
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(6)
++#define TIMER1_COMPA_vect_num 6
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(7)
++#define TIMER1_COMPB_vect_num 7
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(8)
++#define TIMER1_OVF_vect_num 8
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(9)
++#define TIMER0_OVF_vect_num 9
++
++/* Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(10)
++#define SPI__STC_vect_num 10
++
++/* USART, Rx Complete */
++#define USART__RXC_vect _VECTOR(11)
++#define USART__RXC_vect_num 11
++
++/* USART Data Register Empty */
++#define USART__UDRE_vect _VECTOR(12)
++#define USART__UDRE_vect_num 12
++
++/* USART, Tx Complete */
++#define USART__TXC_vect _VECTOR(13)
++#define USART__TXC_vect_num 13
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(14)
++#define ADC_vect_num 14
++
++/* EEPROM Ready */
++#define EE_RDY_vect _VECTOR(15)
++#define EE_RDY_vect_num 15
++
++/* Analog Comparator */
++#define ANA_COMP_vect _VECTOR(16)
++#define ANA_COMP_vect_num 16
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(17)
++#define TWI_vect_num 17
++
++/* Store Program Memory Ready */
++#define SPM_RDY_vect _VECTOR(18)
++#define SPM_RDY_vect_num 18
++
++#define _VECTORS_SIZE 38
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0060
++#define RAMSIZE 1024
++#define RAMEND 0x045F
++#define E2START 0
++#define E2SIZE 512
++#define E2PAGESIZE 4
++#define E2END 0x01FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 2
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5)
++#define FUSE_BODEN (unsigned char)~_BV(6)
++#define FUSE_BODLEVEL (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_CKOPT (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_WTDON (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x07
++
++
++#endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iomxx4.h avr-libc-1.8.0/include/avr/iomxx4.h
+--- avr-libc-1.8.0.orig/include/avr/iomxx4.h 2011-12-29 09:51:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iomxx4.h 2013-01-18 09:50:25.000000000 +0100
+@@ -366,8 +366,8 @@
+
+ /* Reserved [0x62..0x63] */
+
+-#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D\96AVR\9602/07
+- and ATmega644 2593L\96AVR\9602/07. */
++#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D�AVR�02/07
++ and ATmega644 2593L�AVR�02/07. */
+ #define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */
+ #define PRTWI 7
+ #define PRTIM2 6
+diff -urN avr-libc-1.8.0.orig/include/avr/iotn1634.h avr-libc-1.8.0/include/avr/iotn1634.h
+--- avr-libc-1.8.0.orig/include/avr/iotn1634.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iotn1634.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,760 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATTINY1634_H_INCLUDED
++#define _AVR_ATTINY1634_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iotn1634.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_IO16(0x00)
++#endif
++#define ADCW _SFR_IO16(0x00)
++
++#define ADCL _SFR_IO8(0x00)
++#define ADCH _SFR_IO8(0x01)
++
++#define ADCSRB _SFR_IO8(0x02)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ADLAR 3
++
++#define ADCSRA _SFR_IO8(0x03)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADMUX _SFR_IO8(0x04)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define REFS0 6
++#define REFS1 7
++
++#define ACSRB _SFR_IO8(0x05)
++#define ACME 2
++#define HLEV 6
++#define HSEL 7
++
++#define ACSRA _SFR_IO8(0x06)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define PINC _SFR_IO8(0x07)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x08)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x09)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PUEC _SFR_IO8(0x0A)
++
++#define PINB _SFR_IO8(0x0B)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x0C)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x0D)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PUEB _SFR_IO8(0x0E)
++
++#define PINA _SFR_IO8(0x0F)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x10)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x11)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PUEA _SFR_IO8(0x12)
++
++#define PORTCR _SFR_IO8(0x13)
++#define BBMB 1
++#define BBMC 2
++#define BBMA 0
++
++/* Reserved [0x14] */
++
++#define GPIOR1 _SFR_IO8(0x15)
++
++#define GPIOR0 _SFR_IO8(0x15)
++
++#define GPIOR2 _SFR_IO8(0x16)
++
++#define OCR0B _SFR_IO8(0x17)
++
++#define OCR0A _SFR_IO8(0x18)
++
++#define TCNT0 _SFR_IO8(0x19)
++
++#define TCCR0B _SFR_IO8(0x1A)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCCR0A _SFR_IO8(0x1B)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define EECR _SFR_IO8(0x1C)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x1D)
++
++#define EEAR _SFR_IO8(0x1E)
++
++/* Reserved [0x1F] */
++
++#define UDR0 _SFR_IO8(0x20)
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_IO16(0x21)
++
++#define UBRR0L _SFR_IO8(0x21)
++#define UBRR0H _SFR_IO8(0x22)
++
++#define UCSR0D _SFR_IO8(0x23)
++#define SFDE0 5
++#define RXS0 6
++#define RXSIE0 7
++
++#define UCSR0C _SFR_IO8(0x24)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++
++#define UCSR0B _SFR_IO8(0x25)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0A _SFR_IO8(0x26)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define PCMSK0 _SFR_IO8(0x27)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_IO8(0x28)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 0
++#define PCINT13 1
++#define PCINT14 2
++#define PCINT15 3
++#define PCINT16 4
++#define PCINT17 5
++
++/* Reserved [0x29] */
++
++#define USICR _SFR_IO8(0x2A)
++#define USITC 0
++#define USICLK 1
++#define USICS0 2
++#define USICS1 3
++#define USIWM0 4
++#define USIWM1 5
++#define USIOIE 6
++#define USISIE 7
++
++#define USISR _SFR_IO8(0x2B)
++#define USICNT0 0
++#define USICNT1 1
++#define USICNT2 2
++#define USICNT3 3
++#define USIDC 4
++#define USIPF 5
++#define USIOIF 6
++#define USISIF 7
++
++#define USIDR _SFR_IO8(0x2C)
++
++#define USIBR _SFR_IO8(0x2D)
++
++/* Reserved [0x2E] */
++
++#define CCP _SFR_IO8(0x2F)
++
++#define WDTCSR _SFR_IO8(0x30)
++#define WDE 3
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++/* Reserved [0x31] */
++
++#define CLKSR _SFR_IO8(0x32)
++#define CKSEL0 0
++#define CKSEL1 1
++#define CKSEL2 2
++#define CKSEL3 3
++#define SUT 4
++#define CKOUT_IO 5
++#define CSTR 6
++#define OSCRDY 7
++
++#define CLKPR _SFR_IO8(0x33)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++
++#define PRR _SFR_IO8(0x34)
++#define PRADC 0
++#define PRUSART0 1
++#define PRUSART1 2
++#define PRUSI 3
++#define PRTIM0 4
++#define PRTIM1 5
++#define PRTWI 6
++
++#define MCUSR _SFR_IO8(0x35)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x36)
++#define ISC00 0
++#define ISC01 1
++#define SE 4
++#define SM0 5
++#define SM1 6
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define RFLB 3
++#define CTPB 4
++#define RSIG 5
++
++/* Reserved [0x38] */
++
++#define TIFR _SFR_IO8(0x39)
++#define ICF1 3
++#define OCF1B 5
++#define OCF1A 6
++#define TOV1 7
++#define OCF0A 0
++#define TOV0 1
++#define OCF0B 2
++
++#define TIMSK _SFR_IO8(0x3A)
++#define ICIE1 3
++#define OCIE1B 5
++#define OCIE1A 6
++#define TOIE1 7
++#define OCIE0A 0
++#define TOIE0 1
++#define OCIE0B 2
++
++#define GIFR _SFR_IO8(0x3B)
++#define PCIF0 3
++#define PCIF1 4
++#define PCIF2 5
++#define INTF0 6
++
++#define GIMSK _SFR_IO8(0x3C)
++#define PCIE0 3
++#define PCIE1 4
++#define PCIE2 5
++#define INT0 6
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define DIDR0 _SFR_MEM8(0x60)
++#define AREFD 0
++#define AIN0D 1
++#define AIN1D 2
++#define ADC0D 3
++#define ADC1D 4
++#define ADC2D 5
++#define ADC3D 6
++#define ADC4D 7
++
++#define DIDR1 _SFR_MEM8(0x61)
++#define ADC5D 0
++#define ADC6D 1
++#define ADC7D 2
++#define ADC8D 3
++
++#define DIDR2 _SFR_MEM8(0x62)
++#define ADC9D 0
++#define ADC10D 1
++#define ADC11D 2
++
++#define OSCCAL0 _SFR_MEM8(0x63)
++
++#define OSCTCAL0A _SFR_MEM8(0x64)
++
++#define OSCTCAL0B _SFR_MEM8(0x65)
++
++#define OSCCAL1 _SFR_MEM8(0x66)
++
++/* Reserved [0x67] */
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x68)
++
++#define ICR1L _SFR_MEM8(0x68)
++#define ICR1H _SFR_MEM8(0x69)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x6A)
++
++#define OCR1BL _SFR_MEM8(0x6A)
++#define OCR1BH _SFR_MEM8(0x6B)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x6C)
++
++#define OCR1AL _SFR_MEM8(0x6C)
++#define OCR1AH _SFR_MEM8(0x6D)
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x6E)
++
++#define TCNT1L _SFR_MEM8(0x6E)
++#define TCNT1H _SFR_MEM8(0x6F)
++
++#define TCCR1C _SFR_MEM8(0x70)
++#define FOC1B 6
++#define FOC1A 7
++
++#define TCCR1B _SFR_MEM8(0x71)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1A _SFR_MEM8(0x72)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define UDR1 _SFR_MEM8(0x73)
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0x74)
++
++#define UBRR1L _SFR_MEM8(0x74)
++#define UBRR1H _SFR_MEM8(0x75)
++
++#define UCSR1D _SFR_MEM8(0x76)
++#define SFDE1 5
++#define RXS1 6
++#define RXSIE1 7
++
++#define UCSR1C _SFR_MEM8(0x77)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++
++#define UCSR1B _SFR_MEM8(0x78)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1A _SFR_MEM8(0x79)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define TWSD _SFR_MEM8(0x7A)
++#define TWSD0 0
++#define TWSD1 1
++#define TWSD2 2
++#define TWSD3 3
++#define TWSD4 4
++#define TWSD5 5
++#define TWSD6 6
++#define TWSD7 7
++
++#define TWSAM _SFR_MEM8(0x7B)
++
++#define TWSA _SFR_MEM8(0x7C)
++#define TWSA0 0
++#define TWSA1 1
++#define TWSA2 2
++#define TWSA3 3
++#define TWSA4 4
++#define TWSA5 5
++#define TWSA6 6
++#define TWSA7 7
++
++#define TWSSRA _SFR_MEM8(0x7D)
++
++#define TWSCRB _SFR_MEM8(0x7E)
++#define TWCMD0 0
++#define TWCMD1 1
++#define TWAA 2
++
++#define TWSCRA _SFR_MEM8(0x7F)
++#define TWSME 0
++#define TWPME 1
++#define TWSIE 2
++#define TWEN 3
++#define TWASIE 4
++#define TWDIE 5
++#define TWSHE 7
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(2)
++#define PCINT0_vect_num 2
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(3)
++#define PCINT1_vect_num 3
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(4)
++#define PCINT2_vect_num 4
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(5)
++#define WDT_vect_num 5
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(6)
++#define TIMER1_CAPT_vect_num 6
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(7)
++#define TIMER1_COMPA_vect_num 7
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(8)
++#define TIMER1_COMPB_vect_num 8
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(9)
++#define TIMER1_OVF_vect_num 9
++
++/* TimerCounter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(10)
++#define TIMER0_COMPA_vect_num 10
++
++/* TimerCounter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(11)
++#define TIMER0_COMPB_vect_num 11
++
++/* Timer/Couner0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(12)
++#define TIMER0_OVF_vect_num 12
++
++/* Analog Comparator */
++#define ANA_COMP_vect _VECTOR(13)
++#define ANA_COMP_vect_num 13
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(14)
++#define ADC_vect_num 14
++
++/* USART0, Start */
++#define USART0__START_vect _VECTOR(15)
++#define USART0__START_vect_num 15
++
++/* USART0, Rx Complete */
++#define USART0__RX_vect _VECTOR(16)
++#define USART0__RX_vect_num 16
++
++/* USART0 Data Register Empty */
++#define USART0__UDRE_vect _VECTOR(17)
++#define USART0__UDRE_vect_num 17
++
++/* USART0, Tx Complete */
++#define USART0__TX_vect _VECTOR(18)
++#define USART0__TX_vect_num 18
++
++/* USART1, Start */
++#define USART1__START_vect _VECTOR(19)
++#define USART1__START_vect_num 19
++
++/* USART1, Rx Complete */
++#define USART1__RX_vect _VECTOR(20)
++#define USART1__RX_vect_num 20
++
++/* USART1 Data Register Empty */
++#define USART1__UDRE_vect _VECTOR(21)
++#define USART1__UDRE_vect_num 21
++
++/* USART1, Tx Complete */
++#define USART1__TX_vect _VECTOR(22)
++#define USART1__TX_vect_num 22
++
++/* USI Start Condition */
++#define USI_START_vect _VECTOR(23)
++#define USI_START_vect_num 23
++
++/* USI Overflow */
++#define USI_OVERFLOW_vect _VECTOR(24)
++#define USI_OVERFLOW_vect_num 24
++
++/* Two-wire Serial Interface */
++#define TWI_SLAVE_vect _VECTOR(25)
++#define TWI_SLAVE_vect_num 25
++
++/* EEPROM Ready */
++#define EE_RDY_vect _VECTOR(26)
++#define EE_RDY_vect_num 26
++
++/* Touch Sensing */
++#define QTRIP_vect _VECTOR(27)
++#define QTRIP_vect_num 27
++
++#define _VECTORS_SIZE 112
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 32
++#define FLASHEND 0x3FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 1024
++#define RAMEND 0x04FF
++#define E2START 0
++#define E2SIZE 256
++#define E2PAGESIZE 4
++#define E2END 0x00FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2)
++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3)
++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
++#define FUSE_BODACT0 (unsigned char)~_BV(1)
++#define FUSE_BODACT1 (unsigned char)~_BV(2)
++#define FUSE_BODPD0 (unsigned char)~_BV(3)
++#define FUSE_BODPD1 (unsigned char)~_BV(4)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x12
++
++
++#endif /* #ifdef _AVR_ATTINY1634_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iotn828.h avr-libc-1.8.0/include/avr/iotn828.h
+--- avr-libc-1.8.0.orig/include/avr/iotn828.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iotn828.h 2013-01-18 09:50:25.000000000 +0100
+@@ -0,0 +1,843 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATTINY828_H_INCLUDED
++#define _AVR_ATTINY828_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iotn828.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PUEA _SFR_IO8(0x03)
++
++#define PINB _SFR_IO8(0x04)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x05)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x06)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PUEB _SFR_IO8(0x07)
++
++#define PINC _SFR_IO8(0x08)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x09)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x0A)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PUEC _SFR_IO8(0x0B)
++
++#define PIND _SFR_IO8(0x0C)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0D)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0E)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PUED _SFR_IO8(0x0F)
++
++/* Reserved [0x10..0x13] */
++
++#define PHDE _SFR_IO8(0x14)
++#define PHDEC 2
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define ICF1 5
++
++/* Reserved [0x17..0x1A] */
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++#define PCIF3 3
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++
++#define GPIOR0 _SFR_IO8(0x1E)
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++#define EEAR _SFR_IO8(0x21)
++
++/* Reserved [0x22] */
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define TSM 7
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++
++#define GPIOR2 _SFR_IO8(0x2B)
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++#define ACSRB _SFR_IO8(0x2F)
++#define ACPMUX0 0
++#define ACPMUX1 1
++#define ACNMUX0 2
++#define ACNMUX1 3
++#define HLEV 6
++#define HSEL 7
++
++#define ACSRA _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACPMUX2 6
++#define ACD 7
++
++/* Reserved [0x31..0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++
++#define MCUSR _SFR_IO8(0x34)
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define IVSEL 1
++
++#define CCP _SFR_IO8(0x36)
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define RWFLB 3
++#define RWWSRE 4
++#define RSIG 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++
++/* Reserved [0x62..0x63] */
++
++#define PRR _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRTIM0 5
++#define PRTWI 7
++
++/* Reserved [0x65] */
++
++#define OSCCAL0 _SFR_MEM8(0x66)
++
++#define OSCCAL1 _SFR_MEM8(0x67)
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++#define PCIE3 3
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++
++/* Reserved [0x6A] */
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++#define PCINT0 0
++#define PCINT1 1
++#define PCINT2 2
++#define PCINT3 3
++#define PCINT4 4
++#define PCINT5 5
++#define PCINT6 6
++#define PCINT7 7
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define ICIE1 5
++
++/* Reserved [0x70..0x72] */
++
++#define PCMSK3 _SFR_MEM8(0x73)
++#define PCINT24 0
++#define PCINT25 1
++#define PCINT26 2
++#define PCINT27 3
++
++/* Reserved [0x74..0x77] */
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define ADLAR 3
++
++#define ADMUXA _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++
++#define ADMUXB _SFR_MEM8(0x7D)
++#define MUX5 0
++#define REFS 5
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++#define ADC11D 3
++#define ADC12D 4
++#define ADC13D 5
++#define ADC14D 6
++#define ADC15D 7
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Reserved [0x8C..0xB7] */
++
++#define TWSCRA _SFR_MEM8(0xB8)
++#define TWSME 0
++#define TWPME 1
++#define TWSIE 2
++#define TWEN 3
++#define TWASIE 4
++#define TWDIE 5
++#define TWSHE 7
++
++#define TWSCRB _SFR_MEM8(0xB9)
++#define TWCMD0 0
++#define TWCMD1 1
++#define TWAA 2
++#define TWHNM 3
++
++#define TWSSRA _SFR_MEM8(0xBA)
++#define TWAS 0
++#define TWDIR 1
++#define TWBE 2
++#define TWC 3
++#define TWRA 4
++#define TWCH 5
++#define TWASIF 6
++#define TWDIF 7
++
++#define TWSAM _SFR_MEM8(0xBB)
++#define TWAE 0
++#define TWSAM1 1
++#define TWSAM2 2
++#define TWSAM3 3
++#define TWSAM4 4
++#define TWSAM5 5
++#define TWSAM6 6
++#define TWSAM7 7
++
++#define TWSA _SFR_MEM8(0xBC)
++
++#define TWSD _SFR_MEM8(0xBD)
++#define TWSD0 0
++#define TWSD1 1
++#define TWSD2 2
++#define TWSD3 3
++#define TWSD4 4
++#define TWSD5 5
++#define TWSD6 6
++#define TWSD7 7
++
++/* Reserved [0xBE..0xBF] */
++
++#define UCSRA _SFR_MEM8(0xC0)
++#define MPCM 0
++#define U2X 1
++#define UPE 2
++#define DOR 3
++#define FE 4
++#define UDRE 5
++#define TXC 6
++#define RXC 7
++
++#define UCSRB _SFR_MEM8(0xC1)
++#define TXB8 0
++#define RXB8 1
++#define UCSZ2 2
++#define TXEN 3
++#define RXEN 4
++#define UDRIE 5
++#define TXCIE 6
++#define RXCIE 7
++
++#define UCSRC _SFR_MEM8(0xC2)
++#define UCPOL 0
++#define UCSZ0 1
++#define UCSZ1 2
++#define USBS 3
++#define UPM0 4
++#define UPM1 5
++#define UMSEL0 6
++#define UMSEL1 7
++
++#define UCSRD _SFR_MEM8(0xC3)
++#define SFDE 5
++#define RXS 6
++#define RXSIE 7
++
++/* Combine UBRRL and UBRRH */
++#define UBRR _SFR_MEM16(0xC4)
++
++#define UBRRL _SFR_MEM8(0xC4)
++#define UBRRH _SFR_MEM8(0xC5)
++
++#define UDR _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7..0xDD] */
++
++#define DIDR2 _SFR_MEM8(0xDE)
++#define ADC16D 0
++#define ADC17D 1
++#define ADC18D 2
++#define ADC19D 3
++#define ADC20D 4
++#define ADC21D 5
++#define ADC22D 6
++#define ADC23D 7
++
++#define DIDR3 _SFR_MEM8(0xDF)
++#define ADC24D 0
++#define ADC25D 1
++#define ADC26D 2
++#define ADC27D 3
++
++/* Reserved [0xE0..0xE1] */
++
++#define TOCPMCOE _SFR_MEM8(0xE2)
++#define TOCC0OE 0
++#define TOCC1OE 1
++#define TOCC2OE 2
++#define TOCC3OE 3
++#define TOCC4OE 4
++#define TOCC5OE 5
++#define TOCC6OE 6
++#define TOCC7OE 7
++
++/* Reserved [0xE3..0xE7] */
++
++#define TOCPMSA0 _SFR_MEM8(0xE8)
++#define TOCC0S0 0
++#define TOCC0S1 1
++#define TOCC1S0 2
++#define TOCC1S1 3
++#define TOCC2S0 4
++#define TOCC2S1 5
++#define TOCC3S0 6
++#define TOCC3S1 7
++
++#define TOCPMSA1 _SFR_MEM8(0xE9)
++#define TOCC4S0 0
++#define TOCC4S1 1
++#define TOCC5S0 2
++#define TOCC5S1 3
++#define TOCC6S0 4
++#define TOCC6S1 5
++#define TOCC7S0 6
++#define TOCC7S1 7
++
++/* Reserved [0xEA..0xEF] */
++
++#define OSCTCAL0A _SFR_MEM8(0xF0)
++
++#define OSCTCAL0B _SFR_MEM8(0xF1)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(3)
++#define PCINT0_vect_num 3
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(4)
++#define PCINT1_vect_num 4
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(5)
++#define PCINT2_vect_num 5
++
++/* Pin Change Interrupt Request 3 */
++#define PCINT3_vect _VECTOR(6)
++#define PCINT3_vect_num 6
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(7)
++#define WDT_vect_num 7
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(8)
++#define TIMER1_CAPT_vect_num 8
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(9)
++#define TIMER1_COMPA_vect_num 9
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(10)
++#define TIMER1_COMPB_vect_num 10
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(11)
++#define TIMER1_OVF_vect_num 11
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(12)
++#define TIMER0_COMPA_vect_num 12
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(13)
++#define TIMER0_COMPB_vect_num 13
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(14)
++#define TIMER0_OVF_vect_num 14
++
++/* SPI Serial Transfer Complete */
++#define SPI__STC_vect _VECTOR(15)
++#define SPI__STC_vect_num 15
++
++/* USART, Start */
++#define USART__START_vect _VECTOR(16)
++#define USART__START_vect_num 16
++
++/* USART Rx Complete */
++#define USART__RX_vect _VECTOR(17)
++#define USART__RX_vect_num 17
++
++/* USART, Data Register Empty */
++#define USART__UDRE_vect _VECTOR(18)
++#define USART__UDRE_vect_num 18
++
++/* USART Tx Complete */
++#define USART__TX_vect _VECTOR(19)
++#define USART__TX_vect_num 19
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(20)
++#define ADC_vect_num 20
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(21)
++#define EE_READY_vect_num 21
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(22)
++#define ANALOG_COMP_vect_num 22
++
++/* Two-wire Serial Interface */
++#define TWI_SLAVE_vect _VECTOR(23)
++#define TWI_SLAVE_vect_num 23
++
++/* Store Program Memory Read */
++#define SPM_Ready_vect _VECTOR(24)
++#define SPM_Ready_vect_num 24
++
++/* Touch Sensing */
++#define QTRIP_vect _VECTOR(25)
++#define QTRIP_vect_num 25
++
++#define _VECTORS_SIZE 52
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 64
++#define FLASHEND 0x1FFF
++#define RAMSTART 0x0100
++#define RAMSIZE 512
++#define RAMEND 0x02FF
++#define E2START 0
++#define E2SIZE 256
++#define E2PAGESIZE 4
++#define E2END 0x00FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0)
++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_DWEN (unsigned char)~_BV(6)
++#define FUSE_RSTDISBL (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_BODACT0 (unsigned char)~_BV(4)
++#define FUSE_BODACT1 (unsigned char)~_BV(5)
++#define FUSE_BODPD0 (unsigned char)~_BV(6)
++#define FUSE_BODPD1 (unsigned char)~_BV(7)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x14
++
++
++#endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128a1u.h avr-libc-1.8.0/include/avr/iox128a1u.h
+--- avr-libc-1.8.0.orig/include/avr/iox128a1u.h 2011-12-29 09:51:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128a1u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -1,38 +1,36 @@
+-/* Copyright (c) 2010 Atmel Corporation
+- All rights reserved.
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
+
+- Redistribution and use in source and binary forms, with or without
+- modification, are permitted provided that the following conditions are met:
+-
+- * Redistributions of source code must retain the above copyright
+- notice, this list of conditions and the following disclaimer.
+-
+- * Redistributions in binary form must reproduce the above copyright
+- notice, this list of conditions and the following disclaimer in
+- the documentation and/or other materials provided with the
+- distribution.
+-
+- * Neither the name of the copyright holders nor the names of
+- contributors may be used to endorse or promote products derived
+- from this software without specific prior written permission.
+-
+- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- POSSIBILITY OF SUCH DAMAGE. */
+-
+-/* $Id: iox128a1u.h 2162 2010-06-11 17:26:12Z arcanum $ */
+-
+-/* avr/iox128a1u.h - definitions for ATxmega128A1U */
+-
+-/* This file should only be included from <avr/io.h>, never directly. */
+
+ #ifndef _AVR_IO_H_
+ # error "Include <avr/io.h> instead of this file."
+@@ -42,12 +40,10 @@
+ # define _AVR_IOXXX_H_ "iox128a1u.h"
+ #else
+ # error "Attempt to include more than one <avr/ioXXX.h> file."
+-#endif
+-
+-
+-#ifndef _AVR_ATxmega128A1U_H_
+-#define _AVR_ATxmega128A1U_H_ 1
++#endif
+
++#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED
++#define _AVR_ATXMEGA128A1U_H_INCLUDED
+
+ /* Ungrouped common registers */
+ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+@@ -67,6 +63,24 @@
+ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
+ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+@@ -77,7 +91,6 @@
+ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+ #define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+-
+ /* C Language Only */
+ #if !defined (__ASSEMBLER__)
+
+@@ -156,6 +169,12 @@
+ } OCD_t;
+
+
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
+ /* CCP signatures */
+ typedef enum CCP_enum
+ {
+@@ -180,11 +199,6 @@
+ register8_t USBCTRL; /* USB Control Register */
+ } CLK_t;
+
+-/*
+---------------------------------------------------------------------------
+-CLK - Clock System
+---------------------------------------------------------------------------
+-*/
+
+ /* Power Reduction */
+ typedef struct PR_struct
+@@ -258,6 +272,7 @@
+ typedef enum CLK_USBSRC_enum
+ {
+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
+ } CLK_USBSRC_t;
+
+
+@@ -298,7 +313,7 @@
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
+- register8_t PLLCTRL; /* PLL Control REgister */
++ register8_t PLLCTRL; /* PLL Control Register */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+ } OSC_t;
+
+@@ -329,11 +344,19 @@
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+ } OSC_PLLSRC_t;
+
+-/* 32 MHz Calibration Reference */
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
+ typedef enum OSC_RC32MCREF_enum
+ {
+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
+- OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
+ } OSC_RC32MCREF_t;
+
+
+@@ -471,6 +494,8 @@
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
+ } PORTCFG_t;
+
+ /* Virtual Port Mapping */
+@@ -541,6 +566,26 @@
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+ } PORTCFG_EVOUT_t;
+
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
+
+ /*
+ --------------------------------------------------------------------------
+@@ -577,16 +622,17 @@
+ /* Cyclic Redundancy Checker */
+ typedef struct CRC_struct
+ {
+- register8_t CTRL; /* CRC Control Register */
+- register8_t STATUS; /* CRC Status Register */
+- register8_t DATAIN; /* CRC Data Input */
+- register8_t CHECKSUM0; /* CRC Checksum byte 0 */
+- register8_t CHECKSUM1; /* CRC Checksum byte 1 */
+- register8_t CHECKSUM2; /* CRC Checksum byte 2 */
+- register8_t CHECKSUM3; /* CRC Checksum byte 3 */
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
+ } CRC_t;
+
+-/* CRC Reset */
++/* Reset */
+ typedef enum CRC_RESET_enum
+ {
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+@@ -594,10 +640,10 @@
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+ } CRC_RESET_t;
+
+-/* CRC Input Source */
++/* Input Source */
+ typedef enum CRC_SOURCE_enum
+ {
+- CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+@@ -633,11 +679,6 @@
+ register8_t reserved_0x0F;
+ } DMA_CH_t;
+
+-/*
+---------------------------------------------------------------------------
+-DMA - DMA Controller
+---------------------------------------------------------------------------
+-*/
+
+ /* DMA Controller */
+ typedef struct DMA_struct
+@@ -1037,8 +1078,8 @@
+ typedef enum NVM_CMD_enum
+ {
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+- NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+@@ -1062,13 +1103,14 @@
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
+- NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
+ } NVM_CMD_t;
+
+ /* SPM ready interrupt level */
+@@ -1092,36 +1134,36 @@
+ /* Boot lock bits - boot setcion */
+ typedef enum NVM_BLBB_enum
+ {
+- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ } NVM_BLBB_t;
+
+ /* Boot lock bits - application section */
+ typedef enum NVM_BLBA_enum
+ {
+- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ } NVM_BLBA_t;
+
+ /* Boot lock bits - application table section */
+ typedef enum NVM_BLBAT_enum
+ {
+- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ } NVM_BLBAT_t;
+
+ /* Lock bits */
+ typedef enum NVM_LB_enum
+ {
+- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ } NVM_LB_t;
+
+
+@@ -1136,17 +1178,13 @@
+ {
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+- register8_t INTCTRL; /* Channel Interrupt Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+- register8_t reserved_0x7;
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
+ } ADC_CH_t;
+
+-/*
+---------------------------------------------------------------------------
+-ADC - Analog/Digital Converter
+---------------------------------------------------------------------------
+-*/
+
+ /* Analog-to-Digital Converter */
+ typedef struct ADC_struct
+@@ -1158,7 +1196,7 @@
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t reserved_0x05;
+ register8_t INTFLAGS; /* Interrupt Flags */
+- register8_t TEMP; /* Temporary register */
++ register8_t TEMP; /* Temporary Register */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+@@ -1245,7 +1283,7 @@
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+- ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
+ } ADC_CH_GAIN_t;
+
+ /* Conversion result resolution */
+@@ -1257,13 +1295,13 @@
+ } ADC_RESOLUTION_t;
+
+ /* Current Limitation Mode */
+-typedef enum ADC_CURRENT_enum
++typedef enum ADC_CURRLIMIT_enum
+ {
+- ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */
+- ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */
+- ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
+- ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */
+-} ADC_CURRENT_t;
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
+
+ /* Voltage reference selection */
+ typedef enum ADC_REFSEL_enum
+@@ -1440,7 +1478,7 @@
+ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
+ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
+ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
+- DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
+ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
+ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
+ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
+@@ -1548,7 +1586,7 @@
+
+ /*
+ --------------------------------------------------------------------------
+-RTC - Real-Time Clounter
++RTC - Real-Time Counter
+ --------------------------------------------------------------------------
+ */
+
+@@ -1614,11 +1652,6 @@
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+ } EBI_CS_t;
+
+-/*
+---------------------------------------------------------------------------
+-EBI - External Bus Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* External Bus Interface */
+ typedef struct EBI_struct
+@@ -1644,28 +1677,28 @@
+ } EBI_t;
+
+ /* Chip Select adress space */
+-typedef enum EBI_CS_ASIZE_enum
++typedef enum EBI_CS_ASPACE_enum
+ {
+- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */
+- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */
+- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */
+- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */
+- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */
+- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */
+- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */
+- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */
+- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */
+- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */
+- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */
+- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */
+- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */
+- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */
+- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */
+- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */
+- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */
+-} EBI_CS_ASIZE_t;
++ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
++ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
++ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
++ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
++ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
++ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
++ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
++ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
++ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
++ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
++ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
++ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
++ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
++ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
++ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
++ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
++ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
++} EBI_CS_ASPACE_t;
+
+-/* */
++/* SRAM Wait State Selection */
+ typedef enum EBI_CS_SRWS_enum
+ {
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1673,7 +1706,7 @@
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_CS_SRWS_t;
+@@ -1735,7 +1768,7 @@
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+ } EBI_SDCOL_t;
+
+-/* */
++/* SDRAM Load Mode to Active delay */
+ typedef enum EBI_MRDLY_enum
+ {
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+@@ -1744,7 +1777,7 @@
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+ } EBI_MRDLY_t;
+
+-/* */
++/* SDRAM Row Cycle Delay */
+ typedef enum EBI_ROWCYCDLY_enum
+ {
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+@@ -1752,12 +1785,12 @@
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+ } EBI_ROWCYCDLY_t;
+
+-/* */
++/* SDRAM Row to Precharge Delay */
+ typedef enum EBI_RPDLY_enum
+ {
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1765,12 +1798,12 @@
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_RPDLY_t;
+
+-/* */
++/* SDRAM Write Recovery Delay */
+ typedef enum EBI_WRDLY_enum
+ {
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+@@ -1779,7 +1812,7 @@
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+ } EBI_WRDLY_t;
+
+-/* */
++/* SDRAM Exit Self Refresh to Active Delay */
+ typedef enum EBI_ESRDLY_enum
+ {
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+@@ -1787,12 +1820,12 @@
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+ } EBI_ESRDLY_t;
+
+-/* */
++/* SDRAM Row to Column Delay */
+ typedef enum EBI_ROWCOLDLY_enum
+ {
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1800,7 +1833,7 @@
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_ROWCOLDLY_t;
+@@ -1824,11 +1857,6 @@
+ register8_t DATA; /* Data Register */
+ } TWI_MASTER_t;
+
+-/*
+---------------------------------------------------------------------------
+-TWI - Two-Wire Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* */
+ typedef struct TWI_SLAVE_struct
+@@ -1841,11 +1869,6 @@
+ register8_t ADDRMASK; /* Address Mask Register */
+ } TWI_SLAVE_t;
+
+-/*
+---------------------------------------------------------------------------
+-TWI - Two-Wire Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* Two-Wire Interface */
+ typedef struct TWI_struct
+@@ -1911,7 +1934,7 @@
+
+ /*
+ --------------------------------------------------------------------------
+-USB - USB Module
++USB - USB
+ --------------------------------------------------------------------------
+ */
+
+@@ -1920,66 +1943,13 @@
+ {
+ register8_t STATUS; /* Endpoint Status */
+ register8_t CTRL; /* Endpoint Control */
+- register8_t CNTL; /* USB Endpoint Counter Low Byte */
+- register8_t CNTH; /* USB Endpoint Counter High Byte */
+- register8_t DATAPTRL; /* Data Pointer Low Byte */
+- register8_t DATAPTRH; /* Data Pointer High Byte */
+- register8_t AUXDATAL; /* Auxiliary Data Low Byte */
+- register8_t AUXDATAH; /* Auxiliary Data High Byte */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
+ } USB_EP_t;
+
+-/*
+---------------------------------------------------------------------------
+-USB - USB Module
+---------------------------------------------------------------------------
+-*/
+-
+-/* USB Endpoint table */
+-typedef struct USB_EP_TABLE_struct
+-{
+- USB_EP_t EP0OUT; /* USB Endpoint 0 Output */
+- USB_EP_t EP0IN; /* USB Endpoint 0 Input */
+- USB_EP_t EP1OUT; /* USB Endpoint 1 Output */
+- USB_EP_t EP1IN; /* USB Endpoint 1 Input */
+- USB_EP_t EP2OUT; /* USB Endpoint 2 Output */
+- USB_EP_t EP2IN; /* USB Endpoint 2 Input */
+- USB_EP_t EP3OUT; /* USB Endpoint 3 Output */
+- USB_EP_t EP3IN; /* USB Endpoint 3 Input */
+- USB_EP_t EP4OUT; /* USB Endpoint 4 Output */
+- USB_EP_t EP4IN; /* USB Endpoint 4 Input */
+- USB_EP_t EP5OUT; /* USB Endpoint 5 Output */
+- USB_EP_t EP5IN; /* USB Endpoint 5 Input */
+- USB_EP_t EP6OUT; /* USB Endpoint 6 Output */
+- USB_EP_t EP6IN; /* USB Endpoint 6 Input */
+- USB_EP_t EP7OUT; /* USB Endpoint 7 Output */
+- USB_EP_t EP7IN; /* USB Endpoint 7 Input */
+- USB_EP_t EP8OUT; /* USB Endpoint 8 Output */
+- USB_EP_t EP8IN; /* USB Endpoint 8 Input */
+- USB_EP_t EP9OUT; /* USB Endpoint 9 Output */
+- USB_EP_t EP9IN; /* USB Endpoint 9 Input */
+- USB_EP_t EP10OUT; /* USB Endpoint 10 Output */
+- USB_EP_t EP10IN; /* USB Endpoint 10 Input */
+- USB_EP_t EP11OUT; /* USB Endpoint 11 Output */
+- USB_EP_t EP11IN; /* USB Endpoint 11 Input */
+- USB_EP_t EP12OUT; /* USB Endpoint 12 Output */
+- USB_EP_t EP12IN; /* USB Endpoint 12 Input */
+- USB_EP_t EP13OUT; /* USB Endpoint 13 Output */
+- USB_EP_t EP13IN; /* USB Endpoint 13 Input */
+- USB_EP_t EP14OUT; /* USB Endpoint 14 Output */
+- USB_EP_t EP14IN; /* USB Endpoint 14 Input */
+- USB_EP_t EP15OUT; /* USB Endpoint 15 Output */
+- USB_EP_t EP15IN; /* USB Endpoint 15 Input */
+- register8_t FRAMENUML; /* Frame Number Low Byte */
+- register8_t FRAMENUMH; /* Frame Number High Byte */
+-} USB_EP_TABLE_t;
+-
+-/*
+---------------------------------------------------------------------------
+-USB - USB Module
+---------------------------------------------------------------------------
+-*/
+
+-/* USB Module */
++/* Universal Serial Bus */
+ typedef struct USB_struct
+ {
+ register8_t CTRLA; /* Control Register A */
+@@ -2043,6 +2013,71 @@
+ register8_t CAL1; /* Calibration Byte 1 */
+ } USB_t;
+
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
+ /* USB Endpoint Type */
+ typedef enum USB_EP_TYPE_enum
+ {
+@@ -2052,27 +2087,18 @@
+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
+ } USB_EP_TYPE_t;
+
+-/* USB Endpoint Buffer Size */
+-typedef enum USB_EP_SIZE_enum
+-{
+- USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
+- USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
+- USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
+- USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
+- USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
+- USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
+- USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
+- USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
+-} USB_EP_SIZE_t;
+-
+-/* Interrupt level */
+-typedef enum USB_INTLVL_enum
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
+ {
+- USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+- USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+- USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+- USB_INTLVL_HI_gc = (0x03<<0), /* High Level */
+-} USB_INTLVL_t;
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
+
+
+ /*
+@@ -2098,6 +2124,7 @@
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+@@ -2215,11 +2242,6 @@
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+ } TC0_t;
+
+-/*
+---------------------------------------------------------------------------
+-TC - 16-bit Timer/Counter With PWM
+---------------------------------------------------------------------------
+-*/
+
+ /* 16-bit Timer/Counter 1 */
+ typedef struct TC1_struct
+@@ -2305,12 +2327,24 @@
+ {
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+ } TC_WGMODE_t;
+
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
+ /* Event Action */
+ typedef enum TC_EVACT_enum
+ {
+@@ -2403,6 +2437,165 @@
+
+ /*
+ --------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
+ AWEX - Timer/Counter Advanced Waveform Extension
+ --------------------------------------------------------------------------
+ */
+@@ -2415,7 +2608,7 @@
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+- register8_t reserved_0x05;
++ register8_t STATUSSET; /* Status Set Register */
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+@@ -2604,17 +2797,235 @@
+
+ /*
+ --------------------------------------------------------------------------
+-PRESC - Prescaler
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
+ --------------------------------------------------------------------------
+ */
+
+-/* Prescaler */
+-typedef struct PRESC_struct
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
+ {
+- register8_t PRESCALER; /* Control Register */
+-} PRESC_t;
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
+
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
+
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
+
+ /*
+ ==========================================================================
+@@ -2622,79 +3033,82 @@
+ ==========================================================================
+ */
+
+-#define USB_EP_TABLE (*(USB_EP_TABLE_t *) ) /* Universal Serial Bus Module */
+-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
+ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+ #define CLK (*(CLK_t *) 0x0040) /* Clock System */
+ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
+ #define PR (*(PR_t *) 0x0070) /* Power Reduction */
+-#define RST (*(RST_t *) 0x0078) /* Reset Controller */
++#define RST (*(RST_t *) 0x0078) /* Reset */
+ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
+-#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
+ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
+ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
+-#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */
+-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
+-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
+ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */
+-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+-#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */
+-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
+-#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */
+-#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */
+-#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+-#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+-#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+-#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+-#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+-#define PORTH (*(PORT_t *) 0x06E0) /* Port H */
+-#define PORTJ (*(PORT_t *) 0x0700) /* Port J */
+-#define PORTK (*(PORT_t *) 0x0720) /* Port K */
+-#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */
+-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
+-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */
++#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */
++#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */
++#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
+ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
+-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
+-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
+-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
+-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
+-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
+-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+-#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */
+-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
+-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
+-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
+-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */
+
+
+ #endif /* !defined (__ASSEMBLER__) */
+@@ -2702,266 +3116,6 @@
+
+ /* ========== Flattened fully qualified IO register names ========== */
+
+-/* USB_EP_TABLE - Universal Serial Bus Module */
+-#define USB_EP_TABLE_EP0OUT_STATUS _SFR_MEM8(0x0000)
+-#define USB_EP_TABLE_EP0OUT_CTRL _SFR_MEM8(0x0001)
+-#define USB_EP_TABLE_EP0OUT_CNTL _SFR_MEM8(0x0002)
+-#define USB_EP_TABLE_EP0OUT_CNTH _SFR_MEM8(0x0003)
+-#define USB_EP_TABLE_EP0OUT_DATAPTRL _SFR_MEM8(0x0004)
+-#define USB_EP_TABLE_EP0OUT_DATAPTRH _SFR_MEM8(0x0005)
+-#define USB_EP_TABLE_EP0OUT_AUXDATAL _SFR_MEM8(0x0006)
+-#define USB_EP_TABLE_EP0OUT_AUXDATAH _SFR_MEM8(0x0007)
+-#define USB_EP_TABLE_EP0IN_STATUS _SFR_MEM8(0x0008)
+-#define USB_EP_TABLE_EP0IN_CTRL _SFR_MEM8(0x0009)
+-#define USB_EP_TABLE_EP0IN_CNTL _SFR_MEM8(0x000A)
+-#define USB_EP_TABLE_EP0IN_CNTH _SFR_MEM8(0x000B)
+-#define USB_EP_TABLE_EP0IN_DATAPTRL _SFR_MEM8(0x000C)
+-#define USB_EP_TABLE_EP0IN_DATAPTRH _SFR_MEM8(0x000D)
+-#define USB_EP_TABLE_EP0IN_AUXDATAL _SFR_MEM8(0x000E)
+-#define USB_EP_TABLE_EP0IN_AUXDATAH _SFR_MEM8(0x000F)
+-#define USB_EP_TABLE_EP1OUT_STATUS _SFR_MEM8(0x0010)
+-#define USB_EP_TABLE_EP1OUT_CTRL _SFR_MEM8(0x0011)
+-#define USB_EP_TABLE_EP1OUT_CNTL _SFR_MEM8(0x0012)
+-#define USB_EP_TABLE_EP1OUT_CNTH _SFR_MEM8(0x0013)
+-#define USB_EP_TABLE_EP1OUT_DATAPTRL _SFR_MEM8(0x0014)
+-#define USB_EP_TABLE_EP1OUT_DATAPTRH _SFR_MEM8(0x0015)
+-#define USB_EP_TABLE_EP1OUT_AUXDATAL _SFR_MEM8(0x0016)
+-#define USB_EP_TABLE_EP1OUT_AUXDATAH _SFR_MEM8(0x0017)
+-#define USB_EP_TABLE_EP1IN_STATUS _SFR_MEM8(0x0018)
+-#define USB_EP_TABLE_EP1IN_CTRL _SFR_MEM8(0x0019)
+-#define USB_EP_TABLE_EP1IN_CNTL _SFR_MEM8(0x001A)
+-#define USB_EP_TABLE_EP1IN_CNTH _SFR_MEM8(0x001B)
+-#define USB_EP_TABLE_EP1IN_DATAPTRL _SFR_MEM8(0x001C)
+-#define USB_EP_TABLE_EP1IN_DATAPTRH _SFR_MEM8(0x001D)
+-#define USB_EP_TABLE_EP1IN_AUXDATAL _SFR_MEM8(0x001E)
+-#define USB_EP_TABLE_EP1IN_AUXDATAH _SFR_MEM8(0x001F)
+-#define USB_EP_TABLE_EP2OUT_STATUS _SFR_MEM8(0x0020)
+-#define USB_EP_TABLE_EP2OUT_CTRL _SFR_MEM8(0x0021)
+-#define USB_EP_TABLE_EP2OUT_CNTL _SFR_MEM8(0x0022)
+-#define USB_EP_TABLE_EP2OUT_CNTH _SFR_MEM8(0x0023)
+-#define USB_EP_TABLE_EP2OUT_DATAPTRL _SFR_MEM8(0x0024)
+-#define USB_EP_TABLE_EP2OUT_DATAPTRH _SFR_MEM8(0x0025)
+-#define USB_EP_TABLE_EP2OUT_AUXDATAL _SFR_MEM8(0x0026)
+-#define USB_EP_TABLE_EP2OUT_AUXDATAH _SFR_MEM8(0x0027)
+-#define USB_EP_TABLE_EP2IN_STATUS _SFR_MEM8(0x0028)
+-#define USB_EP_TABLE_EP2IN_CTRL _SFR_MEM8(0x0029)
+-#define USB_EP_TABLE_EP2IN_CNTL _SFR_MEM8(0x002A)
+-#define USB_EP_TABLE_EP2IN_CNTH _SFR_MEM8(0x002B)
+-#define USB_EP_TABLE_EP2IN_DATAPTRL _SFR_MEM8(0x002C)
+-#define USB_EP_TABLE_EP2IN_DATAPTRH _SFR_MEM8(0x002D)
+-#define USB_EP_TABLE_EP2IN_AUXDATAL _SFR_MEM8(0x002E)
+-#define USB_EP_TABLE_EP2IN_AUXDATAH _SFR_MEM8(0x002F)
+-#define USB_EP_TABLE_EP3OUT_STATUS _SFR_MEM8(0x0030)
+-#define USB_EP_TABLE_EP3OUT_CTRL _SFR_MEM8(0x0031)
+-#define USB_EP_TABLE_EP3OUT_CNTL _SFR_MEM8(0x0032)
+-#define USB_EP_TABLE_EP3OUT_CNTH _SFR_MEM8(0x0033)
+-#define USB_EP_TABLE_EP3OUT_DATAPTRL _SFR_MEM8(0x0034)
+-#define USB_EP_TABLE_EP3OUT_DATAPTRH _SFR_MEM8(0x0035)
+-#define USB_EP_TABLE_EP3OUT_AUXDATAL _SFR_MEM8(0x0036)
+-#define USB_EP_TABLE_EP3OUT_AUXDATAH _SFR_MEM8(0x0037)
+-#define USB_EP_TABLE_EP3IN_STATUS _SFR_MEM8(0x0038)
+-#define USB_EP_TABLE_EP3IN_CTRL _SFR_MEM8(0x0039)
+-#define USB_EP_TABLE_EP3IN_CNTL _SFR_MEM8(0x003A)
+-#define USB_EP_TABLE_EP3IN_CNTH _SFR_MEM8(0x003B)
+-#define USB_EP_TABLE_EP3IN_DATAPTRL _SFR_MEM8(0x003C)
+-#define USB_EP_TABLE_EP3IN_DATAPTRH _SFR_MEM8(0x003D)
+-#define USB_EP_TABLE_EP3IN_AUXDATAL _SFR_MEM8(0x003E)
+-#define USB_EP_TABLE_EP3IN_AUXDATAH _SFR_MEM8(0x003F)
+-#define USB_EP_TABLE_EP4OUT_STATUS _SFR_MEM8(0x0040)
+-#define USB_EP_TABLE_EP4OUT_CTRL _SFR_MEM8(0x0041)
+-#define USB_EP_TABLE_EP4OUT_CNTL _SFR_MEM8(0x0042)
+-#define USB_EP_TABLE_EP4OUT_CNTH _SFR_MEM8(0x0043)
+-#define USB_EP_TABLE_EP4OUT_DATAPTRL _SFR_MEM8(0x0044)
+-#define USB_EP_TABLE_EP4OUT_DATAPTRH _SFR_MEM8(0x0045)
+-#define USB_EP_TABLE_EP4OUT_AUXDATAL _SFR_MEM8(0x0046)
+-#define USB_EP_TABLE_EP4OUT_AUXDATAH _SFR_MEM8(0x0047)
+-#define USB_EP_TABLE_EP4IN_STATUS _SFR_MEM8(0x0048)
+-#define USB_EP_TABLE_EP4IN_CTRL _SFR_MEM8(0x0049)
+-#define USB_EP_TABLE_EP4IN_CNTL _SFR_MEM8(0x004A)
+-#define USB_EP_TABLE_EP4IN_CNTH _SFR_MEM8(0x004B)
+-#define USB_EP_TABLE_EP4IN_DATAPTRL _SFR_MEM8(0x004C)
+-#define USB_EP_TABLE_EP4IN_DATAPTRH _SFR_MEM8(0x004D)
+-#define USB_EP_TABLE_EP4IN_AUXDATAL _SFR_MEM8(0x004E)
+-#define USB_EP_TABLE_EP4IN_AUXDATAH _SFR_MEM8(0x004F)
+-#define USB_EP_TABLE_EP5OUT_STATUS _SFR_MEM8(0x0050)
+-#define USB_EP_TABLE_EP5OUT_CTRL _SFR_MEM8(0x0051)
+-#define USB_EP_TABLE_EP5OUT_CNTL _SFR_MEM8(0x0052)
+-#define USB_EP_TABLE_EP5OUT_CNTH _SFR_MEM8(0x0053)
+-#define USB_EP_TABLE_EP5OUT_DATAPTRL _SFR_MEM8(0x0054)
+-#define USB_EP_TABLE_EP5OUT_DATAPTRH _SFR_MEM8(0x0055)
+-#define USB_EP_TABLE_EP5OUT_AUXDATAL _SFR_MEM8(0x0056)
+-#define USB_EP_TABLE_EP5OUT_AUXDATAH _SFR_MEM8(0x0057)
+-#define USB_EP_TABLE_EP5IN_STATUS _SFR_MEM8(0x0058)
+-#define USB_EP_TABLE_EP5IN_CTRL _SFR_MEM8(0x0059)
+-#define USB_EP_TABLE_EP5IN_CNTL _SFR_MEM8(0x005A)
+-#define USB_EP_TABLE_EP5IN_CNTH _SFR_MEM8(0x005B)
+-#define USB_EP_TABLE_EP5IN_DATAPTRL _SFR_MEM8(0x005C)
+-#define USB_EP_TABLE_EP5IN_DATAPTRH _SFR_MEM8(0x005D)
+-#define USB_EP_TABLE_EP5IN_AUXDATAL _SFR_MEM8(0x005E)
+-#define USB_EP_TABLE_EP5IN_AUXDATAH _SFR_MEM8(0x005F)
+-#define USB_EP_TABLE_EP6OUT_STATUS _SFR_MEM8(0x0060)
+-#define USB_EP_TABLE_EP6OUT_CTRL _SFR_MEM8(0x0061)
+-#define USB_EP_TABLE_EP6OUT_CNTL _SFR_MEM8(0x0062)
+-#define USB_EP_TABLE_EP6OUT_CNTH _SFR_MEM8(0x0063)
+-#define USB_EP_TABLE_EP6OUT_DATAPTRL _SFR_MEM8(0x0064)
+-#define USB_EP_TABLE_EP6OUT_DATAPTRH _SFR_MEM8(0x0065)
+-#define USB_EP_TABLE_EP6OUT_AUXDATAL _SFR_MEM8(0x0066)
+-#define USB_EP_TABLE_EP6OUT_AUXDATAH _SFR_MEM8(0x0067)
+-#define USB_EP_TABLE_EP6IN_STATUS _SFR_MEM8(0x0068)
+-#define USB_EP_TABLE_EP6IN_CTRL _SFR_MEM8(0x0069)
+-#define USB_EP_TABLE_EP6IN_CNTL _SFR_MEM8(0x006A)
+-#define USB_EP_TABLE_EP6IN_CNTH _SFR_MEM8(0x006B)
+-#define USB_EP_TABLE_EP6IN_DATAPTRL _SFR_MEM8(0x006C)
+-#define USB_EP_TABLE_EP6IN_DATAPTRH _SFR_MEM8(0x006D)
+-#define USB_EP_TABLE_EP6IN_AUXDATAL _SFR_MEM8(0x006E)
+-#define USB_EP_TABLE_EP6IN_AUXDATAH _SFR_MEM8(0x006F)
+-#define USB_EP_TABLE_EP7OUT_STATUS _SFR_MEM8(0x0070)
+-#define USB_EP_TABLE_EP7OUT_CTRL _SFR_MEM8(0x0071)
+-#define USB_EP_TABLE_EP7OUT_CNTL _SFR_MEM8(0x0072)
+-#define USB_EP_TABLE_EP7OUT_CNTH _SFR_MEM8(0x0073)
+-#define USB_EP_TABLE_EP7OUT_DATAPTRL _SFR_MEM8(0x0074)
+-#define USB_EP_TABLE_EP7OUT_DATAPTRH _SFR_MEM8(0x0075)
+-#define USB_EP_TABLE_EP7OUT_AUXDATAL _SFR_MEM8(0x0076)
+-#define USB_EP_TABLE_EP7OUT_AUXDATAH _SFR_MEM8(0x0077)
+-#define USB_EP_TABLE_EP7IN_STATUS _SFR_MEM8(0x0078)
+-#define USB_EP_TABLE_EP7IN_CTRL _SFR_MEM8(0x0079)
+-#define USB_EP_TABLE_EP7IN_CNTL _SFR_MEM8(0x007A)
+-#define USB_EP_TABLE_EP7IN_CNTH _SFR_MEM8(0x007B)
+-#define USB_EP_TABLE_EP7IN_DATAPTRL _SFR_MEM8(0x007C)
+-#define USB_EP_TABLE_EP7IN_DATAPTRH _SFR_MEM8(0x007D)
+-#define USB_EP_TABLE_EP7IN_AUXDATAL _SFR_MEM8(0x007E)
+-#define USB_EP_TABLE_EP7IN_AUXDATAH _SFR_MEM8(0x007F)
+-#define USB_EP_TABLE_EP8OUT_STATUS _SFR_MEM8(0x0080)
+-#define USB_EP_TABLE_EP8OUT_CTRL _SFR_MEM8(0x0081)
+-#define USB_EP_TABLE_EP8OUT_CNTL _SFR_MEM8(0x0082)
+-#define USB_EP_TABLE_EP8OUT_CNTH _SFR_MEM8(0x0083)
+-#define USB_EP_TABLE_EP8OUT_DATAPTRL _SFR_MEM8(0x0084)
+-#define USB_EP_TABLE_EP8OUT_DATAPTRH _SFR_MEM8(0x0085)
+-#define USB_EP_TABLE_EP8OUT_AUXDATAL _SFR_MEM8(0x0086)
+-#define USB_EP_TABLE_EP8OUT_AUXDATAH _SFR_MEM8(0x0087)
+-#define USB_EP_TABLE_EP8IN_STATUS _SFR_MEM8(0x0088)
+-#define USB_EP_TABLE_EP8IN_CTRL _SFR_MEM8(0x0089)
+-#define USB_EP_TABLE_EP8IN_CNTL _SFR_MEM8(0x008A)
+-#define USB_EP_TABLE_EP8IN_CNTH _SFR_MEM8(0x008B)
+-#define USB_EP_TABLE_EP8IN_DATAPTRL _SFR_MEM8(0x008C)
+-#define USB_EP_TABLE_EP8IN_DATAPTRH _SFR_MEM8(0x008D)
+-#define USB_EP_TABLE_EP8IN_AUXDATAL _SFR_MEM8(0x008E)
+-#define USB_EP_TABLE_EP8IN_AUXDATAH _SFR_MEM8(0x008F)
+-#define USB_EP_TABLE_EP9OUT_STATUS _SFR_MEM8(0x0090)
+-#define USB_EP_TABLE_EP9OUT_CTRL _SFR_MEM8(0x0091)
+-#define USB_EP_TABLE_EP9OUT_CNTL _SFR_MEM8(0x0092)
+-#define USB_EP_TABLE_EP9OUT_CNTH _SFR_MEM8(0x0093)
+-#define USB_EP_TABLE_EP9OUT_DATAPTRL _SFR_MEM8(0x0094)
+-#define USB_EP_TABLE_EP9OUT_DATAPTRH _SFR_MEM8(0x0095)
+-#define USB_EP_TABLE_EP9OUT_AUXDATAL _SFR_MEM8(0x0096)
+-#define USB_EP_TABLE_EP9OUT_AUXDATAH _SFR_MEM8(0x0097)
+-#define USB_EP_TABLE_EP9IN_STATUS _SFR_MEM8(0x0098)
+-#define USB_EP_TABLE_EP9IN_CTRL _SFR_MEM8(0x0099)
+-#define USB_EP_TABLE_EP9IN_CNTL _SFR_MEM8(0x009A)
+-#define USB_EP_TABLE_EP9IN_CNTH _SFR_MEM8(0x009B)
+-#define USB_EP_TABLE_EP9IN_DATAPTRL _SFR_MEM8(0x009C)
+-#define USB_EP_TABLE_EP9IN_DATAPTRH _SFR_MEM8(0x009D)
+-#define USB_EP_TABLE_EP9IN_AUXDATAL _SFR_MEM8(0x009E)
+-#define USB_EP_TABLE_EP9IN_AUXDATAH _SFR_MEM8(0x009F)
+-#define USB_EP_TABLE_EP10OUT_STATUS _SFR_MEM8(0x00A0)
+-#define USB_EP_TABLE_EP10OUT_CTRL _SFR_MEM8(0x00A1)
+-#define USB_EP_TABLE_EP10OUT_CNTL _SFR_MEM8(0x00A2)
+-#define USB_EP_TABLE_EP10OUT_CNTH _SFR_MEM8(0x00A3)
+-#define USB_EP_TABLE_EP10OUT_DATAPTRL _SFR_MEM8(0x00A4)
+-#define USB_EP_TABLE_EP10OUT_DATAPTRH _SFR_MEM8(0x00A5)
+-#define USB_EP_TABLE_EP10OUT_AUXDATAL _SFR_MEM8(0x00A6)
+-#define USB_EP_TABLE_EP10OUT_AUXDATAH _SFR_MEM8(0x00A7)
+-#define USB_EP_TABLE_EP10IN_STATUS _SFR_MEM8(0x00A8)
+-#define USB_EP_TABLE_EP10IN_CTRL _SFR_MEM8(0x00A9)
+-#define USB_EP_TABLE_EP10IN_CNTL _SFR_MEM8(0x00AA)
+-#define USB_EP_TABLE_EP10IN_CNTH _SFR_MEM8(0x00AB)
+-#define USB_EP_TABLE_EP10IN_DATAPTRL _SFR_MEM8(0x00AC)
+-#define USB_EP_TABLE_EP10IN_DATAPTRH _SFR_MEM8(0x00AD)
+-#define USB_EP_TABLE_EP10IN_AUXDATAL _SFR_MEM8(0x00AE)
+-#define USB_EP_TABLE_EP10IN_AUXDATAH _SFR_MEM8(0x00AF)
+-#define USB_EP_TABLE_EP11OUT_STATUS _SFR_MEM8(0x00B0)
+-#define USB_EP_TABLE_EP11OUT_CTRL _SFR_MEM8(0x00B1)
+-#define USB_EP_TABLE_EP11OUT_CNTL _SFR_MEM8(0x00B2)
+-#define USB_EP_TABLE_EP11OUT_CNTH _SFR_MEM8(0x00B3)
+-#define USB_EP_TABLE_EP11OUT_DATAPTRL _SFR_MEM8(0x00B4)
+-#define USB_EP_TABLE_EP11OUT_DATAPTRH _SFR_MEM8(0x00B5)
+-#define USB_EP_TABLE_EP11OUT_AUXDATAL _SFR_MEM8(0x00B6)
+-#define USB_EP_TABLE_EP11OUT_AUXDATAH _SFR_MEM8(0x00B7)
+-#define USB_EP_TABLE_EP11IN_STATUS _SFR_MEM8(0x00B8)
+-#define USB_EP_TABLE_EP11IN_CTRL _SFR_MEM8(0x00B9)
+-#define USB_EP_TABLE_EP11IN_CNTL _SFR_MEM8(0x00BA)
+-#define USB_EP_TABLE_EP11IN_CNTH _SFR_MEM8(0x00BB)
+-#define USB_EP_TABLE_EP11IN_DATAPTRL _SFR_MEM8(0x00BC)
+-#define USB_EP_TABLE_EP11IN_DATAPTRH _SFR_MEM8(0x00BD)
+-#define USB_EP_TABLE_EP11IN_AUXDATAL _SFR_MEM8(0x00BE)
+-#define USB_EP_TABLE_EP11IN_AUXDATAH _SFR_MEM8(0x00BF)
+-#define USB_EP_TABLE_EP12OUT_STATUS _SFR_MEM8(0x00C0)
+-#define USB_EP_TABLE_EP12OUT_CTRL _SFR_MEM8(0x00C1)
+-#define USB_EP_TABLE_EP12OUT_CNTL _SFR_MEM8(0x00C2)
+-#define USB_EP_TABLE_EP12OUT_CNTH _SFR_MEM8(0x00C3)
+-#define USB_EP_TABLE_EP12OUT_DATAPTRL _SFR_MEM8(0x00C4)
+-#define USB_EP_TABLE_EP12OUT_DATAPTRH _SFR_MEM8(0x00C5)
+-#define USB_EP_TABLE_EP12OUT_AUXDATAL _SFR_MEM8(0x00C6)
+-#define USB_EP_TABLE_EP12OUT_AUXDATAH _SFR_MEM8(0x00C7)
+-#define USB_EP_TABLE_EP12IN_STATUS _SFR_MEM8(0x00C8)
+-#define USB_EP_TABLE_EP12IN_CTRL _SFR_MEM8(0x00C9)
+-#define USB_EP_TABLE_EP12IN_CNTL _SFR_MEM8(0x00CA)
+-#define USB_EP_TABLE_EP12IN_CNTH _SFR_MEM8(0x00CB)
+-#define USB_EP_TABLE_EP12IN_DATAPTRL _SFR_MEM8(0x00CC)
+-#define USB_EP_TABLE_EP12IN_DATAPTRH _SFR_MEM8(0x00CD)
+-#define USB_EP_TABLE_EP12IN_AUXDATAL _SFR_MEM8(0x00CE)
+-#define USB_EP_TABLE_EP12IN_AUXDATAH _SFR_MEM8(0x00CF)
+-#define USB_EP_TABLE_EP13OUT_STATUS _SFR_MEM8(0x00D0)
+-#define USB_EP_TABLE_EP13OUT_CTRL _SFR_MEM8(0x00D1)
+-#define USB_EP_TABLE_EP13OUT_CNTL _SFR_MEM8(0x00D2)
+-#define USB_EP_TABLE_EP13OUT_CNTH _SFR_MEM8(0x00D3)
+-#define USB_EP_TABLE_EP13OUT_DATAPTRL _SFR_MEM8(0x00D4)
+-#define USB_EP_TABLE_EP13OUT_DATAPTRH _SFR_MEM8(0x00D5)
+-#define USB_EP_TABLE_EP13OUT_AUXDATAL _SFR_MEM8(0x00D6)
+-#define USB_EP_TABLE_EP13OUT_AUXDATAH _SFR_MEM8(0x00D7)
+-#define USB_EP_TABLE_EP13IN_STATUS _SFR_MEM8(0x00D8)
+-#define USB_EP_TABLE_EP13IN_CTRL _SFR_MEM8(0x00D9)
+-#define USB_EP_TABLE_EP13IN_CNTL _SFR_MEM8(0x00DA)
+-#define USB_EP_TABLE_EP13IN_CNTH _SFR_MEM8(0x00DB)
+-#define USB_EP_TABLE_EP13IN_DATAPTRL _SFR_MEM8(0x00DC)
+-#define USB_EP_TABLE_EP13IN_DATAPTRH _SFR_MEM8(0x00DD)
+-#define USB_EP_TABLE_EP13IN_AUXDATAL _SFR_MEM8(0x00DE)
+-#define USB_EP_TABLE_EP13IN_AUXDATAH _SFR_MEM8(0x00DF)
+-#define USB_EP_TABLE_EP14OUT_STATUS _SFR_MEM8(0x00E0)
+-#define USB_EP_TABLE_EP14OUT_CTRL _SFR_MEM8(0x00E1)
+-#define USB_EP_TABLE_EP14OUT_CNTL _SFR_MEM8(0x00E2)
+-#define USB_EP_TABLE_EP14OUT_CNTH _SFR_MEM8(0x00E3)
+-#define USB_EP_TABLE_EP14OUT_DATAPTRL _SFR_MEM8(0x00E4)
+-#define USB_EP_TABLE_EP14OUT_DATAPTRH _SFR_MEM8(0x00E5)
+-#define USB_EP_TABLE_EP14OUT_AUXDATAL _SFR_MEM8(0x00E6)
+-#define USB_EP_TABLE_EP14OUT_AUXDATAH _SFR_MEM8(0x00E7)
+-#define USB_EP_TABLE_EP14IN_STATUS _SFR_MEM8(0x00E8)
+-#define USB_EP_TABLE_EP14IN_CTRL _SFR_MEM8(0x00E9)
+-#define USB_EP_TABLE_EP14IN_CNTL _SFR_MEM8(0x00EA)
+-#define USB_EP_TABLE_EP14IN_CNTH _SFR_MEM8(0x00EB)
+-#define USB_EP_TABLE_EP14IN_DATAPTRL _SFR_MEM8(0x00EC)
+-#define USB_EP_TABLE_EP14IN_DATAPTRH _SFR_MEM8(0x00ED)
+-#define USB_EP_TABLE_EP14IN_AUXDATAL _SFR_MEM8(0x00EE)
+-#define USB_EP_TABLE_EP14IN_AUXDATAH _SFR_MEM8(0x00EF)
+-#define USB_EP_TABLE_EP15OUT_STATUS _SFR_MEM8(0x00F0)
+-#define USB_EP_TABLE_EP15OUT_CTRL _SFR_MEM8(0x00F1)
+-#define USB_EP_TABLE_EP15OUT_CNTL _SFR_MEM8(0x00F2)
+-#define USB_EP_TABLE_EP15OUT_CNTH _SFR_MEM8(0x00F3)
+-#define USB_EP_TABLE_EP15OUT_DATAPTRL _SFR_MEM8(0x00F4)
+-#define USB_EP_TABLE_EP15OUT_DATAPTRH _SFR_MEM8(0x00F5)
+-#define USB_EP_TABLE_EP15OUT_AUXDATAL _SFR_MEM8(0x00F6)
+-#define USB_EP_TABLE_EP15OUT_AUXDATAH _SFR_MEM8(0x00F7)
+-#define USB_EP_TABLE_EP15IN_STATUS _SFR_MEM8(0x00F8)
+-#define USB_EP_TABLE_EP15IN_CTRL _SFR_MEM8(0x00F9)
+-#define USB_EP_TABLE_EP15IN_CNTL _SFR_MEM8(0x00FA)
+-#define USB_EP_TABLE_EP15IN_CNTH _SFR_MEM8(0x00FB)
+-#define USB_EP_TABLE_EP15IN_DATAPTRL _SFR_MEM8(0x00FC)
+-#define USB_EP_TABLE_EP15IN_DATAPTRH _SFR_MEM8(0x00FD)
+-#define USB_EP_TABLE_EP15IN_AUXDATAL _SFR_MEM8(0x00FE)
+-#define USB_EP_TABLE_EP15IN_AUXDATAH _SFR_MEM8(0x00FF)
+-#define USB_EP_TABLE_FRAMENUML _SFR_MEM8(0x0110)
+-#define USB_EP_TABLE_FRAMENUMH _SFR_MEM8(0x0111)
+-
+ /* GPIO - General Purpose IO Registers */
+ #define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+ #define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+@@ -2980,25 +3134,89 @@
+ #define GPIO_GPIORE _SFR_MEM8(0x000E)
+ #define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+-/* VPORT0 - Virtual Port 0 */
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
+ #define VPORT0_DIR _SFR_MEM8(0x0010)
+ #define VPORT0_OUT _SFR_MEM8(0x0011)
+ #define VPORT0_IN _SFR_MEM8(0x0012)
+ #define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+-/* VPORT1 - Virtual Port 1 */
++/* VPORT - Virtual Port */
+ #define VPORT1_DIR _SFR_MEM8(0x0014)
+ #define VPORT1_OUT _SFR_MEM8(0x0015)
+ #define VPORT1_IN _SFR_MEM8(0x0016)
+ #define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+-/* VPORT2 - Virtual Port 2 */
++/* VPORT - Virtual Port */
+ #define VPORT2_DIR _SFR_MEM8(0x0018)
+ #define VPORT2_OUT _SFR_MEM8(0x0019)
+ #define VPORT2_IN _SFR_MEM8(0x001A)
+ #define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+-/* VPORT3 - Virtual Port 3 */
++/* VPORT - Virtual Port */
+ #define VPORT3_DIR _SFR_MEM8(0x001C)
+ #define VPORT3_OUT _SFR_MEM8(0x001D)
+ #define VPORT3_IN _SFR_MEM8(0x001E)
+@@ -3008,7 +3226,7 @@
+ #define OCD_OCDR0 _SFR_MEM8(0x002E)
+ #define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+-/* CPU - CPU Registers */
++/* CPU - CPU registers */
+ #define CPU_CCP _SFR_MEM8(0x0034)
+ #define CPU_RAMPD _SFR_MEM8(0x0038)
+ #define CPU_RAMPX _SFR_MEM8(0x0039)
+@@ -3029,16 +3247,16 @@
+ /* SLEEP - Sleep Controller */
+ #define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+-/* OSC - Oscillator Control */
++/* OSC - Oscillator */
+ #define OSC_CTRL _SFR_MEM8(0x0050)
+ #define OSC_STATUS _SFR_MEM8(0x0051)
+ #define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+-#define OSC_XOSCFAIL _SFR_MEM8(0x005F)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+ #define OSC_RC32KCAL _SFR_MEM8(0x0054)
+ #define OSC_PLLCTRL _SFR_MEM8(0x0055)
+ #define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
++/* DFLL - DFLL */
+ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+ #define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+ #define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+@@ -3046,7 +3264,7 @@
+ #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+ #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
++/* DFLL - DFLL */
+ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+ #define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+ #define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+@@ -3063,7 +3281,7 @@
+ #define PR_PRPE _SFR_MEM8(0x0075)
+ #define PR_PRPF _SFR_MEM8(0x0076)
+
+-/* RST - Reset Controller */
++/* RST - Reset */
+ #define RST_STATUS _SFR_MEM8(0x0078)
+ #define RST_CTRL _SFR_MEM8(0x0079)
+
+@@ -3083,25 +3301,26 @@
+ #define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+ #define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+-/* PMIC - Programmable Interrupt Controller */
++/* PMIC - Programmable Multi-level Interrupt Controller */
+ #define PMIC_STATUS _SFR_MEM8(0x00A0)
+ #define PMIC_INTPRI _SFR_MEM8(0x00A1)
+ #define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+-/* PORTCFG - Port Configuration */
++/* PORTCFG - I/O port Configuration */
+ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+ #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+ #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+ #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
+
+-/* AES - AES Crypto Module */
++/* AES - AES Module */
+ #define AES_CTRL _SFR_MEM8(0x00C0)
+ #define AES_STATUS _SFR_MEM8(0x00C1)
+ #define AES_STATE _SFR_MEM8(0x00C2)
+ #define AES_KEY _SFR_MEM8(0x00C3)
+ #define AES_INTCTRL _SFR_MEM8(0x00C4)
+
+-/* CRC - CRC Module */
++/* CRC - Cyclic Redundancy Checker */
+ #define CRC_CTRL _SFR_MEM8(0x00D0)
+ #define CRC_STATUS _SFR_MEM8(0x00D1)
+ #define CRC_DATAIN _SFR_MEM8(0x00D3)
+@@ -3184,7 +3403,7 @@
+ #define EVSYS_STROBE _SFR_MEM8(0x0190)
+ #define EVSYS_DATA _SFR_MEM8(0x0191)
+
+-/* NVM - Non Volatile Memory Controller */
++/* NVM - Non-volatile Memory Controller */
+ #define NVM_ADDR0 _SFR_MEM8(0x01C0)
+ #define NVM_ADDR1 _SFR_MEM8(0x01C1)
+ #define NVM_ADDR2 _SFR_MEM8(0x01C2)
+@@ -3198,7 +3417,7 @@
+ #define NVM_STATUS _SFR_MEM8(0x01CF)
+ #define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+-/* ADCA - Analog to Digital Converter A */
++/* ADC - Analog-to-Digital Converter */
+ #define ADCA_CTRLA _SFR_MEM8(0x0200)
+ #define ADCA_CTRLB _SFR_MEM8(0x0201)
+ #define ADCA_REFCTRL _SFR_MEM8(0x0202)
+@@ -3217,23 +3436,27 @@
+ #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+ #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+ #define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
+ #define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
+ #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
+ #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
+ #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
+ #define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
+ #define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
+ #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
+ #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
+ #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
+ #define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
+ #define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
+ #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
+ #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
+ #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
+ #define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
+
+-/* ADCB - Analog to Digital Converter B */
++/* ADC - Analog-to-Digital Converter */
+ #define ADCB_CTRLA _SFR_MEM8(0x0240)
+ #define ADCB_CTRLB _SFR_MEM8(0x0241)
+ #define ADCB_REFCTRL _SFR_MEM8(0x0242)
+@@ -3252,23 +3475,27 @@
+ #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
+ #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
+ #define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
+ #define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
+ #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
+ #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
+ #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
+ #define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
+ #define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
+ #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
+ #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
+ #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
+ #define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
+ #define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
+ #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
+ #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
+ #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
+ #define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
+
+-/* DACA - Digital to Analog Converter A */
++/* DAC - Digital-to-Analog Converter */
+ #define DACA_CTRLA _SFR_MEM8(0x0300)
+ #define DACA_CTRLB _SFR_MEM8(0x0301)
+ #define DACA_CTRLC _SFR_MEM8(0x0302)
+@@ -3282,7 +3509,7 @@
+ #define DACA_CH0DATA _SFR_MEM16(0x0318)
+ #define DACA_CH1DATA _SFR_MEM16(0x031A)
+
+-/* DACB - Digital to Analog Converter B */
++/* DAC - Digital-to-Analog Converter */
+ #define DACB_CTRLA _SFR_MEM8(0x0320)
+ #define DACB_CTRLB _SFR_MEM8(0x0321)
+ #define DACB_CTRLC _SFR_MEM8(0x0322)
+@@ -3296,7 +3523,7 @@
+ #define DACB_CH0DATA _SFR_MEM16(0x0338)
+ #define DACB_CH1DATA _SFR_MEM16(0x033A)
+
+-/* ACA - Analog Comparator A */
++/* AC - Analog Comparator */
+ #define ACA_AC0CTRL _SFR_MEM8(0x0380)
+ #define ACA_AC1CTRL _SFR_MEM8(0x0381)
+ #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+@@ -3306,7 +3533,7 @@
+ #define ACA_WINCTRL _SFR_MEM8(0x0386)
+ #define ACA_STATUS _SFR_MEM8(0x0387)
+
+-/* ACB - Analog Comparator B */
++/* AC - Analog Comparator */
+ #define ACB_AC0CTRL _SFR_MEM8(0x0390)
+ #define ACB_AC1CTRL _SFR_MEM8(0x0391)
+ #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
+@@ -3346,7 +3573,7 @@
+ #define EBI_CS3_CTRLB _SFR_MEM8(0x045D)
+ #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E)
+
+-/* TWIC - Two-Wire Interface C */
++/* TWI - Two-Wire Interface */
+ #define TWIC_CTRL _SFR_MEM8(0x0480)
+ #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
+ #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
+@@ -3362,7 +3589,7 @@
+ #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+ #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+-/* TWID - Two-Wire Interface D */
++/* TWI - Two-Wire Interface */
+ #define TWID_CTRL _SFR_MEM8(0x0490)
+ #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491)
+ #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492)
+@@ -3378,7 +3605,7 @@
+ #define TWID_SLAVE_DATA _SFR_MEM8(0x049C)
+ #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D)
+
+-/* TWIE - Two-Wire Interface E */
++/* TWI - Two-Wire Interface */
+ #define TWIE_CTRL _SFR_MEM8(0x04A0)
+ #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
+ #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
+@@ -3394,7 +3621,7 @@
+ #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
+ #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
+
+-/* TWIF - Two-Wire Interface F */
++/* TWI - Two-Wire Interface */
+ #define TWIF_CTRL _SFR_MEM8(0x04B0)
+ #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1)
+ #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2)
+@@ -3410,7 +3637,7 @@
+ #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC)
+ #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD)
+
+-/* USB - Universal Serial Bus Module */
++/* USB - Universal Serial Bus */
+ #define USB_CTRLA _SFR_MEM8(0x04C0)
+ #define USB_CTRLB _SFR_MEM8(0x04C1)
+ #define USB_STATUS _SFR_MEM8(0x04C2)
+@@ -3427,7 +3654,7 @@
+ #define USB_CAL0 _SFR_MEM8(0x04FA)
+ #define USB_CAL1 _SFR_MEM8(0x04FB)
+
+-/* PORTA - Port A */
++/* PORT - I/O Ports */
+ #define PORTA_DIR _SFR_MEM8(0x0600)
+ #define PORTA_DIRSET _SFR_MEM8(0x0601)
+ #define PORTA_DIRCLR _SFR_MEM8(0x0602)
+@@ -3441,6 +3668,7 @@
+ #define PORTA_INT0MASK _SFR_MEM8(0x060A)
+ #define PORTA_INT1MASK _SFR_MEM8(0x060B)
+ #define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
+ #define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+ #define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+ #define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+@@ -3450,7 +3678,7 @@
+ #define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+ #define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+-/* PORTB - Port B */
++/* PORT - I/O Ports */
+ #define PORTB_DIR _SFR_MEM8(0x0620)
+ #define PORTB_DIRSET _SFR_MEM8(0x0621)
+ #define PORTB_DIRCLR _SFR_MEM8(0x0622)
+@@ -3464,6 +3692,7 @@
+ #define PORTB_INT0MASK _SFR_MEM8(0x062A)
+ #define PORTB_INT1MASK _SFR_MEM8(0x062B)
+ #define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
+ #define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+ #define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+ #define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+@@ -3473,7 +3702,7 @@
+ #define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+ #define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+-/* PORTC - Port C */
++/* PORT - I/O Ports */
+ #define PORTC_DIR _SFR_MEM8(0x0640)
+ #define PORTC_DIRSET _SFR_MEM8(0x0641)
+ #define PORTC_DIRCLR _SFR_MEM8(0x0642)
+@@ -3487,6 +3716,7 @@
+ #define PORTC_INT0MASK _SFR_MEM8(0x064A)
+ #define PORTC_INT1MASK _SFR_MEM8(0x064B)
+ #define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
+ #define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+ #define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+ #define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+@@ -3496,7 +3726,7 @@
+ #define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+ #define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+-/* PORTD - Port D */
++/* PORT - I/O Ports */
+ #define PORTD_DIR _SFR_MEM8(0x0660)
+ #define PORTD_DIRSET _SFR_MEM8(0x0661)
+ #define PORTD_DIRCLR _SFR_MEM8(0x0662)
+@@ -3510,6 +3740,7 @@
+ #define PORTD_INT0MASK _SFR_MEM8(0x066A)
+ #define PORTD_INT1MASK _SFR_MEM8(0x066B)
+ #define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
+ #define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+ #define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+ #define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+@@ -3519,7 +3750,7 @@
+ #define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+ #define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+-/* PORTE - Port E */
++/* PORT - I/O Ports */
+ #define PORTE_DIR _SFR_MEM8(0x0680)
+ #define PORTE_DIRSET _SFR_MEM8(0x0681)
+ #define PORTE_DIRCLR _SFR_MEM8(0x0682)
+@@ -3533,6 +3764,7 @@
+ #define PORTE_INT0MASK _SFR_MEM8(0x068A)
+ #define PORTE_INT1MASK _SFR_MEM8(0x068B)
+ #define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
+ #define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+ #define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+ #define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+@@ -3542,7 +3774,7 @@
+ #define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+ #define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+-/* PORTF - Port F */
++/* PORT - I/O Ports */
+ #define PORTF_DIR _SFR_MEM8(0x06A0)
+ #define PORTF_DIRSET _SFR_MEM8(0x06A1)
+ #define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+@@ -3556,6 +3788,7 @@
+ #define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+ #define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+ #define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
+ #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+ #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+ #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+@@ -3565,7 +3798,7 @@
+ #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+ #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+-/* PORTH - Port H */
++/* PORT - I/O Ports */
+ #define PORTH_DIR _SFR_MEM8(0x06E0)
+ #define PORTH_DIRSET _SFR_MEM8(0x06E1)
+ #define PORTH_DIRCLR _SFR_MEM8(0x06E2)
+@@ -3579,6 +3812,7 @@
+ #define PORTH_INT0MASK _SFR_MEM8(0x06EA)
+ #define PORTH_INT1MASK _SFR_MEM8(0x06EB)
+ #define PORTH_INTFLAGS _SFR_MEM8(0x06EC)
++#define PORTH_REMAP _SFR_MEM8(0x06EE)
+ #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0)
+ #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1)
+ #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2)
+@@ -3588,7 +3822,7 @@
+ #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6)
+ #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7)
+
+-/* PORTJ - Port J */
++/* PORT - I/O Ports */
+ #define PORTJ_DIR _SFR_MEM8(0x0700)
+ #define PORTJ_DIRSET _SFR_MEM8(0x0701)
+ #define PORTJ_DIRCLR _SFR_MEM8(0x0702)
+@@ -3602,6 +3836,7 @@
+ #define PORTJ_INT0MASK _SFR_MEM8(0x070A)
+ #define PORTJ_INT1MASK _SFR_MEM8(0x070B)
+ #define PORTJ_INTFLAGS _SFR_MEM8(0x070C)
++#define PORTJ_REMAP _SFR_MEM8(0x070E)
+ #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710)
+ #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711)
+ #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712)
+@@ -3611,7 +3846,7 @@
+ #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716)
+ #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717)
+
+-/* PORTK - Port K */
++/* PORT - I/O Ports */
+ #define PORTK_DIR _SFR_MEM8(0x0720)
+ #define PORTK_DIRSET _SFR_MEM8(0x0721)
+ #define PORTK_DIRCLR _SFR_MEM8(0x0722)
+@@ -3625,6 +3860,7 @@
+ #define PORTK_INT0MASK _SFR_MEM8(0x072A)
+ #define PORTK_INT1MASK _SFR_MEM8(0x072B)
+ #define PORTK_INTFLAGS _SFR_MEM8(0x072C)
++#define PORTK_REMAP _SFR_MEM8(0x072E)
+ #define PORTK_PIN0CTRL _SFR_MEM8(0x0730)
+ #define PORTK_PIN1CTRL _SFR_MEM8(0x0731)
+ #define PORTK_PIN2CTRL _SFR_MEM8(0x0732)
+@@ -3634,7 +3870,7 @@
+ #define PORTK_PIN6CTRL _SFR_MEM8(0x0736)
+ #define PORTK_PIN7CTRL _SFR_MEM8(0x0737)
+
+-/* PORTQ - Port Q */
++/* PORT - I/O Ports */
+ #define PORTQ_DIR _SFR_MEM8(0x07C0)
+ #define PORTQ_DIRSET _SFR_MEM8(0x07C1)
+ #define PORTQ_DIRCLR _SFR_MEM8(0x07C2)
+@@ -3648,6 +3884,7 @@
+ #define PORTQ_INT0MASK _SFR_MEM8(0x07CA)
+ #define PORTQ_INT1MASK _SFR_MEM8(0x07CB)
+ #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC)
++#define PORTQ_REMAP _SFR_MEM8(0x07CE)
+ #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0)
+ #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1)
+ #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2)
+@@ -3657,7 +3894,7 @@
+ #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6)
+ #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7)
+
+-/* PORTR - Port R */
++/* PORT - I/O Ports */
+ #define PORTR_DIR _SFR_MEM8(0x07E0)
+ #define PORTR_DIRSET _SFR_MEM8(0x07E1)
+ #define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+@@ -3671,6 +3908,7 @@
+ #define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+ #define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+ #define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
+ #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+ #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+ #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+@@ -3680,7 +3918,7 @@
+ #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+ #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+-/* TCC0 - Timer/Counter C0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCC0_CTRLA _SFR_MEM8(0x0800)
+ #define TCC0_CTRLB _SFR_MEM8(0x0801)
+ #define TCC0_CTRLC _SFR_MEM8(0x0802)
+@@ -3706,7 +3944,29 @@
+ #define TCC0_CCCBUF _SFR_MEM16(0x083C)
+ #define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+-/* TCC1 - Timer/Counter C1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCC1_CTRLA _SFR_MEM8(0x0840)
+ #define TCC1_CTRLB _SFR_MEM8(0x0841)
+ #define TCC1_CTRLC _SFR_MEM8(0x0842)
+@@ -3728,11 +3988,12 @@
+ #define TCC1_CCABUF _SFR_MEM16(0x0878)
+ #define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+-/* AWEXC - Advanced Waveform Extension C */
++/* AWEX - Advanced Waveform Extension */
+ #define AWEXC_CTRL _SFR_MEM8(0x0880)
+ #define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+ #define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+ #define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
+ #define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+ #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+ #define AWEXC_DTLS _SFR_MEM8(0x0888)
+@@ -3741,10 +4002,10 @@
+ #define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+ #define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+-/* HIRESC - High-Resolution Extension C */
++/* HIRES - High-Resolution Extension */
+ #define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTC0_DATA _SFR_MEM8(0x08A0)
+ #define USARTC0_STATUS _SFR_MEM8(0x08A1)
+ #define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+@@ -3753,7 +4014,7 @@
+ #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+ #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTC1_DATA _SFR_MEM8(0x08B0)
+ #define USARTC1_STATUS _SFR_MEM8(0x08B1)
+ #define USARTC1_CTRLA _SFR_MEM8(0x08B3)
+@@ -3762,7 +4023,7 @@
+ #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
+ #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
+
+-/* SPIC - Serial Peripheral Interface C */
++/* SPI - Serial Peripheral Interface */
+ #define SPIC_CTRL _SFR_MEM8(0x08C0)
+ #define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+ #define SPIC_STATUS _SFR_MEM8(0x08C2)
+@@ -3773,7 +4034,7 @@
+ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+ #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+-/* TCD0 - Timer/Counter D0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCD0_CTRLA _SFR_MEM8(0x0900)
+ #define TCD0_CTRLB _SFR_MEM8(0x0901)
+ #define TCD0_CTRLC _SFR_MEM8(0x0902)
+@@ -3799,7 +4060,29 @@
+ #define TCD0_CCCBUF _SFR_MEM16(0x093C)
+ #define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+-/* TCD1 - Timer/Counter D1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCD1_CTRLA _SFR_MEM8(0x0940)
+ #define TCD1_CTRLB _SFR_MEM8(0x0941)
+ #define TCD1_CTRLC _SFR_MEM8(0x0942)
+@@ -3821,10 +4104,10 @@
+ #define TCD1_CCABUF _SFR_MEM16(0x0978)
+ #define TCD1_CCBBUF _SFR_MEM16(0x097A)
+
+-/* HIRESD - High-Resolution Extension D */
++/* HIRES - High-Resolution Extension */
+ #define HIRESD_CTRLA _SFR_MEM8(0x0990)
+
+-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTD0_DATA _SFR_MEM8(0x09A0)
+ #define USARTD0_STATUS _SFR_MEM8(0x09A1)
+ #define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+@@ -3833,7 +4116,7 @@
+ #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+ #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTD1_DATA _SFR_MEM8(0x09B0)
+ #define USARTD1_STATUS _SFR_MEM8(0x09B1)
+ #define USARTD1_CTRLA _SFR_MEM8(0x09B3)
+@@ -3842,13 +4125,13 @@
+ #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
+ #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
+
+-/* SPID - Serial Peripheral Interface D */
++/* SPI - Serial Peripheral Interface */
+ #define SPID_CTRL _SFR_MEM8(0x09C0)
+ #define SPID_INTCTRL _SFR_MEM8(0x09C1)
+ #define SPID_STATUS _SFR_MEM8(0x09C2)
+ #define SPID_DATA _SFR_MEM8(0x09C3)
+
+-/* TCE0 - Timer/Counter E0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCE0_CTRLA _SFR_MEM8(0x0A00)
+ #define TCE0_CTRLB _SFR_MEM8(0x0A01)
+ #define TCE0_CTRLC _SFR_MEM8(0x0A02)
+@@ -3874,7 +4157,29 @@
+ #define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+ #define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+-/* TCE1 - Timer/Counter E1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCE1_CTRLA _SFR_MEM8(0x0A40)
+ #define TCE1_CTRLB _SFR_MEM8(0x0A41)
+ #define TCE1_CTRLC _SFR_MEM8(0x0A42)
+@@ -3896,11 +4201,12 @@
+ #define TCE1_CCABUF _SFR_MEM16(0x0A78)
+ #define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
+
+-/* AWEXE - Advanced Waveform Extension E */
++/* AWEX - Advanced Waveform Extension */
+ #define AWEXE_CTRL _SFR_MEM8(0x0A80)
+ #define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+ #define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+ #define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
+ #define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+ #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+ #define AWEXE_DTLS _SFR_MEM8(0x0A88)
+@@ -3909,10 +4215,10 @@
+ #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+ #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+-/* HIRESE - High-Resolution Extension E */
++/* HIRES - High-Resolution Extension */
+ #define HIRESE_CTRLA _SFR_MEM8(0x0A90)
+
+-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTE0_DATA _SFR_MEM8(0x0AA0)
+ #define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+ #define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+@@ -3921,7 +4227,7 @@
+ #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+ #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTE1_DATA _SFR_MEM8(0x0AB0)
+ #define USARTE1_STATUS _SFR_MEM8(0x0AB1)
+ #define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
+@@ -3930,13 +4236,13 @@
+ #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
+ #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
+
+-/* SPIE - Serial Peripheral Interface E */
++/* SPI - Serial Peripheral Interface */
+ #define SPIE_CTRL _SFR_MEM8(0x0AC0)
+ #define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+ #define SPIE_STATUS _SFR_MEM8(0x0AC2)
+ #define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+-/* TCF0 - Timer/Counter F0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCF0_CTRLA _SFR_MEM8(0x0B00)
+ #define TCF0_CTRLB _SFR_MEM8(0x0B01)
+ #define TCF0_CTRLC _SFR_MEM8(0x0B02)
+@@ -3962,7 +4268,29 @@
+ #define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+ #define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+-/* TCF1 - Timer/Counter F1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCF1_CTRLA _SFR_MEM8(0x0B40)
+ #define TCF1_CTRLB _SFR_MEM8(0x0B41)
+ #define TCF1_CTRLC _SFR_MEM8(0x0B42)
+@@ -3984,10 +4312,10 @@
+ #define TCF1_CCABUF _SFR_MEM16(0x0B78)
+ #define TCF1_CCBBUF _SFR_MEM16(0x0B7A)
+
+-/* HIRESF - High-Resolution Extension F */
++/* HIRES - High-Resolution Extension */
+ #define HIRESF_CTRLA _SFR_MEM8(0x0B90)
+
+-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTF0_DATA _SFR_MEM8(0x0BA0)
+ #define USARTF0_STATUS _SFR_MEM8(0x0BA1)
+ #define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
+@@ -3996,7 +4324,7 @@
+ #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
+ #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
+
+-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTF1_DATA _SFR_MEM8(0x0BB0)
+ #define USARTF1_STATUS _SFR_MEM8(0x0BB1)
+ #define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
+@@ -4005,7 +4333,7 @@
+ #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
+ #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
+
+-/* SPIF - Serial Peripheral Interface F */
++/* SPI - Serial Peripheral Interface */
+ #define SPIF_CTRL _SFR_MEM8(0x0BC0)
+ #define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
+ #define SPIF_STATUS _SFR_MEM8(0x0BC2)
+@@ -4023,13 +4351,11 @@
+ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+-
+ /* XOCD - On-Chip Debug System */
+ /* OCD.OCDR1 bit masks and bit positions */
+ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+-
+ /* CPU - CPU */
+ /* CPU.CCP bit masks and bit positions */
+ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+@@ -4051,7 +4377,6 @@
+ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+-
+ /* CPU.SREG bit masks and bit positions */
+ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+@@ -4077,7 +4402,6 @@
+ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+ #define CPU_C_bp 0 /* Carry Flag bit position. */
+
+-
+ /* CLK - Clock System */
+ /* CLK.CTRL bit masks and bit positions */
+ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+@@ -4089,7 +4413,6 @@
+ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+-
+ /* CLK.PSCTRL bit masks and bit positions */
+ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+@@ -4111,12 +4434,10 @@
+ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+-
+ /* CLK.LOCK bit masks and bit positions */
+ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+-
+ /* CLK.RTCCTRL bit masks and bit positions */
+ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+@@ -4130,7 +4451,6 @@
+ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
+ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
+
+-
+ /* CLK.USBCTRL bit masks and bit positions */
+ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
+ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
+@@ -4148,9 +4468,8 @@
+ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
+
+-#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */
+-#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */
+-
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
+
+ /* PR.PRGEN bit masks and bit positions */
+ #define PR_USB_bm 0x40 /* USB bit mask. */
+@@ -4171,7 +4490,6 @@
+ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+ #define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+-
+ /* PR.PRPA bit masks and bit positions */
+ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+ #define PR_DAC_bp 2 /* Port A DAC bit position. */
+@@ -4182,17 +4500,15 @@
+ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+-
+ /* PR.PRPB bit masks and bit positions */
+-/* PR_DAC_bm Predefined. */
+-/* PR_DAC_bp Predefined. */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
+
+-/* PR_ADC_bm Predefined. */
+-/* PR_ADC_bp Predefined. */
+-
+-/* PR_AC_bm Predefined. */
+-/* PR_AC_bp Predefined. */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
+
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
+
+ /* PR.PRPC bit masks and bit positions */
+ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+@@ -4216,75 +4532,71 @@
+ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+-
+ /* PR.PRPD bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
+-
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* PR.PRPE bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
+-
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* PR.PRPF bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
+-
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* SLEEP - Sleep Controller */
+ /* SLEEP.CTRL bit masks and bit positions */
+@@ -4300,7 +4612,6 @@
+ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+-
+ /* OSC - Oscillator */
+ /* OSC.CTRL bit masks and bit positions */
+ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+@@ -4318,7 +4629,6 @@
+ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
+ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
+
+-
+ /* OSC.STATUS bit masks and bit positions */
+ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+@@ -4335,7 +4645,6 @@
+ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
+ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
+
+-
+ /* OSC.XOSCCTRL bit masks and bit positions */
+ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+@@ -4347,6 +4656,9 @@
+ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
+ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
+
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
+ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+@@ -4358,7 +4670,6 @@
+ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+-
+ /* OSC.XOSCFAIL bit masks and bit positions */
+ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
+ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
+@@ -4372,7 +4683,6 @@
+ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
+ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
+
+-
+ /* OSC.PLLCTRL bit masks and bit positions */
+ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+@@ -4381,6 +4691,9 @@
+ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
+ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+@@ -4394,25 +4707,22 @@
+ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+-
+ /* OSC.DFLLCTRL bit masks and bit positions */
+-#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */
+-#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */
+-#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */
+-#define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */
+-#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */
+-#define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */
+-
+-#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */
+-#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
+
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
+
+ /* DFLL - DFLL */
+ /* DFLL.CTRL bit masks and bit positions */
+ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+-
+ /* DFLL.CALA bit masks and bit positions */
+ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
+ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
+@@ -4431,7 +4741,6 @@
+ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
+ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
+
+-
+ /* DFLL.CALB bit masks and bit positions */
+ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
+ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
+@@ -4448,7 +4757,6 @@
+ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
+ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
+
+-
+ /* RST - Reset */
+ /* RST.STATUS bit masks and bit positions */
+ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+@@ -4472,12 +4780,10 @@
+ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+-
+ /* RST.CTRL bit masks and bit positions */
+ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+ #define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+-
+ /* WDT - Watch-Dog Timer */
+ /* WDT.CTRL bit masks and bit positions */
+ #define WDT_PER_gm 0x3C /* Period group mask. */
+@@ -4497,7 +4803,6 @@
+ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+ #define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+-
+ /* WDT.WINCTRL bit masks and bit positions */
+ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+@@ -4516,33 +4821,29 @@
+ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+-
+ /* WDT.STATUS bit masks and bit positions */
+ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+-
+ /* MCU - MCU Control */
+ /* MCU.MCUCR bit masks and bit positions */
+ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+-
+ /* MCU.ANAINIT bit masks and bit positions */
+-#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */
+-#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */
+-#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */
+-#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */
+-#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */
+-#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */
+-
+-#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */
+-#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */
+-#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */
+-#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */
+-#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */
+-#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */
+-
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
+
+ /* MCU.EVSYSLOCK bit masks and bit positions */
+ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+@@ -4551,15 +4852,19 @@
+ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+-
+ /* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
+ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
+ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+-
+ /* PMIC - Programmable Multi-level Interrupt Controller */
+ /* PMIC.STATUS bit masks and bit positions */
+ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+@@ -4574,7 +4879,6 @@
+ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+-
+ /* PMIC.CTRL bit masks and bit positions */
+ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+@@ -4591,7 +4895,6 @@
+ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+-
+ /* PORTCFG - Port Configuration */
+ /* PORTCFG.VPCTRLA bit masks and bit positions */
+ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+@@ -4616,7 +4919,6 @@
+ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+-
+ /* PORTCFG.VPCTRLB bit masks and bit positions */
+ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+@@ -4640,7 +4942,6 @@
+ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+-
+ /* PORTCFG.CLKEVOUT bit masks and bit positions */
+ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
+ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
+@@ -4669,6 +4970,15 @@
+ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
+ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
+
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
+
+ /* AES - AES Module */
+ /* AES.CTRL bit masks and bit positions */
+@@ -4687,7 +4997,6 @@
+ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
+ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
+
+-
+ /* AES.STATUS bit masks and bit positions */
+ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */
+ #define AES_ERROR_bp 7 /* AES Error bit position. */
+@@ -4695,7 +5004,6 @@
+ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
+ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
+
+-
+ /* AES.INTCTRL bit masks and bit positions */
+ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
+ #define AES_INTLVL_gp 0 /* Interrupt level group position. */
+@@ -4704,38 +5012,35 @@
+ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+-
+ /* CRC - Cyclic Redundancy Checker */
+ /* CRC.CTRL bit masks and bit positions */
+-#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */
+-#define CRC_RESET_gp 6 /* CRC Reset group position. */
+-#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */
+-#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */
+-#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */
+-#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+-#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */
+-#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */
+-#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */
+-#define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */
+-#define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */
+-#define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */
+-#define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */
+-#define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */
+-#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */
+-#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */
+-
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+ /* CRC.STATUS bit masks and bit positions */
+-#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */
+-#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */
+-
+-#define CRC_BUSY_bm 0x01 /* Enable bit mask. */
+-#define CRC_BUSY_bp 0 /* Enable bit position. */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+ /* DMA - DMA Controller */
+ /* DMA_CH.CTRLA bit masks and bit positions */
+@@ -4761,7 +5066,6 @@
+ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
+ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
+
+-
+ /* DMA_CH.CTRLB bit masks and bit positions */
+ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
+ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
+@@ -4789,7 +5093,6 @@
+ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
+ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
+
+-
+ /* DMA_CH.ADDRCTRL bit masks and bit positions */
+ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
+ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
+@@ -4819,7 +5122,6 @@
+ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
+ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
+
+-
+ /* DMA_CH.TRIGSRC bit masks and bit positions */
+ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
+ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
+@@ -4840,7 +5142,6 @@
+ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
+ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
+
+-
+ /* DMA.CTRL bit masks and bit positions */
+ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
+ #define DMA_ENABLE_bp 7 /* Enable bit position. */
+@@ -4862,7 +5163,6 @@
+ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
+ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
+
+-
+ /* DMA.INTFLAGS bit masks and bit positions */
+ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+@@ -4888,7 +5188,6 @@
+ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+
+-
+ /* DMA.STATUS bit masks and bit positions */
+ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
+ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
+@@ -4914,7 +5213,6 @@
+ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
+ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
+
+-
+ /* EVSYS - Event System */
+ /* EVSYS.CH0MUX bit masks and bit positions */
+ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+@@ -4936,153 +5234,33 @@
+ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+-
+ /* EVSYS.CH1MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH2MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH3MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH4MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH5MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH6MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH7MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH0CTRL bit masks and bit positions */
+ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+@@ -5107,109 +5285,51 @@
+ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+-
+ /* EVSYS.CH1CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
+-
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH2CTRL bit masks and bit positions */
+-/* EVSYS_QDIRM_gm Predefined. */
+-/* EVSYS_QDIRM_gp Predefined. */
+-/* EVSYS_QDIRM0_bm Predefined. */
+-/* EVSYS_QDIRM0_bp Predefined. */
+-/* EVSYS_QDIRM1_bm Predefined. */
+-/* EVSYS_QDIRM1_bp Predefined. */
+-
+-/* EVSYS_QDIEN_bm Predefined. */
+-/* EVSYS_QDIEN_bp Predefined. */
+-
+-/* EVSYS_QDEN_bm Predefined. */
+-/* EVSYS_QDEN_bp Predefined. */
+-
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
+
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
+
+-/* EVSYS.CH3CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH4CTRL bit masks and bit positions */
+-/* EVSYS_QDIRM_gm Predefined. */
+-/* EVSYS_QDIRM_gp Predefined. */
+-/* EVSYS_QDIRM0_bm Predefined. */
+-/* EVSYS_QDIRM0_bp Predefined. */
+-/* EVSYS_QDIRM1_bm Predefined. */
+-/* EVSYS_QDIRM1_bp Predefined. */
+-
+-/* EVSYS_QDIEN_bm Predefined. */
+-/* EVSYS_QDIEN_bp Predefined. */
+-
+-/* EVSYS_QDEN_bm Predefined. */
+-/* EVSYS_QDEN_bp Predefined. */
+-
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
+
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
+
+-/* EVSYS.CH5CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
+
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+-/* EVSYS.CH6CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH7CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
+-
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* NVM - Non Volatile Memory Controller */
+ /* NVM.CMD bit masks and bit positions */
+@@ -5230,12 +5350,10 @@
+ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+ #define NVM_CMD6_bp 6 /* Command bit 6 position. */
+
+-
+ /* NVM.CTRLA bit masks and bit positions */
+ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+-
+ /* NVM.CTRLB bit masks and bit positions */
+ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+@@ -5249,7 +5367,6 @@
+ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+-
+ /* NVM.INTCTRL bit masks and bit positions */
+ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+@@ -5265,7 +5382,6 @@
+ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+-
+ /* NVM.STATUS bit masks and bit positions */
+ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+@@ -5279,7 +5395,6 @@
+ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+-
+ /* NVM.LOCKBITS bit masks and bit positions */
+ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+@@ -5309,7 +5424,6 @@
+ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+-
+ /* ADC - Analog/Digital Converter */
+ /* ADC_CH.CTRL bit masks and bit positions */
+ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+@@ -5331,7 +5445,6 @@
+ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+-
+ /* ADC_CH.MUXCTRL bit masks and bit positions */
+ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
+ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
+@@ -5362,7 +5475,6 @@
+ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
+ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
+
+-
+ /* ADC_CH.INTCTRL bit masks and bit positions */
+ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+@@ -5378,11 +5490,32 @@
+ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+-
+ /* ADC_CH.INTFLAGS bit masks and bit positions */
+ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
+
+ /* ADC.CTRLA bit masks and bit positions */
+ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
+@@ -5410,17 +5543,16 @@
+ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+-
+ /* ADC.CTRLB bit masks and bit positions */
+ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
+ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
+
+-#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */
+-#define ADC_CURRENT_gp 5 /* Current Limitation group position. */
+-#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */
+-#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */
+-#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */
+-#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
+
+ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+@@ -5435,7 +5567,6 @@
+ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+-
+ /* ADC.REFCTRL bit masks and bit positions */
+ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
+ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+@@ -5452,7 +5583,6 @@
+ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+-
+ /* ADC.EVCTRL bit masks and bit positions */
+ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+@@ -5479,7 +5609,6 @@
+ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+-
+ /* ADC.PRESCALER bit masks and bit positions */
+ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+@@ -5490,7 +5619,6 @@
+ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+-
+ /* ADC.INTFLAGS bit masks and bit positions */
+ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
+ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
+@@ -5504,7 +5632,6 @@
+ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+-
+ /* DAC - Digital/Analog Converter */
+ /* DAC.CTRLA bit masks and bit positions */
+ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
+@@ -5522,7 +5649,6 @@
+ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
+ #define DAC_ENABLE_bp 0 /* Enable bit position. */
+
+-
+ /* DAC.CTRLB bit masks and bit positions */
+ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
+ #define DAC_CHSEL_gp 5 /* Channel Select group position. */
+@@ -5537,7 +5663,6 @@
+ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
+ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
+
+-
+ /* DAC.CTRLC bit masks and bit positions */
+ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
+ #define DAC_REFSEL_gp 3 /* Reference Select group position. */
+@@ -5549,7 +5674,6 @@
+ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
+ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
+
+-
+ /* DAC.EVCTRL bit masks and bit positions */
+ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
+ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
+@@ -5563,7 +5687,6 @@
+ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
+ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
+
+-
+ /* DAC.TIMCTRL bit masks and bit positions */
+ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
+ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
+@@ -5585,7 +5708,6 @@
+ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
+ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
+
+-
+ /* DAC.STATUS bit masks and bit positions */
+ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
+ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
+@@ -5593,7 +5715,6 @@
+ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
+ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
+
+-
+ /* DAC.CH0GAINCAL bit masks and bit positions */
+ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
+ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
+@@ -5612,7 +5733,6 @@
+ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
+ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
+
+-
+ /* DAC.CH0OFFSETCAL bit masks and bit positions */
+ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
+ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
+@@ -5631,7 +5751,6 @@
+ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
+ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
+
+-
+ /* DAC.CH1GAINCAL bit masks and bit positions */
+ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
+ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
+@@ -5650,7 +5769,6 @@
+ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
+ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
+
+-
+ /* DAC.CH1OFFSETCAL bit masks and bit positions */
+ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
+ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
+@@ -5669,7 +5787,6 @@
+ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
+ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
+
+-
+ /* AC - Analog Comparator */
+ /* AC.AC0CTRL bit masks and bit positions */
+ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+@@ -5699,35 +5816,21 @@
+ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+ #define AC_ENABLE_bp 0 /* Enable bit position. */
+
+-
+ /* AC.AC1CTRL bit masks and bit positions */
+-/* AC_INTMODE_gm Predefined. */
+-/* AC_INTMODE_gp Predefined. */
+-/* AC_INTMODE0_bm Predefined. */
+-/* AC_INTMODE0_bp Predefined. */
+-/* AC_INTMODE1_bm Predefined. */
+-/* AC_INTMODE1_bp Predefined. */
+-
+-/* AC_INTLVL_gm Predefined. */
+-/* AC_INTLVL_gp Predefined. */
+-/* AC_INTLVL0_bm Predefined. */
+-/* AC_INTLVL0_bp Predefined. */
+-/* AC_INTLVL1_bm Predefined. */
+-/* AC_INTLVL1_bp Predefined. */
+-
+-/* AC_HSMODE_bm Predefined. */
+-/* AC_HSMODE_bp Predefined. */
+-
+-/* AC_HYSMODE_gm Predefined. */
+-/* AC_HYSMODE_gp Predefined. */
+-/* AC_HYSMODE0_bm Predefined. */
+-/* AC_HYSMODE0_bp Predefined. */
+-/* AC_HYSMODE1_bm Predefined. */
+-/* AC_HYSMODE1_bp Predefined. */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
+
+-/* AC_ENABLE_bm Predefined. */
+-/* AC_ENABLE_bp Predefined. */
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
+
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
+
+ /* AC.AC0MUXCTRL bit masks and bit positions */
+ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+@@ -5748,32 +5851,20 @@
+ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+-
+ /* AC.AC1MUXCTRL bit masks and bit positions */
+-/* AC_MUXPOS_gm Predefined. */
+-/* AC_MUXPOS_gp Predefined. */
+-/* AC_MUXPOS0_bm Predefined. */
+-/* AC_MUXPOS0_bp Predefined. */
+-/* AC_MUXPOS1_bm Predefined. */
+-/* AC_MUXPOS1_bp Predefined. */
+-/* AC_MUXPOS2_bm Predefined. */
+-/* AC_MUXPOS2_bp Predefined. */
+-
+-/* AC_MUXNEG_gm Predefined. */
+-/* AC_MUXNEG_gp Predefined. */
+-/* AC_MUXNEG0_bm Predefined. */
+-/* AC_MUXNEG0_bp Predefined. */
+-/* AC_MUXNEG1_bm Predefined. */
+-/* AC_MUXNEG1_bp Predefined. */
+-/* AC_MUXNEG2_bm Predefined. */
+-/* AC_MUXNEG2_bp Predefined. */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
+
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
+
+ /* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
+ #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
+ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
+
+-
+ /* AC.CTRLB bit masks and bit positions */
+ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+@@ -5790,7 +5881,6 @@
+ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+-
+ /* AC.WINCTRL bit masks and bit positions */
+ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+@@ -5809,7 +5899,6 @@
+ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+-
+ /* AC.STATUS bit masks and bit positions */
+ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+ #define AC_WSTATE_gp 6 /* Window Mode State group position. */
+@@ -5833,8 +5922,7 @@
+ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
+ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
+
+-
+-/* RTC - Real-Time Clounter */
++/* RTC - Real-Time Counter */
+ /* RTC.CTRL bit masks and bit positions */
+ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+@@ -5845,12 +5933,10 @@
+ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+-
+ /* RTC.STATUS bit masks and bit positions */
+ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+-
+ /* RTC.INTCTRL bit masks and bit positions */
+ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+@@ -5866,7 +5952,6 @@
+ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+-
+ /* RTC.INTFLAGS bit masks and bit positions */
+ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+@@ -5874,21 +5959,20 @@
+ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+-
+ /* EBI - External Bus Interface */
+ /* EBI_CS.CTRLA bit masks and bit positions */
+-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */
+-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */
+-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */
+-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */
+-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */
+-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */
+-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */
+-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */
+-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */
+-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */
+-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */
+-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */
++#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
++#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
++#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
++#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
++#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
++#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
++#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
++#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
++#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
++#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
++#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
++#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+@@ -5897,7 +5981,6 @@
+ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+-
+ /* EBI_CS.CTRLB bit masks and bit positions */
+ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+@@ -5921,7 +6004,6 @@
+ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+-
+ /* EBI.CTRL bit masks and bit positions */
+ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+@@ -5951,7 +6033,6 @@
+ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+-
+ /* EBI.SDRAMCTRLA bit masks and bit positions */
+ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+@@ -5966,7 +6047,6 @@
+ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+-
+ /* EBI.SDRAMCTRLB bit masks and bit positions */
+ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+@@ -5993,7 +6073,6 @@
+ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+-
+ /* EBI.SDRAMCTRLC bit masks and bit positions */
+ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+@@ -6020,7 +6099,6 @@
+ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+-
+ /* TWI - Two-Wire Interface */
+ /* TWI_MASTER.CTRLA bit masks and bit positions */
+ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+@@ -6039,7 +6117,6 @@
+ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+-
+ /* TWI_MASTER.CTRLB bit masks and bit positions */
+ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+@@ -6054,7 +6131,6 @@
+ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+-
+ /* TWI_MASTER.CTRLC bit masks and bit positions */
+ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+@@ -6066,7 +6142,6 @@
+ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+-
+ /* TWI_MASTER.STATUS bit masks and bit positions */
+ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+@@ -6093,7 +6168,6 @@
+ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+-
+ /* TWI_SLAVE.CTRLA bit masks and bit positions */
+ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+@@ -6120,7 +6194,6 @@
+ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+-
+ /* TWI_SLAVE.CTRLB bit masks and bit positions */
+ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+@@ -6132,7 +6205,6 @@
+ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+-
+ /* TWI_SLAVE.STATUS bit masks and bit positions */
+ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+@@ -6158,7 +6230,6 @@
+ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+-
+ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+@@ -6180,7 +6251,6 @@
+ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+-
+ /* TWI.CTRL bit masks and bit positions */
+ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+@@ -6188,23 +6258,25 @@
+ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+-
+-/* USB - USB Module */
++/* USB - USB */
+ /* USB_EP.STATUS bit masks and bit positions */
+-#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */
+-#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
+
+-#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */
+-#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
+
+-#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */
+-#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
+
+-#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */
+-#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
+
+-#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */
+-#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
+
+ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
+ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
+@@ -6221,7 +6293,6 @@
+ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
+ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
+
+-
+ /* USB_EP.CTRL bit masks and bit positions */
+ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
+ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
+@@ -6239,30 +6310,21 @@
+ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
+ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
+
+-/* USB_EP_STALL_bm Predefined. */
+-/* USB_EP_STALL_bp Predefined. */
+-
+-#define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */
+-#define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */
+-#define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
+-#define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */
+-#define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
+-#define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */
+-#define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
+-#define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */
+-
+-
+-/* USB_EP.CNTH bit masks and bit positions */
+-#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */
+-#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */
+-
+-#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */
+-#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */
+-#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */
+-#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */
+-#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */
+-#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
+
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
+
+ /* USB.CTRLA bit masks and bit positions */
+ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
+@@ -6288,7 +6350,6 @@
+ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
+ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
+
+-
+ /* USB.CTRLB bit masks and bit positions */
+ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
+ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
+@@ -6302,7 +6363,6 @@
+ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */
+ #define USB_ATTACH_bp 0 /* Attach bit position. */
+
+-
+ /* USB.STATUS bit masks and bit positions */
+ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
+ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */
+@@ -6316,7 +6376,6 @@
+ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
+ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */
+
+-
+ /* USB.ADDR bit masks and bit positions */
+ #define USB_ADDR_gm 0x7F /* Device Address group mask. */
+ #define USB_ADDR_gp 0 /* Device Address group position. */
+@@ -6335,7 +6394,6 @@
+ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
+ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
+
+-
+ /* USB.FIFOWP bit masks and bit positions */
+ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
+ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
+@@ -6350,7 +6408,6 @@
+ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
+ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
+
+-
+ /* USB.FIFORP bit masks and bit positions */
+ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
+ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
+@@ -6365,7 +6422,6 @@
+ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
+ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
+
+-
+ /* USB.INTCTRLA bit masks and bit positions */
+ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
+ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
+@@ -6386,7 +6442,6 @@
+ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+-
+ /* USB.INTCTRLB bit masks and bit positions */
+ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
+ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
+@@ -6394,7 +6449,6 @@
+ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
+ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
+
+-
+ /* USB.INTFLAGSACLR bit masks and bit positions */
+ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
+ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
+@@ -6420,32 +6474,30 @@
+ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
+ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
+
+-
+ /* USB.INTFLAGSASET bit masks and bit positions */
+-/* USB_SOFIF_bm Predefined. */
+-/* USB_SOFIF_bp Predefined. */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
+
+-/* USB_SUSPENDIF_bm Predefined. */
+-/* USB_SUSPENDIF_bp Predefined. */
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
+
+-/* USB_RESUMEIF_bm Predefined. */
+-/* USB_RESUMEIF_bp Predefined. */
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
+
+-/* USB_RSTIF_bm Predefined. */
+-/* USB_RSTIF_bp Predefined. */
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
+
+-/* USB_CRCIF_bm Predefined. */
+-/* USB_CRCIF_bp Predefined. */
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
+
+-/* USB_UNFIF_bm Predefined. */
+-/* USB_UNFIF_bp Predefined. */
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
+
+-/* USB_OVFIF_bm Predefined. */
+-/* USB_OVFIF_bp Predefined. */
+-
+-/* USB_STALLIF_bm Predefined. */
+-/* USB_STALLIF_bp Predefined. */
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
+
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
+
+ /* USB.INTFLAGSBCLR bit masks and bit positions */
+ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
+@@ -6454,14 +6506,12 @@
+ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
+ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
+
+-
+ /* USB.INTFLAGSBSET bit masks and bit positions */
+-/* USB_TRNIF_bm Predefined. */
+-/* USB_TRNIF_bp Predefined. */
+-
+-/* USB_SETUPIF_bm Predefined. */
+-/* USB_SETUPIF_bp Predefined. */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
+
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
+
+ /* PORT - I/O Port Configuration */
+ /* PORT.INTCTRL bit masks and bit positions */
+@@ -6479,7 +6529,6 @@
+ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+-
+ /* PORT.INTFLAGS bit masks and bit positions */
+ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+@@ -6487,6 +6536,24 @@
+ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
+
+ /* PORT.PIN0CTRL bit masks and bit positions */
+ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+@@ -6513,188 +6580,96 @@
+ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+-
+ /* PORT.PIN1CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN2CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN3CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN4CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN5CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN6CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN7CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* TC - 16-bit Timer/Counter With PWM */
+ /* TC0.CTRLA bit masks and bit positions */
+@@ -6709,7 +6684,6 @@
+ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+-
+ /* TC0.CTRLB bit masks and bit positions */
+ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+@@ -6732,7 +6706,6 @@
+ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+-
+ /* TC0.CTRLC bit masks and bit positions */
+ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+@@ -6746,7 +6719,6 @@
+ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+-
+ /* TC0.CTRLD bit masks and bit positions */
+ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+ #define TC0_EVACT_gp 5 /* Event Action group position. */
+@@ -6771,11 +6743,13 @@
+ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+-
+ /* TC0.CTRLE bit masks and bit positions */
+-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+-
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
+
+ /* TC0.INTCTRLA bit masks and bit positions */
+ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+@@ -6792,7 +6766,6 @@
+ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+-
+ /* TC0.INTCTRLB bit masks and bit positions */
+ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+@@ -6822,7 +6795,6 @@
+ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+-
+ /* TC0.CTRLFCLR bit masks and bit positions */
+ #define TC0_CMD_gm 0x0C /* Command group mask. */
+ #define TC0_CMD_gp 2 /* Command group position. */
+@@ -6837,21 +6809,15 @@
+ #define TC0_DIR_bm 0x01 /* Direction bit mask. */
+ #define TC0_DIR_bp 0 /* Direction bit position. */
+
+-
+ /* TC0.CTRLFSET bit masks and bit positions */
+-/* TC0_CMD_gm Predefined. */
+-/* TC0_CMD_gp Predefined. */
+-/* TC0_CMD0_bm Predefined. */
+-/* TC0_CMD0_bp Predefined. */
+-/* TC0_CMD1_bm Predefined. */
+-/* TC0_CMD1_bp Predefined. */
+-
+-/* TC0_LUPD_bm Predefined. */
+-/* TC0_LUPD_bp Predefined. */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
+
+-/* TC0_DIR_bm Predefined. */
+-/* TC0_DIR_bp Predefined. */
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
+
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
+
+ /* TC0.CTRLGCLR bit masks and bit positions */
+ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+@@ -6869,23 +6835,21 @@
+ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+-
+ /* TC0.CTRLGSET bit masks and bit positions */
+-/* TC0_CCDBV_bm Predefined. */
+-/* TC0_CCDBV_bp Predefined. */
+-
+-/* TC0_CCCBV_bm Predefined. */
+-/* TC0_CCCBV_bp Predefined. */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
+
+-/* TC0_CCBBV_bm Predefined. */
+-/* TC0_CCBBV_bp Predefined. */
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
+
+-/* TC0_CCABV_bm Predefined. */
+-/* TC0_CCABV_bp Predefined. */
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
+
+-/* TC0_PERBV_bm Predefined. */
+-/* TC0_PERBV_bp Predefined. */
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
+
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
+
+ /* TC0.INTFLAGS bit masks and bit positions */
+ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+@@ -6906,7 +6870,6 @@
+ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+-
+ /* TC1.CTRLA bit masks and bit positions */
+ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+@@ -6919,7 +6882,6 @@
+ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+-
+ /* TC1.CTRLB bit masks and bit positions */
+ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+@@ -6936,7 +6898,6 @@
+ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+-
+ /* TC1.CTRLC bit masks and bit positions */
+ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+@@ -6944,7 +6905,6 @@
+ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+-
+ /* TC1.CTRLD bit masks and bit positions */
+ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+ #define TC1_EVACT_gp 5 /* Event Action group position. */
+@@ -6969,12 +6929,10 @@
+ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+-
+ /* TC1.CTRLE bit masks and bit positions */
+ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+-
+ /* TC1.INTCTRLA bit masks and bit positions */
+ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+@@ -6990,7 +6948,6 @@
+ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+-
+ /* TC1.INTCTRLB bit masks and bit positions */
+ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+@@ -7006,7 +6963,6 @@
+ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+-
+ /* TC1.CTRLFCLR bit masks and bit positions */
+ #define TC1_CMD_gm 0x0C /* Command group mask. */
+ #define TC1_CMD_gp 2 /* Command group position. */
+@@ -7021,21 +6977,15 @@
+ #define TC1_DIR_bm 0x01 /* Direction bit mask. */
+ #define TC1_DIR_bp 0 /* Direction bit position. */
+
+-
+ /* TC1.CTRLFSET bit masks and bit positions */
+-/* TC1_CMD_gm Predefined. */
+-/* TC1_CMD_gp Predefined. */
+-/* TC1_CMD0_bm Predefined. */
+-/* TC1_CMD0_bp Predefined. */
+-/* TC1_CMD1_bm Predefined. */
+-/* TC1_CMD1_bp Predefined. */
+-
+-/* TC1_LUPD_bm Predefined. */
+-/* TC1_LUPD_bp Predefined. */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
+
+-/* TC1_DIR_bm Predefined. */
+-/* TC1_DIR_bp Predefined. */
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
+
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
+
+ /* TC1.CTRLGCLR bit masks and bit positions */
+ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+@@ -7047,17 +6997,15 @@
+ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+-
+ /* TC1.CTRLGSET bit masks and bit positions */
+-/* TC1_CCBBV_bm Predefined. */
+-/* TC1_CCBBV_bp Predefined. */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
+
+-/* TC1_CCABV_bm Predefined. */
+-/* TC1_CCABV_bp Predefined. */
+-
+-/* TC1_PERBV_bm Predefined. */
+-/* TC1_PERBV_bp Predefined. */
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
+
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
+
+ /* TC1.INTFLAGS bit masks and bit positions */
+ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+@@ -7072,6 +7020,154 @@
+ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
+
+ /* AWEX - Timer/Counter Advanced Waveform Extension */
+ /* AWEX.CTRL bit masks and bit positions */
+@@ -7093,7 +7189,6 @@
+ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+-
+ /* AWEX.FDCTRL bit masks and bit positions */
+ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+@@ -7108,7 +7203,6 @@
+ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+-
+ /* AWEX.STATUS bit masks and bit positions */
+ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+@@ -7119,6 +7213,15 @@
+ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
+
+ /* HIRES - Timer/Counter High-Resolution Extension */
+ /* HIRES.CTRLA bit masks and bit positions */
+@@ -7129,7 +7232,6 @@
+ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+-
+ /* USART - Universal Asynchronous Receiver-Transmitter */
+ /* USART.STATUS bit masks and bit positions */
+ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+@@ -7153,7 +7255,6 @@
+ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+-
+ /* USART.CTRLA bit masks and bit positions */
+ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+@@ -7176,7 +7277,6 @@
+ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+-
+ /* USART.CTRLB bit masks and bit positions */
+ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+@@ -7193,7 +7293,6 @@
+ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+-
+ /* USART.CTRLC bit masks and bit positions */
+ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+ #define USART_CMODE_gp 6 /* Communication Mode group position. */
+@@ -7221,7 +7320,6 @@
+ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+-
+ /* USART.BAUDCTRLA bit masks and bit positions */
+ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+@@ -7242,7 +7340,6 @@
+ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+-
+ /* USART.BAUDCTRLB bit masks and bit positions */
+ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+@@ -7255,17 +7352,8 @@
+ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+-/* USART_BSEL_gm Predefined. */
+-/* USART_BSEL_gp Predefined. */
+-/* USART_BSEL0_bm Predefined. */
+-/* USART_BSEL0_bp Predefined. */
+-/* USART_BSEL1_bm Predefined. */
+-/* USART_BSEL1_bp Predefined. */
+-/* USART_BSEL2_bm Predefined. */
+-/* USART_BSEL2_bp Predefined. */
+-/* USART_BSEL3_bm Predefined. */
+-/* USART_BSEL3_bp Predefined. */
+-
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
+
+ /* SPI - Serial Peripheral Interface */
+ /* SPI.CTRL bit masks and bit positions */
+@@ -7295,7 +7383,6 @@
+ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+-
+ /* SPI.INTCTRL bit masks and bit positions */
+ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+@@ -7304,7 +7391,6 @@
+ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+-
+ /* SPI.STATUS bit masks and bit positions */
+ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+@@ -7312,7 +7398,6 @@
+ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+-
+ /* IRCOM - IR Communication Module */
+ /* IRCOM.CTRL bit masks and bit positions */
+ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+@@ -7326,34 +7411,152 @@
+ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+-
+-/* PRESC - Prescaler */
+-/* PRESC.PRESCALER bit masks and bit positions */
+-#define PRESC_RESET_bm 0x01 /* Reset bit mask. */
+-#define PRESC_RESET_bp 0 /* Reset bit position. */
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+
+ // Generic Port Pins
+
+-#define PIN0_bm 0x01
++#define PIN0_bm 0x01
+ #define PIN0_bp 0
+ #define PIN1_bm 0x02
+ #define PIN1_bp 1
+-#define PIN2_bm 0x04
++#define PIN2_bm 0x04
+ #define PIN2_bp 2
+-#define PIN3_bm 0x08
++#define PIN3_bm 0x08
+ #define PIN3_bp 3
+-#define PIN4_bm 0x10
++#define PIN4_bm 0x10
+ #define PIN4_bp 4
+-#define PIN5_bm 0x20
++#define PIN5_bm 0x20
+ #define PIN5_bp 5
+-#define PIN6_bm 0x40
++#define PIN6_bm 0x40
+ #define PIN6_bp 6
+-#define PIN7_bm 0x80
++#define PIN7_bm 0x80
+ #define PIN7_bp 7
+
+-
+ /* ========== Interrupt Vector Definitions ========== */
+ /* Vector 0 is the reset vector */
+
+@@ -7398,17 +7601,51 @@
+ /* TCC0 interrupt vectors */
+ #define TCC0_OVF_vect_num 14
+ #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_ERR_vect_num 15
+ #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCA_vect_num 16
+ #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCB_vect_num 17
+ #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCC_vect_num 18
+ #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCD_vect_num 19
+ #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
+ /* TCC1 interrupt vectors */
+ #define TCC1_OVF_vect_num 20
+ #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+@@ -7444,10 +7681,10 @@
+ #define AES_INT_vect _VECTOR(31) /* AES Interrupt */
+
+ /* NVM interrupt vectors */
+-#define NVM_SPM_vect_num 32
+-#define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */
+-#define NVM_EE_vect_num 33
+-#define NVM_EE_vect _VECTOR(33) /* EE Interrupt */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+ /* PORTB interrupt vectors */
+ #define PORTB_INT0_vect_num 34
+@@ -7488,17 +7725,51 @@
+ /* TCE0 interrupt vectors */
+ #define TCE0_OVF_vect_num 47
+ #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_ERR_vect_num 48
+ #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCA_vect_num 49
+ #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCB_vect_num 50
+ #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCC_vect_num 51
+ #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCD_vect_num 52
+ #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
+ /* TCE1 interrupt vectors */
+ #define TCE1_OVF_vect_num 53
+ #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
+@@ -7568,17 +7839,51 @@
+ /* TCD0 interrupt vectors */
+ #define TCD0_OVF_vect_num 77
+ #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_ERR_vect_num 78
+ #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCA_vect_num 79
+ #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCB_vect_num 80
+ #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCC_vect_num 81
+ #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCD_vect_num 82
+ #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
+ /* TCD1 interrupt vectors */
+ #define TCD1_OVF_vect_num 83
+ #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
+@@ -7648,17 +7953,51 @@
+ /* TCF0 interrupt vectors */
+ #define TCF0_OVF_vect_num 108
+ #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_ERR_vect_num 109
+ #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCA_vect_num 110
+ #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCB_vect_num 111
+ #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCC_vect_num 112
+ #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCD_vect_num 113
+ #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
+ /* TCF1 interrupt vectors */
+ #define TCF1_OVF_vect_num 114
+ #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */
+@@ -7691,23 +8030,21 @@
+
+ /* USB interrupt vectors */
+ #define USB_BUSEVENT_vect_num 125
+-#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */
+-#define USB_TRNCOMPL_vect_num 127
+-#define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */
+-
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
+
+ #define _VECTOR_SIZE 4 /* Size of individual vector. */
+-#define _VECTORS_SIZE (128 * _VECTOR_SIZE)
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
+
+
+ /* ========== Constants ========== */
+
+-#define PROGMEM_START (0x00000)
++#define PROGMEM_START (0x0000)
+ #define PROGMEM_SIZE (139264)
+-#define PROGMEM_PAGE_SIZE (512)
+ #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+-#define APP_SECTION_START (0x00000)
++#define APP_SECTION_START (0x0000)
+ #define APP_SECTION_SIZE (131072)
+ #define APP_SECTION_PAGE_SIZE (512)
+ #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+@@ -7722,14 +8059,8 @@
+ #define BOOT_SECTION_PAGE_SIZE (512)
+ #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+-#define EEPROM_START (0x0000)
+-#define EEPROM_SIZE (2048)
+-#define EEPROM_PAGE_SIZE (32)
+-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+-
+ #define DATAMEM_START (0x0000)
+ #define DATAMEM_SIZE (16777216)
+-#define DATAMEM_PAGE_SIZE (0)
+ #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+ #define IO_START (0x0000)
+@@ -7747,51 +8078,95 @@
+ #define INTERNAL_SRAM_PAGE_SIZE (0)
+ #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+-#define EXTERNAL_SRAM_START (0x4000)
+-#define EXTERNAL_SRAM_SIZE (16760832)
+-#define EXTERNAL_SRAM_PAGE_SIZE (0)
+-#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
+-
+-#define FUSE_START (0x0000)
+-#define FUSE_SIZE (6)
+-#define FUSE_PAGE_SIZE (0)
+-#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+-
+-#define LOCKBIT_START (0x0000)
+-#define LOCKBIT_SIZE (1)
+-#define LOCKBIT_PAGE_SIZE (0)
+-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+ #define SIGNATURES_START (0x0000)
+ #define SIGNATURES_SIZE (3)
+ #define SIGNATURES_PAGE_SIZE (0)
+ #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
+ #define USER_SIGNATURES_START (0x0000)
+ #define USER_SIGNATURES_SIZE (512)
+-#define USER_SIGNATURES_PAGE_SIZE (0)
++#define USER_SIGNATURES_PAGE_SIZE (512)
+ #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+ #define PROD_SIGNATURES_START (0x0000)
+-#define PROD_SIGNATURES_SIZE (52)
+-#define PROD_SIGNATURES_PAGE_SIZE (0)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
+ #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+ #define FLASHEND PROGMEM_END
+-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
++#define SPM_PAGESIZE 512
+ #define RAMSTART INTERNAL_SRAM_START
+ #define RAMSIZE INTERNAL_SRAM_SIZE
+ #define RAMEND INTERNAL_SRAM_END
+-#define XRAMSTART EXTERNAL_SRAM_START
+-#define XRAMSIZE EXTERNAL_SRAM_SIZE
+-#define XRAMEND EXTERNAL_SRAM_END
+ #define E2END EEPROM_END
+ #define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+ /* ========== Fuses ========== */
+-#define FUSE_MEMORY_SIZE 0
++#define FUSE_MEMORY_SIZE 6
+
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
+
+ /* ========== Lock Bits ========== */
+ #define __LOCK_BITS_EXIST
+@@ -7799,12 +8174,11 @@
+ #define __BOOT_LOCK_APPLICATION_BITS_EXIST
+ #define __BOOT_LOCK_BOOT_BITS_EXIST
+
+-
+ /* ========== Signature ========== */
+ #define SIGNATURE_0 0x1E
+ #define SIGNATURE_1 0x97
+ #define SIGNATURE_2 0x4C
+
+
+-#endif /* _AVR_ATxmega128A1U_H_ */
++#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */
+
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128a3u.h avr-libc-1.8.0/include/avr/iox128a3u.h
+--- avr-libc-1.8.0.orig/include/avr/iox128a3u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128a3u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7588 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128a3u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED
++#define _AVR_ATXMEGA128A3U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CH1RES _SFR_MEM16(0x0252)
++#define ADCB_CH2RES _SFR_MEM16(0x0254)
++#define ADCB_CH3RES _SFR_MEM16(0x0256)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
++#define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
++#define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
++#define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCE1_CTRLA _SFR_MEM8(0x0A40)
++#define TCE1_CTRLB _SFR_MEM8(0x0A41)
++#define TCE1_CTRLC _SFR_MEM8(0x0A42)
++#define TCE1_CTRLD _SFR_MEM8(0x0A43)
++#define TCE1_CTRLE _SFR_MEM8(0x0A44)
++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
++#define TCE1_TEMP _SFR_MEM8(0x0A4F)
++#define TCE1_CNT _SFR_MEM16(0x0A60)
++#define TCE1_PER _SFR_MEM16(0x0A66)
++#define TCE1_CCA _SFR_MEM16(0x0A68)
++#define TCE1_CCB _SFR_MEM16(0x0A6A)
++#define TCE1_PERBUF _SFR_MEM16(0x0A76)
++#define TCE1_CCABUF _SFR_MEM16(0x0A78)
++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXE_CTRL _SFR_MEM8(0x0A80)
++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
++#define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
++#define AWEXE_DTLS _SFR_MEM8(0x0A88)
++#define AWEXE_DTHS _SFR_MEM8(0x0A89)
++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1_DATA _SFR_MEM8(0x0AB0)
++#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIE_CTRL _SFR_MEM8(0x0AC0)
++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
++#define SPIE_STATUS _SFR_MEM8(0x0AC2)
++#define SPIE_DATA _SFR_MEM8(0x0AC3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 36
++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 37
++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 38
++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 39
++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
++#define ADCB_CH1_vect_num 40
++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
++#define ADCB_CH2_vect_num 41
++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
++#define ADCB_CH3_vect_num 42
++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* TCE1 interrupt vectors */
++#define TCE1_OVF_vect_num 53
++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
++#define TCE1_ERR_vect_num 54
++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
++#define TCE1_CCA_vect_num 55
++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
++#define TCE1_CCB_vect_num 56
++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
++
++/* SPIE interrupt vectors */
++#define SPIE_INT_vect_num 57
++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* USARTE1 interrupt vectors */
++#define USARTE1_RXC_vect_num 61
++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
++#define USARTE1_DRE_vect_num 62
++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
++#define USARTE1_TXC_vect_num 63
++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USARTF0 interrupt vectors */
++#define USARTF0_RXC_vect_num 119
++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
++#define USARTF0_DRE_vect_num 120
++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
++#define USARTF0_TXC_vect_num 121
++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x42
++
++
++#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128a4u.h avr-libc-1.8.0/include/avr/iox128a4u.h
+--- avr-libc-1.8.0.orig/include/avr/iox128a4u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128a4u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7200 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128a4u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED
++#define _AVR_ATXMEGA128A4U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x46
++
++
++#endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128b1.h avr-libc-1.8.0/include/avr/iox128b1.h
+--- avr-libc-1.8.0.orig/include/avr/iox128b1.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128b1.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,6778 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128b1.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128B1_H_INCLUDED
++#define _AVR_ATXMEGA128B1_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++PR - Power Reduction
++--------------------------------------------------------------------------
++*/
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t reserved_0x04;
++ register8_t PRPE; /* Power Reduction Port E */
++} PR_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */
++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */
++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LCD - LCD Controller
++--------------------------------------------------------------------------
++*/
++
++/* LCD Controller */
++typedef struct LCD_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t INTCTRL; /* Interrupt Enable Register */
++ register8_t INTFLAG; /* Interrupt Flag Register */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t CTRLH; /* Control Register H */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t DATA0; /* LCD Data Register 0 */
++ register8_t DATA1; /* LCD Data Register 1 */
++ register8_t DATA2; /* LCD Data Register 2 */
++ register8_t DATA3; /* LCD Data Register 3 */
++ register8_t DATA4; /* LCD Data Register 4 */
++ register8_t DATA5; /* LCD Data Register 5 */
++ register8_t DATA6; /* LCD Data Register 6 */
++ register8_t DATA7; /* LCD Data Register 7 */
++ register8_t DATA8; /* LCD Data Register 8 */
++ register8_t DATA9; /* LCD Data Register 9 */
++ register8_t DATA10; /* LCD Data Register 10 */
++ register8_t DATA11; /* LCD Data Register 11 */
++ register8_t DATA12; /* LCD Data Register 12 */
++ register8_t DATA13; /* LCD Data Register 13 */
++ register8_t DATA14; /* LCD Data Register 14 */
++ register8_t DATA15; /* LCD Data Register 15 */
++ register8_t DATA16; /* LCD Data Register 16 */
++ register8_t DATA17; /* LCD Data Register 17 */
++ register8_t DATA18; /* LCD Data Register 18 */
++ register8_t DATA19; /* LCD Data Register 19 */
++} LCD_t;
++
++/* LCD Blink Rate */
++typedef enum LCD_BLINKRATE_enum
++{
++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */
++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */
++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */
++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */
++} LCD_BLINKRATE_t;
++
++/* LCD Clock Divide */
++typedef enum LCD_CLKDIV_enum
++{
++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */
++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */
++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */
++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */
++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */
++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */
++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */
++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */
++} LCD_CLKDIV_t;
++
++/* Duty Select */
++typedef enum LCD_DUTY_enum
++{
++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */
++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */
++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */
++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */
++} LCD_DUTY_t;
++
++/* LCD Prescaler Select */
++typedef enum LCD_PRESC_enum
++{
++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */
++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */
++} LCD_PRESC_t;
++
++/* Type of Digit */
++typedef enum LCD_TDG_enum
++{
++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */
++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */
++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */
++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */
++} LCD_TDG_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */
++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPE _SFR_MEM8(0x0075)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM8(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++#define ACA_CURRCTRL _SFR_MEM8(0x0388)
++#define ACA_CURRCALIB _SFR_MEM8(0x0389)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++#define ACB_CURRCTRL _SFR_MEM8(0x0398)
++#define ACB_CURRCALIB _SFR_MEM8(0x0399)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTG_DIR _SFR_MEM8(0x06C0)
++#define PORTG_DIRSET _SFR_MEM8(0x06C1)
++#define PORTG_DIRCLR _SFR_MEM8(0x06C2)
++#define PORTG_DIRTGL _SFR_MEM8(0x06C3)
++#define PORTG_OUT _SFR_MEM8(0x06C4)
++#define PORTG_OUTSET _SFR_MEM8(0x06C5)
++#define PORTG_OUTCLR _SFR_MEM8(0x06C6)
++#define PORTG_OUTTGL _SFR_MEM8(0x06C7)
++#define PORTG_IN _SFR_MEM8(0x06C8)
++#define PORTG_INTCTRL _SFR_MEM8(0x06C9)
++#define PORTG_INT0MASK _SFR_MEM8(0x06CA)
++#define PORTG_INT1MASK _SFR_MEM8(0x06CB)
++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC)
++#define PORTG_REMAP _SFR_MEM8(0x06CE)
++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0)
++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1)
++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2)
++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3)
++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4)
++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5)
++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6)
++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7)
++
++/* PORT - I/O Ports */
++#define PORTM_DIR _SFR_MEM8(0x0760)
++#define PORTM_DIRSET _SFR_MEM8(0x0761)
++#define PORTM_DIRCLR _SFR_MEM8(0x0762)
++#define PORTM_DIRTGL _SFR_MEM8(0x0763)
++#define PORTM_OUT _SFR_MEM8(0x0764)
++#define PORTM_OUTSET _SFR_MEM8(0x0765)
++#define PORTM_OUTCLR _SFR_MEM8(0x0766)
++#define PORTM_OUTTGL _SFR_MEM8(0x0767)
++#define PORTM_IN _SFR_MEM8(0x0768)
++#define PORTM_INTCTRL _SFR_MEM8(0x0769)
++#define PORTM_INT0MASK _SFR_MEM8(0x076A)
++#define PORTM_INT1MASK _SFR_MEM8(0x076B)
++#define PORTM_INTFLAGS _SFR_MEM8(0x076C)
++#define PORTM_REMAP _SFR_MEM8(0x076E)
++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770)
++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771)
++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772)
++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773)
++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774)
++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775)
++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776)
++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* LCD - LCD Controller */
++#define LCD_CTRLA _SFR_MEM8(0x0D00)
++#define LCD_CTRLB _SFR_MEM8(0x0D01)
++#define LCD_CTRLC _SFR_MEM8(0x0D02)
++#define LCD_INTCTRL _SFR_MEM8(0x0D03)
++#define LCD_INTFLAG _SFR_MEM8(0x0D04)
++#define LCD_CTRLD _SFR_MEM8(0x0D05)
++#define LCD_CTRLE _SFR_MEM8(0x0D06)
++#define LCD_CTRLF _SFR_MEM8(0x0D07)
++#define LCD_CTRLG _SFR_MEM8(0x0D08)
++#define LCD_CTRLH _SFR_MEM8(0x0D09)
++#define LCD_DATA0 _SFR_MEM8(0x0D10)
++#define LCD_DATA1 _SFR_MEM8(0x0D11)
++#define LCD_DATA2 _SFR_MEM8(0x0D12)
++#define LCD_DATA3 _SFR_MEM8(0x0D13)
++#define LCD_DATA4 _SFR_MEM8(0x0D14)
++#define LCD_DATA5 _SFR_MEM8(0x0D15)
++#define LCD_DATA6 _SFR_MEM8(0x0D16)
++#define LCD_DATA7 _SFR_MEM8(0x0D17)
++#define LCD_DATA8 _SFR_MEM8(0x0D18)
++#define LCD_DATA9 _SFR_MEM8(0x0D19)
++#define LCD_DATA10 _SFR_MEM8(0x0D1A)
++#define LCD_DATA11 _SFR_MEM8(0x0D1B)
++#define LCD_DATA12 _SFR_MEM8(0x0D1C)
++#define LCD_DATA13 _SFR_MEM8(0x0D1D)
++#define LCD_DATA14 _SFR_MEM8(0x0D1E)
++#define LCD_DATA15 _SFR_MEM8(0x0D1F)
++#define LCD_DATA16 _SFR_MEM8(0x0D20)
++#define LCD_DATA17 _SFR_MEM8(0x0D21)
++#define LCD_DATA18 _SFR_MEM8(0x0D22)
++#define LCD_DATA19 _SFR_MEM8(0x0D23)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* PR - Power Reduction */
++/* PR.PRGEN bit masks and bit positions */
++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */
++#define PR_LCD_bp 7 /* LCD Module bit position. */
++
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */
++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */
++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */
++
++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */
++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */
++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* LCD - LCD Controller */
++/* LCD.CTRLA bit masks and bit positions */
++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */
++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */
++
++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */
++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */
++
++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */
++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */
++
++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */
++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */
++
++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */
++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */
++
++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */
++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */
++
++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */
++#define LCD_SEGON_bp 1 /* Segments On bit position. */
++
++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */
++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */
++
++/* LCD.CTRLB bit masks and bit positions */
++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */
++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */
++
++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */
++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */
++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */
++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */
++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */
++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */
++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */
++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */
++
++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */
++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */
++
++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */
++#define LCD_DUTY_gp 0 /* Duty Select group position. */
++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */
++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */
++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */
++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */
++
++/* LCD.CTRLC bit masks and bit positions */
++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */
++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */
++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */
++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */
++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */
++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */
++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */
++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */
++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */
++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */
++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */
++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */
++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */
++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */
++
++/* LCD.INTCTRL bit masks and bit positions */
++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */
++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */
++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */
++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */
++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */
++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */
++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */
++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */
++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */
++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */
++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */
++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */
++
++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */
++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* LCD.INTFLAG bit masks and bit positions */
++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */
++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */
++
++/* LCD.CTRLD bit masks and bit positions */
++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */
++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */
++
++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */
++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */
++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */
++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */
++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */
++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */
++
++/* LCD.CTRLE bit masks and bit positions */
++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */
++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */
++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */
++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */
++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */
++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */
++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */
++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */
++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */
++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */
++
++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */
++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */
++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */
++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */
++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */
++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */
++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */
++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */
++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */
++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */
++
++/* LCD.CTRLF bit masks and bit positions */
++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */
++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */
++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */
++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */
++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */
++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */
++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */
++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */
++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */
++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */
++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */
++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */
++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */
++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */
++
++/* LCD.CTRLG bit masks and bit positions */
++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */
++#define LCD_TDG_gp 6 /* Type of Digit group position. */
++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */
++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */
++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */
++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */
++
++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */
++#define LCD_STSEG_gp 0 /* Start Segment group position. */
++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */
++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */
++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */
++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */
++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */
++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */
++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */
++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */
++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */
++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */
++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */
++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */
++
++/* LCD.CTRLH bit masks and bit positions */
++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */
++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */
++
++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */
++#define LCD_DCODE_gp 0 /* Display Code group position. */
++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */
++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */
++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */
++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */
++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */
++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */
++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */
++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */
++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */
++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */
++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */
++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */
++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */
++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 31
++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 32
++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */
++
++/* LCD interrupt vectors */
++#define LCD_INT_vect_num 35
++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 36
++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 37
++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */
++#define NVM_SPM_vect_num 38
++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 39
++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 40
++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 41
++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 42
++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 43
++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 44
++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 48
++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 49
++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */
++
++/* PORTG interrupt vectors */
++#define PORTG_INT0_vect_num 50
++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */
++#define PORTG_INT1_vect_num 51
++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */
++
++/* PORTM interrupt vectors */
++#define PORTM_INT0_vect_num 52
++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */
++#define PORTM_INT1_vect_num 53
++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 54
++#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 55
++#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 58
++#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 58
++#define TCE2_LUNF_vect _VECTOR(58) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 59
++#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 59
++#define TCE2_HUNF_vect _VECTOR(59) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 60
++#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 60
++#define TCE2_LCMPA_vect _VECTOR(60) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 61
++#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 61
++#define TCE2_LCMPB_vect _VECTOR(61) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 62
++#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 62
++#define TCE2_LCMPC_vect _VECTOR(62) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 63
++#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 63
++#define TCE2_LCMPD_vect _VECTOR(63) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 69
++#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 70
++#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 71
++#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 75
++#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 76
++#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 77
++#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 78
++#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 79
++#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 80
++#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (81 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x4D
++
++
++#endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128b3.h avr-libc-1.8.0/include/avr/iox128b3.h
+--- avr-libc-1.8.0.orig/include/avr/iox128b3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128b3.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,6194 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128b3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128B3_H_INCLUDED
++#define _AVR_ATXMEGA128B3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++PR - Power Reduction
++--------------------------------------------------------------------------
++*/
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t reserved_0x04;
++ register8_t PRPE; /* Power Reduction Port E */
++} PR_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */
++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */
++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LCD - LCD Controller
++--------------------------------------------------------------------------
++*/
++
++/* LCD Controller */
++typedef struct LCD_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t INTCTRL; /* Interrupt Enable Register */
++ register8_t INTFLAG; /* Interrupt Flag Register */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t CTRLH; /* Control Register H */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t DATA0; /* LCD Data Register 0 */
++ register8_t DATA1; /* LCD Data Register 1 */
++ register8_t DATA2; /* LCD Data Register 2 */
++ register8_t DATA3; /* LCD Data Register 3 */
++ register8_t DATA4; /* LCD Data Register 4 */
++ register8_t DATA5; /* LCD Data Register 5 */
++ register8_t DATA6; /* LCD Data Register 6 */
++ register8_t DATA7; /* LCD Data Register 7 */
++ register8_t DATA8; /* LCD Data Register 8 */
++ register8_t DATA9; /* LCD Data Register 9 */
++ register8_t DATA10; /* LCD Data Register 10 */
++ register8_t DATA11; /* LCD Data Register 11 */
++ register8_t DATA12; /* LCD Data Register 12 */
++ register8_t DATA13; /* LCD Data Register 13 */
++ register8_t DATA14; /* LCD Data Register 14 */
++ register8_t DATA15; /* LCD Data Register 15 */
++ register8_t DATA16; /* LCD Data Register 16 */
++ register8_t DATA17; /* LCD Data Register 17 */
++ register8_t DATA18; /* LCD Data Register 18 */
++ register8_t DATA19; /* LCD Data Register 19 */
++} LCD_t;
++
++/* LCD Blink Rate */
++typedef enum LCD_BLINKRATE_enum
++{
++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */
++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */
++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */
++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */
++} LCD_BLINKRATE_t;
++
++/* LCD Clock Divide */
++typedef enum LCD_CLKDIV_enum
++{
++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */
++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */
++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */
++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */
++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */
++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */
++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */
++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */
++} LCD_CLKDIV_t;
++
++/* Duty Select */
++typedef enum LCD_DUTY_enum
++{
++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */
++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */
++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */
++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */
++} LCD_DUTY_t;
++
++/* LCD Prescaler Select */
++typedef enum LCD_PRESC_enum
++{
++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */
++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */
++} LCD_PRESC_t;
++
++/* Type of Digit */
++typedef enum LCD_TDG_enum
++{
++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */
++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */
++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */
++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */
++} LCD_TDG_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */
++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPE _SFR_MEM8(0x0075)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM8(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++#define ACB_CURRCTRL _SFR_MEM8(0x0398)
++#define ACB_CURRCALIB _SFR_MEM8(0x0399)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTG_DIR _SFR_MEM8(0x06C0)
++#define PORTG_DIRSET _SFR_MEM8(0x06C1)
++#define PORTG_DIRCLR _SFR_MEM8(0x06C2)
++#define PORTG_DIRTGL _SFR_MEM8(0x06C3)
++#define PORTG_OUT _SFR_MEM8(0x06C4)
++#define PORTG_OUTSET _SFR_MEM8(0x06C5)
++#define PORTG_OUTCLR _SFR_MEM8(0x06C6)
++#define PORTG_OUTTGL _SFR_MEM8(0x06C7)
++#define PORTG_IN _SFR_MEM8(0x06C8)
++#define PORTG_INTCTRL _SFR_MEM8(0x06C9)
++#define PORTG_INT0MASK _SFR_MEM8(0x06CA)
++#define PORTG_INT1MASK _SFR_MEM8(0x06CB)
++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC)
++#define PORTG_REMAP _SFR_MEM8(0x06CE)
++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0)
++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1)
++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2)
++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3)
++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4)
++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5)
++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6)
++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7)
++
++/* PORT - I/O Ports */
++#define PORTM_DIR _SFR_MEM8(0x0760)
++#define PORTM_DIRSET _SFR_MEM8(0x0761)
++#define PORTM_DIRCLR _SFR_MEM8(0x0762)
++#define PORTM_DIRTGL _SFR_MEM8(0x0763)
++#define PORTM_OUT _SFR_MEM8(0x0764)
++#define PORTM_OUTSET _SFR_MEM8(0x0765)
++#define PORTM_OUTCLR _SFR_MEM8(0x0766)
++#define PORTM_OUTTGL _SFR_MEM8(0x0767)
++#define PORTM_IN _SFR_MEM8(0x0768)
++#define PORTM_INTCTRL _SFR_MEM8(0x0769)
++#define PORTM_INT0MASK _SFR_MEM8(0x076A)
++#define PORTM_INT1MASK _SFR_MEM8(0x076B)
++#define PORTM_INTFLAGS _SFR_MEM8(0x076C)
++#define PORTM_REMAP _SFR_MEM8(0x076E)
++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770)
++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771)
++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772)
++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773)
++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774)
++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775)
++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776)
++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* LCD - LCD Controller */
++#define LCD_CTRLA _SFR_MEM8(0x0D00)
++#define LCD_CTRLB _SFR_MEM8(0x0D01)
++#define LCD_CTRLC _SFR_MEM8(0x0D02)
++#define LCD_INTCTRL _SFR_MEM8(0x0D03)
++#define LCD_INTFLAG _SFR_MEM8(0x0D04)
++#define LCD_CTRLD _SFR_MEM8(0x0D05)
++#define LCD_CTRLE _SFR_MEM8(0x0D06)
++#define LCD_CTRLF _SFR_MEM8(0x0D07)
++#define LCD_CTRLG _SFR_MEM8(0x0D08)
++#define LCD_CTRLH _SFR_MEM8(0x0D09)
++#define LCD_DATA0 _SFR_MEM8(0x0D10)
++#define LCD_DATA1 _SFR_MEM8(0x0D11)
++#define LCD_DATA2 _SFR_MEM8(0x0D12)
++#define LCD_DATA3 _SFR_MEM8(0x0D13)
++#define LCD_DATA4 _SFR_MEM8(0x0D14)
++#define LCD_DATA5 _SFR_MEM8(0x0D15)
++#define LCD_DATA6 _SFR_MEM8(0x0D16)
++#define LCD_DATA7 _SFR_MEM8(0x0D17)
++#define LCD_DATA8 _SFR_MEM8(0x0D18)
++#define LCD_DATA9 _SFR_MEM8(0x0D19)
++#define LCD_DATA10 _SFR_MEM8(0x0D1A)
++#define LCD_DATA11 _SFR_MEM8(0x0D1B)
++#define LCD_DATA12 _SFR_MEM8(0x0D1C)
++#define LCD_DATA13 _SFR_MEM8(0x0D1D)
++#define LCD_DATA14 _SFR_MEM8(0x0D1E)
++#define LCD_DATA15 _SFR_MEM8(0x0D1F)
++#define LCD_DATA16 _SFR_MEM8(0x0D20)
++#define LCD_DATA17 _SFR_MEM8(0x0D21)
++#define LCD_DATA18 _SFR_MEM8(0x0D22)
++#define LCD_DATA19 _SFR_MEM8(0x0D23)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* PR - Power Reduction */
++/* PR.PRGEN bit masks and bit positions */
++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */
++#define PR_LCD_bp 7 /* LCD Module bit position. */
++
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */
++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */
++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */
++
++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */
++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */
++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* LCD - LCD Controller */
++/* LCD.CTRLA bit masks and bit positions */
++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */
++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */
++
++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */
++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */
++
++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */
++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */
++
++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */
++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */
++
++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */
++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */
++
++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */
++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */
++
++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */
++#define LCD_SEGON_bp 1 /* Segments On bit position. */
++
++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */
++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */
++
++/* LCD.CTRLB bit masks and bit positions */
++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */
++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */
++
++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */
++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */
++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */
++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */
++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */
++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */
++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */
++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */
++
++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */
++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */
++
++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */
++#define LCD_DUTY_gp 0 /* Duty Select group position. */
++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */
++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */
++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */
++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */
++
++/* LCD.CTRLC bit masks and bit positions */
++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */
++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */
++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */
++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */
++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */
++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */
++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */
++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */
++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */
++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */
++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */
++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */
++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */
++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */
++
++/* LCD.INTCTRL bit masks and bit positions */
++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */
++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */
++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */
++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */
++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */
++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */
++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */
++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */
++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */
++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */
++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */
++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */
++
++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */
++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* LCD.INTFLAG bit masks and bit positions */
++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */
++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */
++
++/* LCD.CTRLD bit masks and bit positions */
++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */
++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */
++
++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */
++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */
++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */
++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */
++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */
++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */
++
++/* LCD.CTRLE bit masks and bit positions */
++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */
++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */
++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */
++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */
++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */
++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */
++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */
++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */
++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */
++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */
++
++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */
++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */
++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */
++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */
++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */
++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */
++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */
++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */
++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */
++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */
++
++/* LCD.CTRLF bit masks and bit positions */
++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */
++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */
++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */
++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */
++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */
++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */
++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */
++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */
++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */
++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */
++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */
++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */
++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */
++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */
++
++/* LCD.CTRLG bit masks and bit positions */
++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */
++#define LCD_TDG_gp 6 /* Type of Digit group position. */
++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */
++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */
++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */
++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */
++
++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */
++#define LCD_STSEG_gp 0 /* Start Segment group position. */
++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */
++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */
++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */
++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */
++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */
++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */
++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */
++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */
++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */
++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */
++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */
++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */
++
++/* LCD.CTRLH bit masks and bit positions */
++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */
++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */
++
++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */
++#define LCD_DCODE_gp 0 /* Display Code group position. */
++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */
++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */
++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */
++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */
++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */
++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */
++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */
++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */
++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */
++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */
++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */
++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */
++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */
++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 31
++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 32
++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */
++
++/* LCD interrupt vectors */
++#define LCD_INT_vect_num 35
++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 36
++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 37
++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */
++#define NVM_SPM_vect_num 38
++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 39
++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 40
++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 41
++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 42
++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 43
++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 44
++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 48
++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 49
++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */
++
++/* PORTG interrupt vectors */
++#define PORTG_INT0_vect_num 50
++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */
++#define PORTG_INT1_vect_num 51
++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */
++
++/* PORTM interrupt vectors */
++#define PORTM_INT0_vect_num 52
++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */
++#define PORTM_INT1_vect_num 53
++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (54 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x4B
++
++
++#endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128c3.h avr-libc-1.8.0/include/avr/iox128c3.h
+--- avr-libc-1.8.0.orig/include/avr/iox128c3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128c3.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,6145 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128c3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128C3_H_INCLUDED
++#define _AVR_ATXMEGA128C3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x52
++
++
++#endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox128d4.h avr-libc-1.8.0/include/avr/iox128d4.h
+--- avr-libc-1.8.0.orig/include/avr/iox128d4.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox128d4.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,5444 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox128d4.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA128D4_H_INCLUDED
++#define _AVR_ATXMEGA128D4_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (139264)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (131072)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (8192)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x47
++
++
++#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox16a4u.h avr-libc-1.8.0/include/avr/iox16a4u.h
+--- avr-libc-1.8.0.orig/include/avr/iox16a4u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox16a4u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7200 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox16a4u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA16A4U_H_INCLUDED
++#define _AVR_ATXMEGA16A4U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (20480)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (16384)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x4000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (10240)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (1024)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (2048)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (1024)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x41
++
++
++#endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox16c4.h avr-libc-1.8.0/include/avr/iox16c4.h
+--- avr-libc-1.8.0.orig/include/avr/iox16c4.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox16c4.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,5959 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox16c4.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA16C4_H_INCLUDED
++#define _AVR_ATXMEGA16C4_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (20480)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (16384)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x4000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (10240)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (1024)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (2048)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (1024)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x43
++
++
++#endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox192a3u.h avr-libc-1.8.0/include/avr/iox192a3u.h
+--- avr-libc-1.8.0.orig/include/avr/iox192a3u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox192a3u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7588 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox192a3u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA192A3U_H_INCLUDED
++#define _AVR_ATXMEGA192A3U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CH1RES _SFR_MEM16(0x0252)
++#define ADCB_CH2RES _SFR_MEM16(0x0254)
++#define ADCB_CH3RES _SFR_MEM16(0x0256)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
++#define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
++#define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
++#define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCE1_CTRLA _SFR_MEM8(0x0A40)
++#define TCE1_CTRLB _SFR_MEM8(0x0A41)
++#define TCE1_CTRLC _SFR_MEM8(0x0A42)
++#define TCE1_CTRLD _SFR_MEM8(0x0A43)
++#define TCE1_CTRLE _SFR_MEM8(0x0A44)
++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
++#define TCE1_TEMP _SFR_MEM8(0x0A4F)
++#define TCE1_CNT _SFR_MEM16(0x0A60)
++#define TCE1_PER _SFR_MEM16(0x0A66)
++#define TCE1_CCA _SFR_MEM16(0x0A68)
++#define TCE1_CCB _SFR_MEM16(0x0A6A)
++#define TCE1_PERBUF _SFR_MEM16(0x0A76)
++#define TCE1_CCABUF _SFR_MEM16(0x0A78)
++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXE_CTRL _SFR_MEM8(0x0A80)
++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
++#define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
++#define AWEXE_DTLS _SFR_MEM8(0x0A88)
++#define AWEXE_DTHS _SFR_MEM8(0x0A89)
++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1_DATA _SFR_MEM8(0x0AB0)
++#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIE_CTRL _SFR_MEM8(0x0AC0)
++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
++#define SPIE_STATUS _SFR_MEM8(0x0AC2)
++#define SPIE_DATA _SFR_MEM8(0x0AC3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 36
++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 37
++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 38
++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 39
++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
++#define ADCB_CH1_vect_num 40
++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
++#define ADCB_CH2_vect_num 41
++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
++#define ADCB_CH3_vect_num 42
++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* TCE1 interrupt vectors */
++#define TCE1_OVF_vect_num 53
++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
++#define TCE1_ERR_vect_num 54
++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
++#define TCE1_CCA_vect_num 55
++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
++#define TCE1_CCB_vect_num 56
++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
++
++/* SPIE interrupt vectors */
++#define SPIE_INT_vect_num 57
++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* USARTE1 interrupt vectors */
++#define USARTE1_RXC_vect_num 61
++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
++#define USARTE1_DRE_vect_num 62
++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
++#define USARTE1_TXC_vect_num 63
++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USARTF0 interrupt vectors */
++#define USARTF0_RXC_vect_num 119
++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
++#define USARTF0_DRE_vect_num 120
++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
++#define USARTF0_TXC_vect_num 121
++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (204800)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (196608)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x2E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x30000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (24576)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (16384)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x44
++
++
++#endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox192c3.h avr-libc-1.8.0/include/avr/iox192c3.h
+--- avr-libc-1.8.0.orig/include/avr/iox192c3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox192c3.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,6145 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox192c3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA192C3_H_INCLUDED
++#define _AVR_ATXMEGA192C3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (204800)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (196608)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x2E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x30000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (16384)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (16384)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x97
++#define SIGNATURE_2 0x51
++
++
++#endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox256a3bu.h avr-libc-1.8.0/include/avr/iox256a3bu.h
+--- avr-libc-1.8.0.orig/include/avr/iox256a3bu.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox256a3bu.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7597 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox256a3bu.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA256A3BU_H_INCLUDED
++#define _AVR_ATXMEGA256A3BU_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++VBAT - Battery Backup Module
++--------------------------------------------------------------------------
++*/
++
++/* Battery Backup Module */
++typedef struct VBAT_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t BACKUP0; /* Backup Register 0 */
++ register8_t BACKUP1; /* Backup Register 1 */
++} VBAT_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC32 - 32-bit Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* 32-bit Real-Time Counter */
++typedef struct RTC32_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t SYNCCTRL; /* Synchronization Control/Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _DWORDREGISTER(CNT); /* Count Register */
++ _DWORDREGISTER(PER); /* Period Register */
++ _DWORDREGISTER(COMP); /* Compare Register */
++} RTC32_t;
++
++/* Compare Interrupt level */
++typedef enum RTC32_COMPINTLVL_enum
++{
++ RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC32_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC32_OVFINTLVL_enum
++{
++ RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC32_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define VBAT (*(VBAT_t *) 0x00F0) /* Battery Backup Module */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* VBAT - Battery Backup Module */
++#define VBAT_CTRL _SFR_MEM8(0x00F0)
++#define VBAT_STATUS _SFR_MEM8(0x00F1)
++#define VBAT_BACKUP0 _SFR_MEM8(0x00F2)
++#define VBAT_BACKUP1 _SFR_MEM8(0x00F3)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CH1RES _SFR_MEM16(0x0252)
++#define ADCB_CH2RES _SFR_MEM16(0x0254)
++#define ADCB_CH3RES _SFR_MEM16(0x0256)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
++#define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
++#define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
++#define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++
++/* RTC32 - 32-bit Real-Time Counter */
++#define RTC32_CTRL _SFR_MEM8(0x0420)
++#define RTC32_SYNCCTRL _SFR_MEM8(0x0421)
++#define RTC32_INTCTRL _SFR_MEM8(0x0422)
++#define RTC32_INTFLAGS _SFR_MEM8(0x0423)
++#define RTC32_CNT _SFR_MEM32(0x0424)
++#define RTC32_PER _SFR_MEM32(0x0428)
++#define RTC32_COMP _SFR_MEM32(0x042C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCE1_CTRLA _SFR_MEM8(0x0A40)
++#define TCE1_CTRLB _SFR_MEM8(0x0A41)
++#define TCE1_CTRLC _SFR_MEM8(0x0A42)
++#define TCE1_CTRLD _SFR_MEM8(0x0A43)
++#define TCE1_CTRLE _SFR_MEM8(0x0A44)
++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
++#define TCE1_TEMP _SFR_MEM8(0x0A4F)
++#define TCE1_CNT _SFR_MEM16(0x0A60)
++#define TCE1_PER _SFR_MEM16(0x0A66)
++#define TCE1_CCA _SFR_MEM16(0x0A68)
++#define TCE1_CCB _SFR_MEM16(0x0A6A)
++#define TCE1_PERBUF _SFR_MEM16(0x0A76)
++#define TCE1_CCABUF _SFR_MEM16(0x0A78)
++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXE_CTRL _SFR_MEM8(0x0A80)
++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
++#define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
++#define AWEXE_DTLS _SFR_MEM8(0x0A88)
++#define AWEXE_DTHS _SFR_MEM8(0x0A89)
++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* VBAT - Battery Backup Module */
++/* VBAT.CTRL bit masks and bit positions */
++#define VBAT_HIGHESR_bm 0x20 /* 32-kHz Crystal Oscillator High Power Mode bit mask. */
++#define VBAT_HIGHESR_bp 5 /* 32-kHz Crystal Oscillator High Power Mode bit position. */
++
++#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */
++#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */
++
++#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */
++#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */
++
++#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */
++#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */
++
++#define VBAT_ACCEN_bm 0x02 /* Access Enable bit mask. */
++#define VBAT_ACCEN_bp 1 /* Access Enable bit position. */
++
++#define VBAT_RESET_bm 0x01 /* Reset bit mask. */
++#define VBAT_RESET_bp 0 /* Reset bit position. */
++
++/* VBAT.STATUS bit masks and bit positions */
++#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */
++#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */
++
++#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */
++#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */
++
++#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */
++#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */
++
++#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */
++#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */
++
++#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */
++#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC32 - 32-bit Real-Time Counter */
++/* RTC32.CTRL bit masks and bit positions */
++#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */
++#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */
++
++/* RTC32.SYNCCTRL bit masks and bit positions */
++#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */
++#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */
++
++#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC32.INTCTRL bit masks and bit positions */
++#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC32.INTFLAGS bit masks and bit positions */
++#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC32 interrupt vectors */
++#define RTC32_OVF_vect_num 10
++#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC32_COMP_vect_num 11
++#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 36
++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 37
++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 38
++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 39
++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
++#define ADCB_CH1_vect_num 40
++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
++#define ADCB_CH2_vect_num 41
++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
++#define ADCB_CH3_vect_num 42
++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* TCE1 interrupt vectors */
++#define TCE1_OVF_vect_num 53
++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
++#define TCE1_ERR_vect_num 54
++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
++#define TCE1_CCA_vect_num 55
++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
++#define TCE1_CCB_vect_num 56
++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USARTF0 interrupt vectors */
++#define USARTF0_RXC_vect_num 119
++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
++#define USARTF0_DRE_vect_num 120
++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
++#define USARTF0_TXC_vect_num 121
++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (270336)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (262144)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x40000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (24576)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (4096)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (16384)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (4096)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x98
++#define SIGNATURE_2 0x43
++
++
++#endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox256a3u.h avr-libc-1.8.0/include/avr/iox256a3u.h
+--- avr-libc-1.8.0.orig/include/avr/iox256a3u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox256a3u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7588 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox256a3u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA256A3U_H_INCLUDED
++#define _AVR_ATXMEGA256A3U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CH1RES _SFR_MEM16(0x0252)
++#define ADCB_CH2RES _SFR_MEM16(0x0254)
++#define ADCB_CH3RES _SFR_MEM16(0x0256)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
++#define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
++#define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
++#define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCE1_CTRLA _SFR_MEM8(0x0A40)
++#define TCE1_CTRLB _SFR_MEM8(0x0A41)
++#define TCE1_CTRLC _SFR_MEM8(0x0A42)
++#define TCE1_CTRLD _SFR_MEM8(0x0A43)
++#define TCE1_CTRLE _SFR_MEM8(0x0A44)
++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
++#define TCE1_TEMP _SFR_MEM8(0x0A4F)
++#define TCE1_CNT _SFR_MEM16(0x0A60)
++#define TCE1_PER _SFR_MEM16(0x0A66)
++#define TCE1_CCA _SFR_MEM16(0x0A68)
++#define TCE1_CCB _SFR_MEM16(0x0A6A)
++#define TCE1_PERBUF _SFR_MEM16(0x0A76)
++#define TCE1_CCABUF _SFR_MEM16(0x0A78)
++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXE_CTRL _SFR_MEM8(0x0A80)
++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
++#define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
++#define AWEXE_DTLS _SFR_MEM8(0x0A88)
++#define AWEXE_DTHS _SFR_MEM8(0x0A89)
++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1_DATA _SFR_MEM8(0x0AB0)
++#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIE_CTRL _SFR_MEM8(0x0AC0)
++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
++#define SPIE_STATUS _SFR_MEM8(0x0AC2)
++#define SPIE_DATA _SFR_MEM8(0x0AC3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 36
++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 37
++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 38
++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 39
++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
++#define ADCB_CH1_vect_num 40
++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
++#define ADCB_CH2_vect_num 41
++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
++#define ADCB_CH3_vect_num 42
++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* TCE1 interrupt vectors */
++#define TCE1_OVF_vect_num 53
++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
++#define TCE1_ERR_vect_num 54
++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
++#define TCE1_CCA_vect_num 55
++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
++#define TCE1_CCB_vect_num 56
++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
++
++/* SPIE interrupt vectors */
++#define SPIE_INT_vect_num 57
++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* USARTE1 interrupt vectors */
++#define USARTE1_RXC_vect_num 61
++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
++#define USARTE1_DRE_vect_num 62
++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
++#define USARTE1_TXC_vect_num 63
++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USARTF0 interrupt vectors */
++#define USARTF0_RXC_vect_num 119
++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
++#define USARTF0_DRE_vect_num 120
++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
++#define USARTF0_TXC_vect_num 121
++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (270336)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (262144)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x40000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (24576)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (4096)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (16384)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (4096)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x98
++#define SIGNATURE_2 0x42
++
++
++#endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox256c3.h avr-libc-1.8.0/include/avr/iox256c3.h
+--- avr-libc-1.8.0.orig/include/avr/iox256c3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox256c3.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,6145 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox256c3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA256C3_H_INCLUDED
++#define _AVR_ATXMEGA256C3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (270336)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (262144)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x40000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (24576)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (4096)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (16384)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (4096)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x98
++#define SIGNATURE_2 0x46
++
++
++#endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox32a4u.h avr-libc-1.8.0/include/avr/iox32a4u.h
+--- avr-libc-1.8.0.orig/include/avr/iox32a4u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox32a4u.h 2013-01-18 09:50:26.000000000 +0100
+@@ -0,0 +1,7200 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox32a4u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA32A4U_H_INCLUDED
++#define _AVR_ATXMEGA32A4U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (36864)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (32768)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x7000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x8000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (1024)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (1024)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x41
++
++
++#endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox32c4.h avr-libc-1.8.0/include/avr/iox32c4.h
+--- avr-libc-1.8.0.orig/include/avr/iox32c4.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox32c4.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,5959 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox32c4.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA32C4_H_INCLUDED
++#define _AVR_ATXMEGA32C4_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (36864)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (32768)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x7000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x8000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (1024)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (1024)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x44
++
++
++#endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox384c3.h avr-libc-1.8.0/include/avr/iox384c3.h
+--- avr-libc-1.8.0.orig/include/avr/iox384c3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox384c3.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,6693 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox384c3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA384C3_H_INCLUDED
++#define _AVR_ATXMEGA384C3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH01_gc = (0x01<<0), /* Channel 0 > channel 1 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM8(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */
++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */
++
++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */
++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (401408)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (393216)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x5E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x60000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (40960)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (4096)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (32768)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (4096)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x98
++#define SIGNATURE_2 0x45
++
++
++#endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox384d3.h avr-libc-1.8.0/include/avr/iox384d3.h
+--- avr-libc-1.8.0.orig/include/avr/iox384d3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox384d3.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,5705 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox384d3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA384D3_H_INCLUDED
++#define _AVR_ATXMEGA384D3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (401408)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (393216)
++#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x5E000)
++#define APPTABLE_SECTION_SIZE (8192)
++#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x60000)
++#define BOOT_SECTION_SIZE (8192)
++#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (40960)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (4096)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (32768)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (4096)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (512)
++#define USER_SIGNATURES_PAGE_SIZE (512)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (512)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 512
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x98
++#define SIGNATURE_2 0x47
++
++
++#endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64a1u.h avr-libc-1.8.0/include/avr/iox64a1u.h
+--- avr-libc-1.8.0.orig/include/avr/iox64a1u.h 2011-12-29 09:51:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64a1u.h 2013-01-18 09:50:27.000000000 +0100
+@@ -1,38 +1,36 @@
+-/* Copyright (c) 2010 Atmel Corporation
+- All rights reserved.
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
+
+- Redistribution and use in source and binary forms, with or without
+- modification, are permitted provided that the following conditions are met:
+-
+- * Redistributions of source code must retain the above copyright
+- notice, this list of conditions and the following disclaimer.
+-
+- * Redistributions in binary form must reproduce the above copyright
+- notice, this list of conditions and the following disclaimer in
+- the documentation and/or other materials provided with the
+- distribution.
+-
+- * Neither the name of the copyright holders nor the names of
+- contributors may be used to endorse or promote products derived
+- from this software without specific prior written permission.
+-
+- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- POSSIBILITY OF SUCH DAMAGE. */
+-
+-/* $Id$ */
+-
+-/* avr/iox64a1u.h - definitions for ATxmega64A1U */
+-
+-/* This file should only be included from <avr/io.h>, never directly. */
+
+ #ifndef _AVR_IO_H_
+ # error "Include <avr/io.h> instead of this file."
+@@ -42,12 +40,10 @@
+ # define _AVR_IOXXX_H_ "iox64a1u.h"
+ #else
+ # error "Attempt to include more than one <avr/ioXXX.h> file."
+-#endif
+-
+-
+-#ifndef _AVR_ATxmega64A1U_H_
+-#define _AVR_ATxmega64A1U_H_ 1
++#endif
+
++#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED
++#define _AVR_ATXMEGA64A1U_H_INCLUDED
+
+ /* Ungrouped common registers */
+ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+@@ -67,6 +63,24 @@
+ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
+ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+@@ -77,7 +91,6 @@
+ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+ #define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+-
+ /* C Language Only */
+ #if !defined (__ASSEMBLER__)
+
+@@ -156,6 +169,12 @@
+ } OCD_t;
+
+
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
+ /* CCP signatures */
+ typedef enum CCP_enum
+ {
+@@ -180,11 +199,6 @@
+ register8_t USBCTRL; /* USB Control Register */
+ } CLK_t;
+
+-/*
+---------------------------------------------------------------------------
+-CLK - Clock System
+---------------------------------------------------------------------------
+-*/
+
+ /* Power Reduction */
+ typedef struct PR_struct
+@@ -258,6 +272,7 @@
+ typedef enum CLK_USBSRC_enum
+ {
+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
+ } CLK_USBSRC_t;
+
+
+@@ -298,7 +313,7 @@
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
+- register8_t PLLCTRL; /* PLL Control REgister */
++ register8_t PLLCTRL; /* PLL Control Register */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+ } OSC_t;
+
+@@ -329,11 +344,19 @@
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+ } OSC_PLLSRC_t;
+
+-/* 32 MHz Calibration Reference */
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
+ typedef enum OSC_RC32MCREF_enum
+ {
+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
+- OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
+ } OSC_RC32MCREF_t;
+
+
+@@ -471,6 +494,8 @@
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
+ } PORTCFG_t;
+
+ /* Virtual Port Mapping */
+@@ -541,6 +566,26 @@
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+ } PORTCFG_EVOUT_t;
+
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
+
+ /*
+ --------------------------------------------------------------------------
+@@ -577,16 +622,17 @@
+ /* Cyclic Redundancy Checker */
+ typedef struct CRC_struct
+ {
+- register8_t CTRL; /* CRC Control Register */
+- register8_t STATUS; /* CRC Status Register */
+- register8_t DATAIN; /* CRC Data Input */
+- register8_t CHECKSUM0; /* CRC Checksum byte 0 */
+- register8_t CHECKSUM1; /* CRC Checksum byte 1 */
+- register8_t CHECKSUM2; /* CRC Checksum byte 2 */
+- register8_t CHECKSUM3; /* CRC Checksum byte 3 */
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
+ } CRC_t;
+
+-/* CRC Reset */
++/* Reset */
+ typedef enum CRC_RESET_enum
+ {
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+@@ -594,10 +640,10 @@
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+ } CRC_RESET_t;
+
+-/* CRC Input Source */
++/* Input Source */
+ typedef enum CRC_SOURCE_enum
+ {
+- CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+@@ -633,11 +679,6 @@
+ register8_t reserved_0x0F;
+ } DMA_CH_t;
+
+-/*
+---------------------------------------------------------------------------
+-DMA - DMA Controller
+---------------------------------------------------------------------------
+-*/
+
+ /* DMA Controller */
+ typedef struct DMA_struct
+@@ -1037,8 +1078,8 @@
+ typedef enum NVM_CMD_enum
+ {
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+- NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+@@ -1062,13 +1103,14 @@
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
+- NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
+ } NVM_CMD_t;
+
+ /* SPM ready interrupt level */
+@@ -1092,36 +1134,36 @@
+ /* Boot lock bits - boot setcion */
+ typedef enum NVM_BLBB_enum
+ {
+- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ } NVM_BLBB_t;
+
+ /* Boot lock bits - application section */
+ typedef enum NVM_BLBA_enum
+ {
+- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ } NVM_BLBA_t;
+
+ /* Boot lock bits - application table section */
+ typedef enum NVM_BLBAT_enum
+ {
+- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ } NVM_BLBAT_t;
+
+ /* Lock bits */
+ typedef enum NVM_LB_enum
+ {
+- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ } NVM_LB_t;
+
+
+@@ -1136,17 +1178,13 @@
+ {
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+- register8_t INTCTRL; /* Channel Interrupt Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+- register8_t reserved_0x7;
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
+ } ADC_CH_t;
+
+-/*
+---------------------------------------------------------------------------
+-ADC - Analog/Digital Converter
+---------------------------------------------------------------------------
+-*/
+
+ /* Analog-to-Digital Converter */
+ typedef struct ADC_struct
+@@ -1158,7 +1196,7 @@
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t reserved_0x05;
+ register8_t INTFLAGS; /* Interrupt Flags */
+- register8_t TEMP; /* Temporary register */
++ register8_t TEMP; /* Temporary Register */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+@@ -1245,7 +1283,7 @@
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+- ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
+ } ADC_CH_GAIN_t;
+
+ /* Conversion result resolution */
+@@ -1257,13 +1295,13 @@
+ } ADC_RESOLUTION_t;
+
+ /* Current Limitation Mode */
+-typedef enum ADC_CURRENT_enum
++typedef enum ADC_CURRLIMIT_enum
+ {
+- ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */
+- ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */
+- ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
+- ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */
+-} ADC_CURRENT_t;
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
+
+ /* Voltage reference selection */
+ typedef enum ADC_REFSEL_enum
+@@ -1440,7 +1478,7 @@
+ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
+ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
+ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
+- DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
+ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
+ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
+ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
+@@ -1548,7 +1586,7 @@
+
+ /*
+ --------------------------------------------------------------------------
+-RTC - Real-Time Clounter
++RTC - Real-Time Counter
+ --------------------------------------------------------------------------
+ */
+
+@@ -1614,11 +1652,6 @@
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+ } EBI_CS_t;
+
+-/*
+---------------------------------------------------------------------------
+-EBI - External Bus Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* External Bus Interface */
+ typedef struct EBI_struct
+@@ -1644,28 +1677,28 @@
+ } EBI_t;
+
+ /* Chip Select adress space */
+-typedef enum EBI_CS_ASIZE_enum
++typedef enum EBI_CS_ASPACE_enum
+ {
+- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */
+- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */
+- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */
+- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */
+- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */
+- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */
+- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */
+- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */
+- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */
+- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */
+- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */
+- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */
+- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */
+- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */
+- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */
+- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */
+- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */
+-} EBI_CS_ASIZE_t;
++ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
++ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
++ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
++ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
++ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
++ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
++ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
++ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
++ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
++ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
++ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
++ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
++ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
++ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
++ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
++ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
++ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
++} EBI_CS_ASPACE_t;
+
+-/* */
++/* SRAM Wait State Selection */
+ typedef enum EBI_CS_SRWS_enum
+ {
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1673,7 +1706,7 @@
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_CS_SRWS_t;
+@@ -1735,7 +1768,7 @@
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+ } EBI_SDCOL_t;
+
+-/* */
++/* SDRAM Load Mode to Active delay */
+ typedef enum EBI_MRDLY_enum
+ {
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+@@ -1744,7 +1777,7 @@
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+ } EBI_MRDLY_t;
+
+-/* */
++/* SDRAM Row Cycle Delay */
+ typedef enum EBI_ROWCYCDLY_enum
+ {
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+@@ -1752,12 +1785,12 @@
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+ } EBI_ROWCYCDLY_t;
+
+-/* */
++/* SDRAM Row to Precharge Delay */
+ typedef enum EBI_RPDLY_enum
+ {
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1765,12 +1798,12 @@
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_RPDLY_t;
+
+-/* */
++/* SDRAM Write Recovery Delay */
+ typedef enum EBI_WRDLY_enum
+ {
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+@@ -1779,7 +1812,7 @@
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+ } EBI_WRDLY_t;
+
+-/* */
++/* SDRAM Exit Self Refresh to Active Delay */
+ typedef enum EBI_ESRDLY_enum
+ {
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+@@ -1787,12 +1820,12 @@
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+ } EBI_ESRDLY_t;
+
+-/* */
++/* SDRAM Row to Column Delay */
+ typedef enum EBI_ROWCOLDLY_enum
+ {
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+@@ -1800,7 +1833,7 @@
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+ } EBI_ROWCOLDLY_t;
+@@ -1824,11 +1857,6 @@
+ register8_t DATA; /* Data Register */
+ } TWI_MASTER_t;
+
+-/*
+---------------------------------------------------------------------------
+-TWI - Two-Wire Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* */
+ typedef struct TWI_SLAVE_struct
+@@ -1841,11 +1869,6 @@
+ register8_t ADDRMASK; /* Address Mask Register */
+ } TWI_SLAVE_t;
+
+-/*
+---------------------------------------------------------------------------
+-TWI - Two-Wire Interface
+---------------------------------------------------------------------------
+-*/
+
+ /* Two-Wire Interface */
+ typedef struct TWI_struct
+@@ -1911,7 +1934,7 @@
+
+ /*
+ --------------------------------------------------------------------------
+-USB - USB Module
++USB - USB
+ --------------------------------------------------------------------------
+ */
+
+@@ -1920,66 +1943,13 @@
+ {
+ register8_t STATUS; /* Endpoint Status */
+ register8_t CTRL; /* Endpoint Control */
+- register8_t CNTL; /* USB Endpoint Counter Low Byte */
+- register8_t CNTH; /* USB Endpoint Counter High Byte */
+- register8_t DATAPTRL; /* Data Pointer Low Byte */
+- register8_t DATAPTRH; /* Data Pointer High Byte */
+- register8_t AUXDATAL; /* Auxiliary Data Low Byte */
+- register8_t AUXDATAH; /* Auxiliary Data High Byte */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
+ } USB_EP_t;
+
+-/*
+---------------------------------------------------------------------------
+-USB - USB Module
+---------------------------------------------------------------------------
+-*/
+-
+-/* USB Endpoint table */
+-typedef struct USB_EP_TABLE_struct
+-{
+- USB_EP_t EP0OUT; /* USB Endpoint 0 Output */
+- USB_EP_t EP0IN; /* USB Endpoint 0 Input */
+- USB_EP_t EP1OUT; /* USB Endpoint 1 Output */
+- USB_EP_t EP1IN; /* USB Endpoint 1 Input */
+- USB_EP_t EP2OUT; /* USB Endpoint 2 Output */
+- USB_EP_t EP2IN; /* USB Endpoint 2 Input */
+- USB_EP_t EP3OUT; /* USB Endpoint 3 Output */
+- USB_EP_t EP3IN; /* USB Endpoint 3 Input */
+- USB_EP_t EP4OUT; /* USB Endpoint 4 Output */
+- USB_EP_t EP4IN; /* USB Endpoint 4 Input */
+- USB_EP_t EP5OUT; /* USB Endpoint 5 Output */
+- USB_EP_t EP5IN; /* USB Endpoint 5 Input */
+- USB_EP_t EP6OUT; /* USB Endpoint 6 Output */
+- USB_EP_t EP6IN; /* USB Endpoint 6 Input */
+- USB_EP_t EP7OUT; /* USB Endpoint 7 Output */
+- USB_EP_t EP7IN; /* USB Endpoint 7 Input */
+- USB_EP_t EP8OUT; /* USB Endpoint 8 Output */
+- USB_EP_t EP8IN; /* USB Endpoint 8 Input */
+- USB_EP_t EP9OUT; /* USB Endpoint 9 Output */
+- USB_EP_t EP9IN; /* USB Endpoint 9 Input */
+- USB_EP_t EP10OUT; /* USB Endpoint 10 Output */
+- USB_EP_t EP10IN; /* USB Endpoint 10 Input */
+- USB_EP_t EP11OUT; /* USB Endpoint 11 Output */
+- USB_EP_t EP11IN; /* USB Endpoint 11 Input */
+- USB_EP_t EP12OUT; /* USB Endpoint 12 Output */
+- USB_EP_t EP12IN; /* USB Endpoint 12 Input */
+- USB_EP_t EP13OUT; /* USB Endpoint 13 Output */
+- USB_EP_t EP13IN; /* USB Endpoint 13 Input */
+- USB_EP_t EP14OUT; /* USB Endpoint 14 Output */
+- USB_EP_t EP14IN; /* USB Endpoint 14 Input */
+- USB_EP_t EP15OUT; /* USB Endpoint 15 Output */
+- USB_EP_t EP15IN; /* USB Endpoint 15 Input */
+- register8_t FRAMENUML; /* Frame Number Low Byte */
+- register8_t FRAMENUMH; /* Frame Number High Byte */
+-} USB_EP_TABLE_t;
+-
+-/*
+---------------------------------------------------------------------------
+-USB - USB Module
+---------------------------------------------------------------------------
+-*/
+
+-/* USB Module */
++/* Universal Serial Bus */
+ typedef struct USB_struct
+ {
+ register8_t CTRLA; /* Control Register A */
+@@ -2043,6 +2013,71 @@
+ register8_t CAL1; /* Calibration Byte 1 */
+ } USB_t;
+
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
+ /* USB Endpoint Type */
+ typedef enum USB_EP_TYPE_enum
+ {
+@@ -2052,27 +2087,18 @@
+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
+ } USB_EP_TYPE_t;
+
+-/* USB Endpoint Buffer Size */
+-typedef enum USB_EP_SIZE_enum
+-{
+- USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
+- USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
+- USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
+- USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
+- USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
+- USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
+- USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
+- USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
+-} USB_EP_SIZE_t;
+-
+-/* Interrupt level */
+-typedef enum USB_INTLVL_enum
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
+ {
+- USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+- USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+- USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+- USB_INTLVL_HI_gc = (0x03<<0), /* High Level */
+-} USB_INTLVL_t;
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
+
+
+ /*
+@@ -2098,6 +2124,7 @@
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+@@ -2215,11 +2242,6 @@
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+ } TC0_t;
+
+-/*
+---------------------------------------------------------------------------
+-TC - 16-bit Timer/Counter With PWM
+---------------------------------------------------------------------------
+-*/
+
+ /* 16-bit Timer/Counter 1 */
+ typedef struct TC1_struct
+@@ -2305,12 +2327,24 @@
+ {
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+ } TC_WGMODE_t;
+
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
+ /* Event Action */
+ typedef enum TC_EVACT_enum
+ {
+@@ -2403,6 +2437,165 @@
+
+ /*
+ --------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
+ AWEX - Timer/Counter Advanced Waveform Extension
+ --------------------------------------------------------------------------
+ */
+@@ -2415,7 +2608,7 @@
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+- register8_t reserved_0x05;
++ register8_t STATUSSET; /* Status Set Register */
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+@@ -2604,17 +2797,235 @@
+
+ /*
+ --------------------------------------------------------------------------
+-PRESC - Prescaler
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
+ --------------------------------------------------------------------------
+ */
+
+-/* Prescaler */
+-typedef struct PRESC_struct
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
+ {
+- register8_t PRESCALER; /* Control Register */
+-} PRESC_t;
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
+
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
+
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
+
+ /*
+ ==========================================================================
+@@ -2622,78 +3033,82 @@
+ ==========================================================================
+ */
+
+-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
+ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+ #define CLK (*(CLK_t *) 0x0040) /* Clock System */
+ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
+ #define PR (*(PR_t *) 0x0070) /* Power Reduction */
+-#define RST (*(RST_t *) 0x0078) /* Reset Controller */
++#define RST (*(RST_t *) 0x0078) /* Reset */
+ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
+-#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
+ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
+ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
+-#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */
+-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
+-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
+ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */
+-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+-#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */
+-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
+-#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */
+-#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */
+-#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+-#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+-#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+-#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+-#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+-#define PORTH (*(PORT_t *) 0x06E0) /* Port H */
+-#define PORTJ (*(PORT_t *) 0x0700) /* Port J */
+-#define PORTK (*(PORT_t *) 0x0720) /* Port K */
+-#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */
+-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
+-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */
++#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */
++#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */
++#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
+ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
+-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
+-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
+-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
+-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
+-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
+-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+-#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */
+-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
+-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
+-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
+-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */
+
+
+ #endif /* !defined (__ASSEMBLER__) */
+@@ -2719,25 +3134,89 @@
+ #define GPIO_GPIORE _SFR_MEM8(0x000E)
+ #define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+-/* VPORT0 - Virtual Port 0 */
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
+ #define VPORT0_DIR _SFR_MEM8(0x0010)
+ #define VPORT0_OUT _SFR_MEM8(0x0011)
+ #define VPORT0_IN _SFR_MEM8(0x0012)
+ #define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+-/* VPORT1 - Virtual Port 1 */
++/* VPORT - Virtual Port */
+ #define VPORT1_DIR _SFR_MEM8(0x0014)
+ #define VPORT1_OUT _SFR_MEM8(0x0015)
+ #define VPORT1_IN _SFR_MEM8(0x0016)
+ #define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+-/* VPORT2 - Virtual Port 2 */
++/* VPORT - Virtual Port */
+ #define VPORT2_DIR _SFR_MEM8(0x0018)
+ #define VPORT2_OUT _SFR_MEM8(0x0019)
+ #define VPORT2_IN _SFR_MEM8(0x001A)
+ #define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+-/* VPORT3 - Virtual Port 3 */
++/* VPORT - Virtual Port */
+ #define VPORT3_DIR _SFR_MEM8(0x001C)
+ #define VPORT3_OUT _SFR_MEM8(0x001D)
+ #define VPORT3_IN _SFR_MEM8(0x001E)
+@@ -2747,7 +3226,7 @@
+ #define OCD_OCDR0 _SFR_MEM8(0x002E)
+ #define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+-/* CPU - CPU Registers */
++/* CPU - CPU registers */
+ #define CPU_CCP _SFR_MEM8(0x0034)
+ #define CPU_RAMPD _SFR_MEM8(0x0038)
+ #define CPU_RAMPX _SFR_MEM8(0x0039)
+@@ -2768,16 +3247,16 @@
+ /* SLEEP - Sleep Controller */
+ #define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+-/* OSC - Oscillator Control */
++/* OSC - Oscillator */
+ #define OSC_CTRL _SFR_MEM8(0x0050)
+ #define OSC_STATUS _SFR_MEM8(0x0051)
+ #define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+-#define OSC_XOSCFAIL _SFR_MEM8(0x005F)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+ #define OSC_RC32KCAL _SFR_MEM8(0x0054)
+ #define OSC_PLLCTRL _SFR_MEM8(0x0055)
+ #define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
++/* DFLL - DFLL */
+ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+ #define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+ #define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+@@ -2785,7 +3264,7 @@
+ #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+ #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
++/* DFLL - DFLL */
+ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+ #define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+ #define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+@@ -2802,7 +3281,7 @@
+ #define PR_PRPE _SFR_MEM8(0x0075)
+ #define PR_PRPF _SFR_MEM8(0x0076)
+
+-/* RST - Reset Controller */
++/* RST - Reset */
+ #define RST_STATUS _SFR_MEM8(0x0078)
+ #define RST_CTRL _SFR_MEM8(0x0079)
+
+@@ -2822,25 +3301,26 @@
+ #define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+ #define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+-/* PMIC - Programmable Interrupt Controller */
++/* PMIC - Programmable Multi-level Interrupt Controller */
+ #define PMIC_STATUS _SFR_MEM8(0x00A0)
+ #define PMIC_INTPRI _SFR_MEM8(0x00A1)
+ #define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+-/* PORTCFG - Port Configuration */
++/* PORTCFG - I/O port Configuration */
+ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+ #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+ #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+ #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
+
+-/* AES - AES Crypto Module */
++/* AES - AES Module */
+ #define AES_CTRL _SFR_MEM8(0x00C0)
+ #define AES_STATUS _SFR_MEM8(0x00C1)
+ #define AES_STATE _SFR_MEM8(0x00C2)
+ #define AES_KEY _SFR_MEM8(0x00C3)
+ #define AES_INTCTRL _SFR_MEM8(0x00C4)
+
+-/* CRC - CRC Module */
++/* CRC - Cyclic Redundancy Checker */
+ #define CRC_CTRL _SFR_MEM8(0x00D0)
+ #define CRC_STATUS _SFR_MEM8(0x00D1)
+ #define CRC_DATAIN _SFR_MEM8(0x00D3)
+@@ -2923,7 +3403,7 @@
+ #define EVSYS_STROBE _SFR_MEM8(0x0190)
+ #define EVSYS_DATA _SFR_MEM8(0x0191)
+
+-/* NVM - Non Volatile Memory Controller */
++/* NVM - Non-volatile Memory Controller */
+ #define NVM_ADDR0 _SFR_MEM8(0x01C0)
+ #define NVM_ADDR1 _SFR_MEM8(0x01C1)
+ #define NVM_ADDR2 _SFR_MEM8(0x01C2)
+@@ -2937,7 +3417,7 @@
+ #define NVM_STATUS _SFR_MEM8(0x01CF)
+ #define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+-/* ADCA - Analog to Digital Converter A */
++/* ADC - Analog-to-Digital Converter */
+ #define ADCA_CTRLA _SFR_MEM8(0x0200)
+ #define ADCA_CTRLB _SFR_MEM8(0x0201)
+ #define ADCA_REFCTRL _SFR_MEM8(0x0202)
+@@ -2956,23 +3436,27 @@
+ #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+ #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+ #define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
+ #define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
+ #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
+ #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
+ #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
+ #define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
+ #define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
+ #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
+ #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
+ #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
+ #define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
+ #define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
+ #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
+ #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
+ #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
+ #define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
+
+-/* ADCB - Analog to Digital Converter B */
++/* ADC - Analog-to-Digital Converter */
+ #define ADCB_CTRLA _SFR_MEM8(0x0240)
+ #define ADCB_CTRLB _SFR_MEM8(0x0241)
+ #define ADCB_REFCTRL _SFR_MEM8(0x0242)
+@@ -2991,23 +3475,27 @@
+ #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
+ #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
+ #define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
+ #define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
+ #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
+ #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
+ #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
+ #define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
+ #define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
+ #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
+ #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
+ #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
+ #define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
+ #define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
+ #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
+ #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
+ #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
+ #define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
+
+-/* DACA - Digital to Analog Converter A */
++/* DAC - Digital-to-Analog Converter */
+ #define DACA_CTRLA _SFR_MEM8(0x0300)
+ #define DACA_CTRLB _SFR_MEM8(0x0301)
+ #define DACA_CTRLC _SFR_MEM8(0x0302)
+@@ -3021,7 +3509,7 @@
+ #define DACA_CH0DATA _SFR_MEM16(0x0318)
+ #define DACA_CH1DATA _SFR_MEM16(0x031A)
+
+-/* DACB - Digital to Analog Converter B */
++/* DAC - Digital-to-Analog Converter */
+ #define DACB_CTRLA _SFR_MEM8(0x0320)
+ #define DACB_CTRLB _SFR_MEM8(0x0321)
+ #define DACB_CTRLC _SFR_MEM8(0x0322)
+@@ -3035,7 +3523,7 @@
+ #define DACB_CH0DATA _SFR_MEM16(0x0338)
+ #define DACB_CH1DATA _SFR_MEM16(0x033A)
+
+-/* ACA - Analog Comparator A */
++/* AC - Analog Comparator */
+ #define ACA_AC0CTRL _SFR_MEM8(0x0380)
+ #define ACA_AC1CTRL _SFR_MEM8(0x0381)
+ #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+@@ -3045,7 +3533,7 @@
+ #define ACA_WINCTRL _SFR_MEM8(0x0386)
+ #define ACA_STATUS _SFR_MEM8(0x0387)
+
+-/* ACB - Analog Comparator B */
++/* AC - Analog Comparator */
+ #define ACB_AC0CTRL _SFR_MEM8(0x0390)
+ #define ACB_AC1CTRL _SFR_MEM8(0x0391)
+ #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
+@@ -3085,7 +3573,7 @@
+ #define EBI_CS3_CTRLB _SFR_MEM8(0x045D)
+ #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E)
+
+-/* TWIC - Two-Wire Interface C */
++/* TWI - Two-Wire Interface */
+ #define TWIC_CTRL _SFR_MEM8(0x0480)
+ #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
+ #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
+@@ -3101,7 +3589,7 @@
+ #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+ #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+-/* TWID - Two-Wire Interface D */
++/* TWI - Two-Wire Interface */
+ #define TWID_CTRL _SFR_MEM8(0x0490)
+ #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491)
+ #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492)
+@@ -3117,7 +3605,7 @@
+ #define TWID_SLAVE_DATA _SFR_MEM8(0x049C)
+ #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D)
+
+-/* TWIE - Two-Wire Interface E */
++/* TWI - Two-Wire Interface */
+ #define TWIE_CTRL _SFR_MEM8(0x04A0)
+ #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
+ #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
+@@ -3133,7 +3621,7 @@
+ #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
+ #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
+
+-/* TWIF - Two-Wire Interface F */
++/* TWI - Two-Wire Interface */
+ #define TWIF_CTRL _SFR_MEM8(0x04B0)
+ #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1)
+ #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2)
+@@ -3149,7 +3637,7 @@
+ #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC)
+ #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD)
+
+-/* USB - Universal Serial Bus Module */
++/* USB - Universal Serial Bus */
+ #define USB_CTRLA _SFR_MEM8(0x04C0)
+ #define USB_CTRLB _SFR_MEM8(0x04C1)
+ #define USB_STATUS _SFR_MEM8(0x04C2)
+@@ -3166,7 +3654,7 @@
+ #define USB_CAL0 _SFR_MEM8(0x04FA)
+ #define USB_CAL1 _SFR_MEM8(0x04FB)
+
+-/* PORTA - Port A */
++/* PORT - I/O Ports */
+ #define PORTA_DIR _SFR_MEM8(0x0600)
+ #define PORTA_DIRSET _SFR_MEM8(0x0601)
+ #define PORTA_DIRCLR _SFR_MEM8(0x0602)
+@@ -3180,6 +3668,7 @@
+ #define PORTA_INT0MASK _SFR_MEM8(0x060A)
+ #define PORTA_INT1MASK _SFR_MEM8(0x060B)
+ #define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
+ #define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+ #define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+ #define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+@@ -3189,7 +3678,7 @@
+ #define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+ #define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+-/* PORTB - Port B */
++/* PORT - I/O Ports */
+ #define PORTB_DIR _SFR_MEM8(0x0620)
+ #define PORTB_DIRSET _SFR_MEM8(0x0621)
+ #define PORTB_DIRCLR _SFR_MEM8(0x0622)
+@@ -3203,6 +3692,7 @@
+ #define PORTB_INT0MASK _SFR_MEM8(0x062A)
+ #define PORTB_INT1MASK _SFR_MEM8(0x062B)
+ #define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
+ #define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+ #define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+ #define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+@@ -3212,7 +3702,7 @@
+ #define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+ #define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+-/* PORTC - Port C */
++/* PORT - I/O Ports */
+ #define PORTC_DIR _SFR_MEM8(0x0640)
+ #define PORTC_DIRSET _SFR_MEM8(0x0641)
+ #define PORTC_DIRCLR _SFR_MEM8(0x0642)
+@@ -3226,6 +3716,7 @@
+ #define PORTC_INT0MASK _SFR_MEM8(0x064A)
+ #define PORTC_INT1MASK _SFR_MEM8(0x064B)
+ #define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
+ #define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+ #define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+ #define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+@@ -3235,7 +3726,7 @@
+ #define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+ #define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+-/* PORTD - Port D */
++/* PORT - I/O Ports */
+ #define PORTD_DIR _SFR_MEM8(0x0660)
+ #define PORTD_DIRSET _SFR_MEM8(0x0661)
+ #define PORTD_DIRCLR _SFR_MEM8(0x0662)
+@@ -3249,6 +3740,7 @@
+ #define PORTD_INT0MASK _SFR_MEM8(0x066A)
+ #define PORTD_INT1MASK _SFR_MEM8(0x066B)
+ #define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
+ #define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+ #define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+ #define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+@@ -3258,7 +3750,7 @@
+ #define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+ #define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+-/* PORTE - Port E */
++/* PORT - I/O Ports */
+ #define PORTE_DIR _SFR_MEM8(0x0680)
+ #define PORTE_DIRSET _SFR_MEM8(0x0681)
+ #define PORTE_DIRCLR _SFR_MEM8(0x0682)
+@@ -3272,6 +3764,7 @@
+ #define PORTE_INT0MASK _SFR_MEM8(0x068A)
+ #define PORTE_INT1MASK _SFR_MEM8(0x068B)
+ #define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
+ #define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+ #define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+ #define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+@@ -3281,7 +3774,7 @@
+ #define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+ #define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+-/* PORTF - Port F */
++/* PORT - I/O Ports */
+ #define PORTF_DIR _SFR_MEM8(0x06A0)
+ #define PORTF_DIRSET _SFR_MEM8(0x06A1)
+ #define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+@@ -3295,6 +3788,7 @@
+ #define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+ #define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+ #define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
+ #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+ #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+ #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+@@ -3304,7 +3798,7 @@
+ #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+ #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+-/* PORTH - Port H */
++/* PORT - I/O Ports */
+ #define PORTH_DIR _SFR_MEM8(0x06E0)
+ #define PORTH_DIRSET _SFR_MEM8(0x06E1)
+ #define PORTH_DIRCLR _SFR_MEM8(0x06E2)
+@@ -3318,6 +3812,7 @@
+ #define PORTH_INT0MASK _SFR_MEM8(0x06EA)
+ #define PORTH_INT1MASK _SFR_MEM8(0x06EB)
+ #define PORTH_INTFLAGS _SFR_MEM8(0x06EC)
++#define PORTH_REMAP _SFR_MEM8(0x06EE)
+ #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0)
+ #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1)
+ #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2)
+@@ -3327,7 +3822,7 @@
+ #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6)
+ #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7)
+
+-/* PORTJ - Port J */
++/* PORT - I/O Ports */
+ #define PORTJ_DIR _SFR_MEM8(0x0700)
+ #define PORTJ_DIRSET _SFR_MEM8(0x0701)
+ #define PORTJ_DIRCLR _SFR_MEM8(0x0702)
+@@ -3341,6 +3836,7 @@
+ #define PORTJ_INT0MASK _SFR_MEM8(0x070A)
+ #define PORTJ_INT1MASK _SFR_MEM8(0x070B)
+ #define PORTJ_INTFLAGS _SFR_MEM8(0x070C)
++#define PORTJ_REMAP _SFR_MEM8(0x070E)
+ #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710)
+ #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711)
+ #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712)
+@@ -3350,7 +3846,7 @@
+ #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716)
+ #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717)
+
+-/* PORTK - Port K */
++/* PORT - I/O Ports */
+ #define PORTK_DIR _SFR_MEM8(0x0720)
+ #define PORTK_DIRSET _SFR_MEM8(0x0721)
+ #define PORTK_DIRCLR _SFR_MEM8(0x0722)
+@@ -3364,6 +3860,7 @@
+ #define PORTK_INT0MASK _SFR_MEM8(0x072A)
+ #define PORTK_INT1MASK _SFR_MEM8(0x072B)
+ #define PORTK_INTFLAGS _SFR_MEM8(0x072C)
++#define PORTK_REMAP _SFR_MEM8(0x072E)
+ #define PORTK_PIN0CTRL _SFR_MEM8(0x0730)
+ #define PORTK_PIN1CTRL _SFR_MEM8(0x0731)
+ #define PORTK_PIN2CTRL _SFR_MEM8(0x0732)
+@@ -3373,7 +3870,7 @@
+ #define PORTK_PIN6CTRL _SFR_MEM8(0x0736)
+ #define PORTK_PIN7CTRL _SFR_MEM8(0x0737)
+
+-/* PORTQ - Port Q */
++/* PORT - I/O Ports */
+ #define PORTQ_DIR _SFR_MEM8(0x07C0)
+ #define PORTQ_DIRSET _SFR_MEM8(0x07C1)
+ #define PORTQ_DIRCLR _SFR_MEM8(0x07C2)
+@@ -3387,6 +3884,7 @@
+ #define PORTQ_INT0MASK _SFR_MEM8(0x07CA)
+ #define PORTQ_INT1MASK _SFR_MEM8(0x07CB)
+ #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC)
++#define PORTQ_REMAP _SFR_MEM8(0x07CE)
+ #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0)
+ #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1)
+ #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2)
+@@ -3396,7 +3894,7 @@
+ #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6)
+ #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7)
+
+-/* PORTR - Port R */
++/* PORT - I/O Ports */
+ #define PORTR_DIR _SFR_MEM8(0x07E0)
+ #define PORTR_DIRSET _SFR_MEM8(0x07E1)
+ #define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+@@ -3410,6 +3908,7 @@
+ #define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+ #define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+ #define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
+ #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+ #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+ #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+@@ -3419,7 +3918,7 @@
+ #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+ #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+-/* TCC0 - Timer/Counter C0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCC0_CTRLA _SFR_MEM8(0x0800)
+ #define TCC0_CTRLB _SFR_MEM8(0x0801)
+ #define TCC0_CTRLC _SFR_MEM8(0x0802)
+@@ -3445,7 +3944,29 @@
+ #define TCC0_CCCBUF _SFR_MEM16(0x083C)
+ #define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+-/* TCC1 - Timer/Counter C1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCC1_CTRLA _SFR_MEM8(0x0840)
+ #define TCC1_CTRLB _SFR_MEM8(0x0841)
+ #define TCC1_CTRLC _SFR_MEM8(0x0842)
+@@ -3467,11 +3988,12 @@
+ #define TCC1_CCABUF _SFR_MEM16(0x0878)
+ #define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+-/* AWEXC - Advanced Waveform Extension C */
++/* AWEX - Advanced Waveform Extension */
+ #define AWEXC_CTRL _SFR_MEM8(0x0880)
+ #define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+ #define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+ #define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
+ #define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+ #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+ #define AWEXC_DTLS _SFR_MEM8(0x0888)
+@@ -3480,10 +4002,10 @@
+ #define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+ #define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+-/* HIRESC - High-Resolution Extension C */
++/* HIRES - High-Resolution Extension */
+ #define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTC0_DATA _SFR_MEM8(0x08A0)
+ #define USARTC0_STATUS _SFR_MEM8(0x08A1)
+ #define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+@@ -3492,7 +4014,7 @@
+ #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+ #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTC1_DATA _SFR_MEM8(0x08B0)
+ #define USARTC1_STATUS _SFR_MEM8(0x08B1)
+ #define USARTC1_CTRLA _SFR_MEM8(0x08B3)
+@@ -3501,7 +4023,7 @@
+ #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
+ #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
+
+-/* SPIC - Serial Peripheral Interface C */
++/* SPI - Serial Peripheral Interface */
+ #define SPIC_CTRL _SFR_MEM8(0x08C0)
+ #define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+ #define SPIC_STATUS _SFR_MEM8(0x08C2)
+@@ -3512,7 +4034,7 @@
+ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+ #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+-/* TCD0 - Timer/Counter D0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCD0_CTRLA _SFR_MEM8(0x0900)
+ #define TCD0_CTRLB _SFR_MEM8(0x0901)
+ #define TCD0_CTRLC _SFR_MEM8(0x0902)
+@@ -3538,7 +4060,29 @@
+ #define TCD0_CCCBUF _SFR_MEM16(0x093C)
+ #define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+-/* TCD1 - Timer/Counter D1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCD1_CTRLA _SFR_MEM8(0x0940)
+ #define TCD1_CTRLB _SFR_MEM8(0x0941)
+ #define TCD1_CTRLC _SFR_MEM8(0x0942)
+@@ -3560,10 +4104,10 @@
+ #define TCD1_CCABUF _SFR_MEM16(0x0978)
+ #define TCD1_CCBBUF _SFR_MEM16(0x097A)
+
+-/* HIRESD - High-Resolution Extension D */
++/* HIRES - High-Resolution Extension */
+ #define HIRESD_CTRLA _SFR_MEM8(0x0990)
+
+-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTD0_DATA _SFR_MEM8(0x09A0)
+ #define USARTD0_STATUS _SFR_MEM8(0x09A1)
+ #define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+@@ -3572,7 +4116,7 @@
+ #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+ #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTD1_DATA _SFR_MEM8(0x09B0)
+ #define USARTD1_STATUS _SFR_MEM8(0x09B1)
+ #define USARTD1_CTRLA _SFR_MEM8(0x09B3)
+@@ -3581,13 +4125,13 @@
+ #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
+ #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
+
+-/* SPID - Serial Peripheral Interface D */
++/* SPI - Serial Peripheral Interface */
+ #define SPID_CTRL _SFR_MEM8(0x09C0)
+ #define SPID_INTCTRL _SFR_MEM8(0x09C1)
+ #define SPID_STATUS _SFR_MEM8(0x09C2)
+ #define SPID_DATA _SFR_MEM8(0x09C3)
+
+-/* TCE0 - Timer/Counter E0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCE0_CTRLA _SFR_MEM8(0x0A00)
+ #define TCE0_CTRLB _SFR_MEM8(0x0A01)
+ #define TCE0_CTRLC _SFR_MEM8(0x0A02)
+@@ -3613,7 +4157,29 @@
+ #define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+ #define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+-/* TCE1 - Timer/Counter E1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCE1_CTRLA _SFR_MEM8(0x0A40)
+ #define TCE1_CTRLB _SFR_MEM8(0x0A41)
+ #define TCE1_CTRLC _SFR_MEM8(0x0A42)
+@@ -3635,11 +4201,12 @@
+ #define TCE1_CCABUF _SFR_MEM16(0x0A78)
+ #define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
+
+-/* AWEXE - Advanced Waveform Extension E */
++/* AWEX - Advanced Waveform Extension */
+ #define AWEXE_CTRL _SFR_MEM8(0x0A80)
+ #define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+ #define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+ #define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
+ #define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+ #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+ #define AWEXE_DTLS _SFR_MEM8(0x0A88)
+@@ -3648,10 +4215,10 @@
+ #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+ #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+-/* HIRESE - High-Resolution Extension E */
++/* HIRES - High-Resolution Extension */
+ #define HIRESE_CTRLA _SFR_MEM8(0x0A90)
+
+-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTE0_DATA _SFR_MEM8(0x0AA0)
+ #define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+ #define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+@@ -3660,7 +4227,7 @@
+ #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+ #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTE1_DATA _SFR_MEM8(0x0AB0)
+ #define USARTE1_STATUS _SFR_MEM8(0x0AB1)
+ #define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
+@@ -3669,13 +4236,13 @@
+ #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
+ #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
+
+-/* SPIE - Serial Peripheral Interface E */
++/* SPI - Serial Peripheral Interface */
+ #define SPIE_CTRL _SFR_MEM8(0x0AC0)
+ #define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+ #define SPIE_STATUS _SFR_MEM8(0x0AC2)
+ #define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+-/* TCF0 - Timer/Counter F0 */
++/* TC0 - 16-bit Timer/Counter 0 */
+ #define TCF0_CTRLA _SFR_MEM8(0x0B00)
+ #define TCF0_CTRLB _SFR_MEM8(0x0B01)
+ #define TCF0_CTRLC _SFR_MEM8(0x0B02)
+@@ -3701,7 +4268,29 @@
+ #define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+ #define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+-/* TCF1 - Timer/Counter F1 */
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
+ #define TCF1_CTRLA _SFR_MEM8(0x0B40)
+ #define TCF1_CTRLB _SFR_MEM8(0x0B41)
+ #define TCF1_CTRLC _SFR_MEM8(0x0B42)
+@@ -3723,10 +4312,10 @@
+ #define TCF1_CCABUF _SFR_MEM16(0x0B78)
+ #define TCF1_CCBBUF _SFR_MEM16(0x0B7A)
+
+-/* HIRESF - High-Resolution Extension F */
++/* HIRES - High-Resolution Extension */
+ #define HIRESF_CTRLA _SFR_MEM8(0x0B90)
+
+-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTF0_DATA _SFR_MEM8(0x0BA0)
+ #define USARTF0_STATUS _SFR_MEM8(0x0BA1)
+ #define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
+@@ -3735,7 +4324,7 @@
+ #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
+ #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
+
+-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
+ #define USARTF1_DATA _SFR_MEM8(0x0BB0)
+ #define USARTF1_STATUS _SFR_MEM8(0x0BB1)
+ #define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
+@@ -3744,7 +4333,7 @@
+ #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
+ #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
+
+-/* SPIF - Serial Peripheral Interface F */
++/* SPI - Serial Peripheral Interface */
+ #define SPIF_CTRL _SFR_MEM8(0x0BC0)
+ #define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
+ #define SPIF_STATUS _SFR_MEM8(0x0BC2)
+@@ -3762,13 +4351,11 @@
+ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+-
+ /* XOCD - On-Chip Debug System */
+ /* OCD.OCDR1 bit masks and bit positions */
+ #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+ #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+-
+ /* CPU - CPU */
+ /* CPU.CCP bit masks and bit positions */
+ #define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+@@ -3790,7 +4377,6 @@
+ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+-
+ /* CPU.SREG bit masks and bit positions */
+ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+@@ -3816,7 +4402,6 @@
+ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+ #define CPU_C_bp 0 /* Carry Flag bit position. */
+
+-
+ /* CLK - Clock System */
+ /* CLK.CTRL bit masks and bit positions */
+ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+@@ -3828,7 +4413,6 @@
+ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+-
+ /* CLK.PSCTRL bit masks and bit positions */
+ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+@@ -3850,12 +4434,10 @@
+ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+-
+ /* CLK.LOCK bit masks and bit positions */
+ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+-
+ /* CLK.RTCCTRL bit masks and bit positions */
+ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+@@ -3869,7 +4451,6 @@
+ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
+ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
+
+-
+ /* CLK.USBCTRL bit masks and bit positions */
+ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
+ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
+@@ -3887,9 +4468,8 @@
+ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
+
+-#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */
+-#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */
+-
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
+
+ /* PR.PRGEN bit masks and bit positions */
+ #define PR_USB_bm 0x40 /* USB bit mask. */
+@@ -3910,7 +4490,6 @@
+ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+ #define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+-
+ /* PR.PRPA bit masks and bit positions */
+ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+ #define PR_DAC_bp 2 /* Port A DAC bit position. */
+@@ -3921,17 +4500,15 @@
+ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+-
+ /* PR.PRPB bit masks and bit positions */
+-/* PR_DAC_bm Predefined. */
+-/* PR_DAC_bp Predefined. */
+-
+-/* PR_ADC_bm Predefined. */
+-/* PR_ADC_bp Predefined. */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
+
+-/* PR_AC_bm Predefined. */
+-/* PR_AC_bp Predefined. */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
+
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
+
+ /* PR.PRPC bit masks and bit positions */
+ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+@@ -3955,75 +4532,71 @@
+ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+-
+ /* PR.PRPD bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
+-
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* PR.PRPE bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
+-
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* PR.PRPF bit masks and bit positions */
+-/* PR_TWI_bm Predefined. */
+-/* PR_TWI_bp Predefined. */
+-
+-/* PR_USART1_bm Predefined. */
+-/* PR_USART1_bp Predefined. */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
+
+-/* PR_USART0_bm Predefined. */
+-/* PR_USART0_bp Predefined. */
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
+
+-/* PR_SPI_bm Predefined. */
+-/* PR_SPI_bp Predefined. */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
+
+-/* PR_HIRES_bm Predefined. */
+-/* PR_HIRES_bp Predefined. */
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
+
+-/* PR_TC1_bm Predefined. */
+-/* PR_TC1_bp Predefined. */
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
+
+-/* PR_TC0_bm Predefined. */
+-/* PR_TC0_bp Predefined. */
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
+
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
+
+ /* SLEEP - Sleep Controller */
+ /* SLEEP.CTRL bit masks and bit positions */
+@@ -4039,7 +4612,6 @@
+ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+-
+ /* OSC - Oscillator */
+ /* OSC.CTRL bit masks and bit positions */
+ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+@@ -4057,7 +4629,6 @@
+ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
+ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
+
+-
+ /* OSC.STATUS bit masks and bit positions */
+ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+@@ -4074,7 +4645,6 @@
+ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
+ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
+
+-
+ /* OSC.XOSCCTRL bit masks and bit positions */
+ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+@@ -4086,6 +4656,9 @@
+ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
+ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
+
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
+ #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+@@ -4097,7 +4670,6 @@
+ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+-
+ /* OSC.XOSCFAIL bit masks and bit positions */
+ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
+ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
+@@ -4111,7 +4683,6 @@
+ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
+ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
+
+-
+ /* OSC.PLLCTRL bit masks and bit positions */
+ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+@@ -4120,6 +4691,9 @@
+ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
+ #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+@@ -4133,25 +4707,22 @@
+ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+-
+ /* OSC.DFLLCTRL bit masks and bit positions */
+-#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */
+-#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */
+-#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */
+-#define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */
+-#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */
+-#define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */
+-
+-#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */
+-#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
+
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
+
+ /* DFLL - DFLL */
+ /* DFLL.CTRL bit masks and bit positions */
+ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+-
+ /* DFLL.CALA bit masks and bit positions */
+ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
+ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
+@@ -4170,7 +4741,6 @@
+ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
+ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
+
+-
+ /* DFLL.CALB bit masks and bit positions */
+ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
+ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
+@@ -4187,7 +4757,6 @@
+ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
+ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
+
+-
+ /* RST - Reset */
+ /* RST.STATUS bit masks and bit positions */
+ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+@@ -4211,12 +4780,10 @@
+ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+-
+ /* RST.CTRL bit masks and bit positions */
+ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+ #define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+-
+ /* WDT - Watch-Dog Timer */
+ /* WDT.CTRL bit masks and bit positions */
+ #define WDT_PER_gm 0x3C /* Period group mask. */
+@@ -4236,7 +4803,6 @@
+ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+ #define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+-
+ /* WDT.WINCTRL bit masks and bit positions */
+ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+@@ -4255,33 +4821,29 @@
+ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+-
+ /* WDT.STATUS bit masks and bit positions */
+ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+-
+ /* MCU - MCU Control */
+ /* MCU.MCUCR bit masks and bit positions */
+ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+-
+ /* MCU.ANAINIT bit masks and bit positions */
+-#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */
+-#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */
+-#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */
+-#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */
+-#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */
+-#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */
+-
+-#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */
+-#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */
+-#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */
+-#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */
+-#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */
+-#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */
+-
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
+
+ /* MCU.EVSYSLOCK bit masks and bit positions */
+ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+@@ -4290,15 +4852,19 @@
+ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+-
+ /* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
+ #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
+ #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+-
+ /* PMIC - Programmable Multi-level Interrupt Controller */
+ /* PMIC.STATUS bit masks and bit positions */
+ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+@@ -4313,7 +4879,6 @@
+ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+-
+ /* PMIC.CTRL bit masks and bit positions */
+ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+ #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+@@ -4330,7 +4895,6 @@
+ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+-
+ /* PORTCFG - Port Configuration */
+ /* PORTCFG.VPCTRLA bit masks and bit positions */
+ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+@@ -4355,7 +4919,6 @@
+ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+-
+ /* PORTCFG.VPCTRLB bit masks and bit positions */
+ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+@@ -4379,7 +4942,6 @@
+ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+-
+ /* PORTCFG.CLKEVOUT bit masks and bit positions */
+ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
+ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
+@@ -4408,6 +4970,15 @@
+ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
+ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
+
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
+
+ /* AES - AES Module */
+ /* AES.CTRL bit masks and bit positions */
+@@ -4426,7 +4997,6 @@
+ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
+ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
+
+-
+ /* AES.STATUS bit masks and bit positions */
+ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */
+ #define AES_ERROR_bp 7 /* AES Error bit position. */
+@@ -4434,7 +5004,6 @@
+ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
+ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
+
+-
+ /* AES.INTCTRL bit masks and bit positions */
+ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
+ #define AES_INTLVL_gp 0 /* Interrupt level group position. */
+@@ -4443,38 +5012,35 @@
+ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+-
+ /* CRC - Cyclic Redundancy Checker */
+ /* CRC.CTRL bit masks and bit positions */
+-#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */
+-#define CRC_RESET_gp 6 /* CRC Reset group position. */
+-#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */
+-#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */
+-#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */
+-#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
+
+ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
+ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */
+
+-#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */
+-#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */
+-#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */
+-#define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */
+-#define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */
+-#define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */
+-#define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */
+-#define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */
+-#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */
+-#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */
+-
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
+
+ /* CRC.STATUS bit masks and bit positions */
+-#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */
+-#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */
+-
+-#define CRC_BUSY_bm 0x01 /* Enable bit mask. */
+-#define CRC_BUSY_bp 0 /* Enable bit position. */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
+
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
+
+ /* DMA - DMA Controller */
+ /* DMA_CH.CTRLA bit masks and bit positions */
+@@ -4500,7 +5066,6 @@
+ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
+ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
+
+-
+ /* DMA_CH.CTRLB bit masks and bit positions */
+ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
+ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
+@@ -4528,7 +5093,6 @@
+ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
+ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
+
+-
+ /* DMA_CH.ADDRCTRL bit masks and bit positions */
+ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
+ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
+@@ -4558,7 +5122,6 @@
+ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
+ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
+
+-
+ /* DMA_CH.TRIGSRC bit masks and bit positions */
+ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
+ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
+@@ -4579,7 +5142,6 @@
+ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
+ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
+
+-
+ /* DMA.CTRL bit masks and bit positions */
+ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
+ #define DMA_ENABLE_bp 7 /* Enable bit position. */
+@@ -4601,7 +5163,6 @@
+ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
+ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
+
+-
+ /* DMA.INTFLAGS bit masks and bit positions */
+ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+@@ -4627,7 +5188,6 @@
+ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+
+-
+ /* DMA.STATUS bit masks and bit positions */
+ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
+ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
+@@ -4653,7 +5213,6 @@
+ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
+ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
+
+-
+ /* EVSYS - Event System */
+ /* EVSYS.CH0MUX bit masks and bit positions */
+ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+@@ -4675,153 +5234,33 @@
+ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+-
+ /* EVSYS.CH1MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH2MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH3MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH4MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH5MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH6MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH7MUX bit masks and bit positions */
+-/* EVSYS_CHMUX_gm Predefined. */
+-/* EVSYS_CHMUX_gp Predefined. */
+-/* EVSYS_CHMUX0_bm Predefined. */
+-/* EVSYS_CHMUX0_bp Predefined. */
+-/* EVSYS_CHMUX1_bm Predefined. */
+-/* EVSYS_CHMUX1_bp Predefined. */
+-/* EVSYS_CHMUX2_bm Predefined. */
+-/* EVSYS_CHMUX2_bp Predefined. */
+-/* EVSYS_CHMUX3_bm Predefined. */
+-/* EVSYS_CHMUX3_bp Predefined. */
+-/* EVSYS_CHMUX4_bm Predefined. */
+-/* EVSYS_CHMUX4_bp Predefined. */
+-/* EVSYS_CHMUX5_bm Predefined. */
+-/* EVSYS_CHMUX5_bp Predefined. */
+-/* EVSYS_CHMUX6_bm Predefined. */
+-/* EVSYS_CHMUX6_bp Predefined. */
+-/* EVSYS_CHMUX7_bm Predefined. */
+-/* EVSYS_CHMUX7_bp Predefined. */
+-
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
+
+ /* EVSYS.CH0CTRL bit masks and bit positions */
+ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+@@ -4846,109 +5285,51 @@
+ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+-
+ /* EVSYS.CH1CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
+-
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH2CTRL bit masks and bit positions */
+-/* EVSYS_QDIRM_gm Predefined. */
+-/* EVSYS_QDIRM_gp Predefined. */
+-/* EVSYS_QDIRM0_bm Predefined. */
+-/* EVSYS_QDIRM0_bp Predefined. */
+-/* EVSYS_QDIRM1_bm Predefined. */
+-/* EVSYS_QDIRM1_bp Predefined. */
+-
+-/* EVSYS_QDIEN_bm Predefined. */
+-/* EVSYS_QDIEN_bp Predefined. */
+-
+-/* EVSYS_QDEN_bm Predefined. */
+-/* EVSYS_QDEN_bp Predefined. */
+-
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
+
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
+
+-/* EVSYS.CH3CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
+
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH4CTRL bit masks and bit positions */
+-/* EVSYS_QDIRM_gm Predefined. */
+-/* EVSYS_QDIRM_gp Predefined. */
+-/* EVSYS_QDIRM0_bm Predefined. */
+-/* EVSYS_QDIRM0_bp Predefined. */
+-/* EVSYS_QDIRM1_bm Predefined. */
+-/* EVSYS_QDIRM1_bp Predefined. */
+-
+-/* EVSYS_QDIEN_bm Predefined. */
+-/* EVSYS_QDIEN_bp Predefined. */
+-
+-/* EVSYS_QDEN_bm Predefined. */
+-/* EVSYS_QDEN_bp Predefined. */
+-
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
+
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
+
+-/* EVSYS.CH5CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
+
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+-/* EVSYS.CH6CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* EVSYS.CH7CTRL bit masks and bit positions */
+-/* EVSYS_DIGFILT_gm Predefined. */
+-/* EVSYS_DIGFILT_gp Predefined. */
+-/* EVSYS_DIGFILT0_bm Predefined. */
+-/* EVSYS_DIGFILT0_bp Predefined. */
+-/* EVSYS_DIGFILT1_bm Predefined. */
+-/* EVSYS_DIGFILT1_bp Predefined. */
+-/* EVSYS_DIGFILT2_bm Predefined. */
+-/* EVSYS_DIGFILT2_bp Predefined. */
+-
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
+
+ /* NVM - Non Volatile Memory Controller */
+ /* NVM.CMD bit masks and bit positions */
+@@ -4969,12 +5350,10 @@
+ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+ #define NVM_CMD6_bp 6 /* Command bit 6 position. */
+
+-
+ /* NVM.CTRLA bit masks and bit positions */
+ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+-
+ /* NVM.CTRLB bit masks and bit positions */
+ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+@@ -4988,7 +5367,6 @@
+ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+-
+ /* NVM.INTCTRL bit masks and bit positions */
+ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+@@ -5004,7 +5382,6 @@
+ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+-
+ /* NVM.STATUS bit masks and bit positions */
+ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+@@ -5018,7 +5395,6 @@
+ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+-
+ /* NVM.LOCKBITS bit masks and bit positions */
+ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+@@ -5048,7 +5424,6 @@
+ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+-
+ /* ADC - Analog/Digital Converter */
+ /* ADC_CH.CTRL bit masks and bit positions */
+ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+@@ -5070,7 +5445,6 @@
+ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+-
+ /* ADC_CH.MUXCTRL bit masks and bit positions */
+ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
+ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
+@@ -5101,7 +5475,6 @@
+ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
+ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
+
+-
+ /* ADC_CH.INTCTRL bit masks and bit positions */
+ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+ #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+@@ -5117,11 +5490,32 @@
+ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+-
+ /* ADC_CH.INTFLAGS bit masks and bit positions */
+ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
+
+ /* ADC.CTRLA bit masks and bit positions */
+ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
+@@ -5149,17 +5543,16 @@
+ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+-
+ /* ADC.CTRLB bit masks and bit positions */
+ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
+ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
+
+-#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */
+-#define ADC_CURRENT_gp 5 /* Current Limitation group position. */
+-#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */
+-#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */
+-#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */
+-#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
+
+ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+@@ -5174,7 +5567,6 @@
+ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+-
+ /* ADC.REFCTRL bit masks and bit positions */
+ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
+ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+@@ -5191,7 +5583,6 @@
+ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+-
+ /* ADC.EVCTRL bit masks and bit positions */
+ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+@@ -5218,7 +5609,6 @@
+ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+-
+ /* ADC.PRESCALER bit masks and bit positions */
+ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+@@ -5229,7 +5619,6 @@
+ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+-
+ /* ADC.INTFLAGS bit masks and bit positions */
+ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
+ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
+@@ -5243,7 +5632,6 @@
+ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+-
+ /* DAC - Digital/Analog Converter */
+ /* DAC.CTRLA bit masks and bit positions */
+ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
+@@ -5261,7 +5649,6 @@
+ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
+ #define DAC_ENABLE_bp 0 /* Enable bit position. */
+
+-
+ /* DAC.CTRLB bit masks and bit positions */
+ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
+ #define DAC_CHSEL_gp 5 /* Channel Select group position. */
+@@ -5276,7 +5663,6 @@
+ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
+ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
+
+-
+ /* DAC.CTRLC bit masks and bit positions */
+ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
+ #define DAC_REFSEL_gp 3 /* Reference Select group position. */
+@@ -5288,7 +5674,6 @@
+ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
+ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
+
+-
+ /* DAC.EVCTRL bit masks and bit positions */
+ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
+ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
+@@ -5302,7 +5687,6 @@
+ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
+ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
+
+-
+ /* DAC.TIMCTRL bit masks and bit positions */
+ #define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
+ #define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
+@@ -5324,7 +5708,6 @@
+ #define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
+ #define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
+
+-
+ /* DAC.STATUS bit masks and bit positions */
+ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
+ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
+@@ -5332,7 +5715,6 @@
+ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
+ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
+
+-
+ /* DAC.CH0GAINCAL bit masks and bit positions */
+ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
+ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
+@@ -5351,7 +5733,6 @@
+ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
+ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
+
+-
+ /* DAC.CH0OFFSETCAL bit masks and bit positions */
+ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
+ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
+@@ -5370,7 +5751,6 @@
+ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
+ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
+
+-
+ /* DAC.CH1GAINCAL bit masks and bit positions */
+ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
+ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
+@@ -5389,7 +5769,6 @@
+ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
+ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
+
+-
+ /* DAC.CH1OFFSETCAL bit masks and bit positions */
+ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
+ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
+@@ -5408,7 +5787,6 @@
+ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
+ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
+
+-
+ /* AC - Analog Comparator */
+ /* AC.AC0CTRL bit masks and bit positions */
+ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+@@ -5438,35 +5816,21 @@
+ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+ #define AC_ENABLE_bp 0 /* Enable bit position. */
+
+-
+ /* AC.AC1CTRL bit masks and bit positions */
+-/* AC_INTMODE_gm Predefined. */
+-/* AC_INTMODE_gp Predefined. */
+-/* AC_INTMODE0_bm Predefined. */
+-/* AC_INTMODE0_bp Predefined. */
+-/* AC_INTMODE1_bm Predefined. */
+-/* AC_INTMODE1_bp Predefined. */
+-
+-/* AC_INTLVL_gm Predefined. */
+-/* AC_INTLVL_gp Predefined. */
+-/* AC_INTLVL0_bm Predefined. */
+-/* AC_INTLVL0_bp Predefined. */
+-/* AC_INTLVL1_bm Predefined. */
+-/* AC_INTLVL1_bp Predefined. */
+-
+-/* AC_HSMODE_bm Predefined. */
+-/* AC_HSMODE_bp Predefined. */
+-
+-/* AC_HYSMODE_gm Predefined. */
+-/* AC_HYSMODE_gp Predefined. */
+-/* AC_HYSMODE0_bm Predefined. */
+-/* AC_HYSMODE0_bp Predefined. */
+-/* AC_HYSMODE1_bm Predefined. */
+-/* AC_HYSMODE1_bp Predefined. */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
+
+-/* AC_ENABLE_bm Predefined. */
+-/* AC_ENABLE_bp Predefined. */
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
+
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
+
+ /* AC.AC0MUXCTRL bit masks and bit positions */
+ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+@@ -5487,32 +5851,20 @@
+ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+-
+ /* AC.AC1MUXCTRL bit masks and bit positions */
+-/* AC_MUXPOS_gm Predefined. */
+-/* AC_MUXPOS_gp Predefined. */
+-/* AC_MUXPOS0_bm Predefined. */
+-/* AC_MUXPOS0_bp Predefined. */
+-/* AC_MUXPOS1_bm Predefined. */
+-/* AC_MUXPOS1_bp Predefined. */
+-/* AC_MUXPOS2_bm Predefined. */
+-/* AC_MUXPOS2_bp Predefined. */
+-
+-/* AC_MUXNEG_gm Predefined. */
+-/* AC_MUXNEG_gp Predefined. */
+-/* AC_MUXNEG0_bm Predefined. */
+-/* AC_MUXNEG0_bp Predefined. */
+-/* AC_MUXNEG1_bm Predefined. */
+-/* AC_MUXNEG1_bp Predefined. */
+-/* AC_MUXNEG2_bm Predefined. */
+-/* AC_MUXNEG2_bp Predefined. */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
+
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
+
+ /* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
+ #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
+ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
+
+-
+ /* AC.CTRLB bit masks and bit positions */
+ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+@@ -5529,7 +5881,6 @@
+ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+-
+ /* AC.WINCTRL bit masks and bit positions */
+ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+@@ -5548,7 +5899,6 @@
+ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+-
+ /* AC.STATUS bit masks and bit positions */
+ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+ #define AC_WSTATE_gp 6 /* Window Mode State group position. */
+@@ -5572,8 +5922,7 @@
+ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
+ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
+
+-
+-/* RTC - Real-Time Clounter */
++/* RTC - Real-Time Counter */
+ /* RTC.CTRL bit masks and bit positions */
+ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+@@ -5584,12 +5933,10 @@
+ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+-
+ /* RTC.STATUS bit masks and bit positions */
+ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+-
+ /* RTC.INTCTRL bit masks and bit positions */
+ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+@@ -5605,7 +5952,6 @@
+ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+-
+ /* RTC.INTFLAGS bit masks and bit positions */
+ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+@@ -5613,21 +5959,20 @@
+ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+-
+ /* EBI - External Bus Interface */
+ /* EBI_CS.CTRLA bit masks and bit positions */
+-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */
+-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */
+-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */
+-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */
+-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */
+-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */
+-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */
+-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */
+-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */
+-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */
+-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */
+-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */
++#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
++#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
++#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
++#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
++#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
++#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
++#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
++#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
++#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
++#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
++#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
++#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+@@ -5636,7 +5981,6 @@
+ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+-
+ /* EBI_CS.CTRLB bit masks and bit positions */
+ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+@@ -5660,7 +6004,6 @@
+ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+-
+ /* EBI.CTRL bit masks and bit positions */
+ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+@@ -5690,7 +6033,6 @@
+ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+-
+ /* EBI.SDRAMCTRLA bit masks and bit positions */
+ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+@@ -5705,7 +6047,6 @@
+ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+-
+ /* EBI.SDRAMCTRLB bit masks and bit positions */
+ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+@@ -5732,7 +6073,6 @@
+ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+-
+ /* EBI.SDRAMCTRLC bit masks and bit positions */
+ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+@@ -5759,7 +6099,6 @@
+ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+-
+ /* TWI - Two-Wire Interface */
+ /* TWI_MASTER.CTRLA bit masks and bit positions */
+ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+@@ -5778,7 +6117,6 @@
+ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+-
+ /* TWI_MASTER.CTRLB bit masks and bit positions */
+ #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+ #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+@@ -5793,7 +6131,6 @@
+ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+-
+ /* TWI_MASTER.CTRLC bit masks and bit positions */
+ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+@@ -5805,7 +6142,6 @@
+ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+-
+ /* TWI_MASTER.STATUS bit masks and bit positions */
+ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+@@ -5832,7 +6168,6 @@
+ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+-
+ /* TWI_SLAVE.CTRLA bit masks and bit positions */
+ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+@@ -5859,7 +6194,6 @@
+ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+-
+ /* TWI_SLAVE.CTRLB bit masks and bit positions */
+ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+@@ -5871,7 +6205,6 @@
+ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+-
+ /* TWI_SLAVE.STATUS bit masks and bit positions */
+ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+@@ -5897,7 +6230,6 @@
+ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+-
+ /* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+@@ -5919,7 +6251,6 @@
+ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+-
+ /* TWI.CTRL bit masks and bit positions */
+ #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+ #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+@@ -5927,23 +6258,25 @@
+ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+-
+-/* USB - USB Module */
++/* USB - USB */
+ /* USB_EP.STATUS bit masks and bit positions */
+-#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */
+-#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
+
+-#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */
+-#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
+
+-#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */
+-#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
+
+-#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */
+-#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
+
+-#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */
+-#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
+
+ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
+ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
+@@ -5960,7 +6293,6 @@
+ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
+ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
+
+-
+ /* USB_EP.CTRL bit masks and bit positions */
+ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
+ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
+@@ -5978,30 +6310,21 @@
+ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
+ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
+
+-/* USB_EP_STALL_bm Predefined. */
+-/* USB_EP_STALL_bp Predefined. */
+-
+-#define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */
+-#define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */
+-#define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
+-#define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */
+-#define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
+-#define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */
+-#define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
+-#define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */
+-
+-
+-/* USB_EP.CNTH bit masks and bit positions */
+-#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */
+-#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */
+-
+-#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */
+-#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */
+-#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */
+-#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */
+-#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */
+-#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
+
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
+
+ /* USB.CTRLA bit masks and bit positions */
+ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
+@@ -6027,7 +6350,6 @@
+ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
+ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
+
+-
+ /* USB.CTRLB bit masks and bit positions */
+ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
+ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
+@@ -6041,7 +6363,6 @@
+ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */
+ #define USB_ATTACH_bp 0 /* Attach bit position. */
+
+-
+ /* USB.STATUS bit masks and bit positions */
+ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
+ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */
+@@ -6055,7 +6376,6 @@
+ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
+ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */
+
+-
+ /* USB.ADDR bit masks and bit positions */
+ #define USB_ADDR_gm 0x7F /* Device Address group mask. */
+ #define USB_ADDR_gp 0 /* Device Address group position. */
+@@ -6074,7 +6394,6 @@
+ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
+ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
+
+-
+ /* USB.FIFOWP bit masks and bit positions */
+ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
+ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
+@@ -6089,7 +6408,6 @@
+ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
+ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
+
+-
+ /* USB.FIFORP bit masks and bit positions */
+ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
+ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
+@@ -6104,7 +6422,6 @@
+ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
+ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
+
+-
+ /* USB.INTCTRLA bit masks and bit positions */
+ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
+ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
+@@ -6125,7 +6442,6 @@
+ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+-
+ /* USB.INTCTRLB bit masks and bit positions */
+ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
+ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
+@@ -6133,7 +6449,6 @@
+ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
+ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
+
+-
+ /* USB.INTFLAGSACLR bit masks and bit positions */
+ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
+ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
+@@ -6159,32 +6474,30 @@
+ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
+ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
+
+-
+ /* USB.INTFLAGSASET bit masks and bit positions */
+-/* USB_SOFIF_bm Predefined. */
+-/* USB_SOFIF_bp Predefined. */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
+
+-/* USB_SUSPENDIF_bm Predefined. */
+-/* USB_SUSPENDIF_bp Predefined. */
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
+
+-/* USB_RESUMEIF_bm Predefined. */
+-/* USB_RESUMEIF_bp Predefined. */
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
+
+-/* USB_RSTIF_bm Predefined. */
+-/* USB_RSTIF_bp Predefined. */
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
+
+-/* USB_CRCIF_bm Predefined. */
+-/* USB_CRCIF_bp Predefined. */
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
+
+-/* USB_UNFIF_bm Predefined. */
+-/* USB_UNFIF_bp Predefined. */
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
+
+-/* USB_OVFIF_bm Predefined. */
+-/* USB_OVFIF_bp Predefined. */
+-
+-/* USB_STALLIF_bm Predefined. */
+-/* USB_STALLIF_bp Predefined. */
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
+
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
+
+ /* USB.INTFLAGSBCLR bit masks and bit positions */
+ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
+@@ -6193,14 +6506,12 @@
+ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
+ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
+
+-
+ /* USB.INTFLAGSBSET bit masks and bit positions */
+-/* USB_TRNIF_bm Predefined. */
+-/* USB_TRNIF_bp Predefined. */
+-
+-/* USB_SETUPIF_bm Predefined. */
+-/* USB_SETUPIF_bp Predefined. */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
+
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
+
+ /* PORT - I/O Port Configuration */
+ /* PORT.INTCTRL bit masks and bit positions */
+@@ -6218,7 +6529,6 @@
+ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+-
+ /* PORT.INTFLAGS bit masks and bit positions */
+ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+@@ -6226,6 +6536,24 @@
+ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
+
+ /* PORT.PIN0CTRL bit masks and bit positions */
+ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+@@ -6252,188 +6580,96 @@
+ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+-
+ /* PORT.PIN1CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN2CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN3CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN4CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN5CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN6CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* PORT.PIN7CTRL bit masks and bit positions */
+-/* PORT_SRLEN_bm Predefined. */
+-/* PORT_SRLEN_bp Predefined. */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
+
+-/* PORT_INVEN_bm Predefined. */
+-/* PORT_INVEN_bp Predefined. */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
+
+-/* PORT_OPC_gm Predefined. */
+-/* PORT_OPC_gp Predefined. */
+-/* PORT_OPC0_bm Predefined. */
+-/* PORT_OPC0_bp Predefined. */
+-/* PORT_OPC1_bm Predefined. */
+-/* PORT_OPC1_bp Predefined. */
+-/* PORT_OPC2_bm Predefined. */
+-/* PORT_OPC2_bp Predefined. */
+-
+-/* PORT_ISC_gm Predefined. */
+-/* PORT_ISC_gp Predefined. */
+-/* PORT_ISC0_bm Predefined. */
+-/* PORT_ISC0_bp Predefined. */
+-/* PORT_ISC1_bm Predefined. */
+-/* PORT_ISC1_bp Predefined. */
+-/* PORT_ISC2_bm Predefined. */
+-/* PORT_ISC2_bp Predefined. */
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
+
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
+
+ /* TC - 16-bit Timer/Counter With PWM */
+ /* TC0.CTRLA bit masks and bit positions */
+@@ -6448,7 +6684,6 @@
+ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+-
+ /* TC0.CTRLB bit masks and bit positions */
+ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+@@ -6471,7 +6706,6 @@
+ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+-
+ /* TC0.CTRLC bit masks and bit positions */
+ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+@@ -6485,7 +6719,6 @@
+ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+-
+ /* TC0.CTRLD bit masks and bit positions */
+ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+ #define TC0_EVACT_gp 5 /* Event Action group position. */
+@@ -6510,11 +6743,13 @@
+ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+-
+ /* TC0.CTRLE bit masks and bit positions */
+-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+-
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
+
+ /* TC0.INTCTRLA bit masks and bit positions */
+ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+@@ -6531,7 +6766,6 @@
+ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+-
+ /* TC0.INTCTRLB bit masks and bit positions */
+ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+@@ -6561,7 +6795,6 @@
+ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+-
+ /* TC0.CTRLFCLR bit masks and bit positions */
+ #define TC0_CMD_gm 0x0C /* Command group mask. */
+ #define TC0_CMD_gp 2 /* Command group position. */
+@@ -6576,21 +6809,15 @@
+ #define TC0_DIR_bm 0x01 /* Direction bit mask. */
+ #define TC0_DIR_bp 0 /* Direction bit position. */
+
+-
+ /* TC0.CTRLFSET bit masks and bit positions */
+-/* TC0_CMD_gm Predefined. */
+-/* TC0_CMD_gp Predefined. */
+-/* TC0_CMD0_bm Predefined. */
+-/* TC0_CMD0_bp Predefined. */
+-/* TC0_CMD1_bm Predefined. */
+-/* TC0_CMD1_bp Predefined. */
+-
+-/* TC0_LUPD_bm Predefined. */
+-/* TC0_LUPD_bp Predefined. */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
+
+-/* TC0_DIR_bm Predefined. */
+-/* TC0_DIR_bp Predefined. */
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
+
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
+
+ /* TC0.CTRLGCLR bit masks and bit positions */
+ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+@@ -6608,23 +6835,21 @@
+ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+-
+ /* TC0.CTRLGSET bit masks and bit positions */
+-/* TC0_CCDBV_bm Predefined. */
+-/* TC0_CCDBV_bp Predefined. */
+-
+-/* TC0_CCCBV_bm Predefined. */
+-/* TC0_CCCBV_bp Predefined. */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
+
+-/* TC0_CCBBV_bm Predefined. */
+-/* TC0_CCBBV_bp Predefined. */
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
+
+-/* TC0_CCABV_bm Predefined. */
+-/* TC0_CCABV_bp Predefined. */
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
+
+-/* TC0_PERBV_bm Predefined. */
+-/* TC0_PERBV_bp Predefined. */
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
+
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
+
+ /* TC0.INTFLAGS bit masks and bit positions */
+ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+@@ -6645,7 +6870,6 @@
+ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+-
+ /* TC1.CTRLA bit masks and bit positions */
+ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+@@ -6658,7 +6882,6 @@
+ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+-
+ /* TC1.CTRLB bit masks and bit positions */
+ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+@@ -6675,7 +6898,6 @@
+ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+-
+ /* TC1.CTRLC bit masks and bit positions */
+ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+@@ -6683,7 +6905,6 @@
+ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+-
+ /* TC1.CTRLD bit masks and bit positions */
+ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+ #define TC1_EVACT_gp 5 /* Event Action group position. */
+@@ -6708,12 +6929,10 @@
+ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+-
+ /* TC1.CTRLE bit masks and bit positions */
+ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+-
+ /* TC1.INTCTRLA bit masks and bit positions */
+ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+@@ -6729,7 +6948,6 @@
+ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+-
+ /* TC1.INTCTRLB bit masks and bit positions */
+ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+@@ -6745,7 +6963,6 @@
+ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+-
+ /* TC1.CTRLFCLR bit masks and bit positions */
+ #define TC1_CMD_gm 0x0C /* Command group mask. */
+ #define TC1_CMD_gp 2 /* Command group position. */
+@@ -6760,21 +6977,15 @@
+ #define TC1_DIR_bm 0x01 /* Direction bit mask. */
+ #define TC1_DIR_bp 0 /* Direction bit position. */
+
+-
+ /* TC1.CTRLFSET bit masks and bit positions */
+-/* TC1_CMD_gm Predefined. */
+-/* TC1_CMD_gp Predefined. */
+-/* TC1_CMD0_bm Predefined. */
+-/* TC1_CMD0_bp Predefined. */
+-/* TC1_CMD1_bm Predefined. */
+-/* TC1_CMD1_bp Predefined. */
+-
+-/* TC1_LUPD_bm Predefined. */
+-/* TC1_LUPD_bp Predefined. */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
+
+-/* TC1_DIR_bm Predefined. */
+-/* TC1_DIR_bp Predefined. */
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
+
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
+
+ /* TC1.CTRLGCLR bit masks and bit positions */
+ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+@@ -6786,17 +6997,15 @@
+ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+-
+ /* TC1.CTRLGSET bit masks and bit positions */
+-/* TC1_CCBBV_bm Predefined. */
+-/* TC1_CCBBV_bp Predefined. */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
+
+-/* TC1_CCABV_bm Predefined. */
+-/* TC1_CCABV_bp Predefined. */
+-
+-/* TC1_PERBV_bm Predefined. */
+-/* TC1_PERBV_bp Predefined. */
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
+
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
+
+ /* TC1.INTFLAGS bit masks and bit positions */
+ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+@@ -6811,6 +7020,154 @@
+ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
+
+ /* AWEX - Timer/Counter Advanced Waveform Extension */
+ /* AWEX.CTRL bit masks and bit positions */
+@@ -6832,7 +7189,6 @@
+ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+-
+ /* AWEX.FDCTRL bit masks and bit positions */
+ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+@@ -6847,7 +7203,6 @@
+ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+-
+ /* AWEX.STATUS bit masks and bit positions */
+ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+@@ -6858,6 +7213,15 @@
+ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
+
+ /* HIRES - Timer/Counter High-Resolution Extension */
+ /* HIRES.CTRLA bit masks and bit positions */
+@@ -6868,7 +7232,6 @@
+ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+-
+ /* USART - Universal Asynchronous Receiver-Transmitter */
+ /* USART.STATUS bit masks and bit positions */
+ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+@@ -6892,7 +7255,6 @@
+ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+-
+ /* USART.CTRLA bit masks and bit positions */
+ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+@@ -6915,7 +7277,6 @@
+ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+-
+ /* USART.CTRLB bit masks and bit positions */
+ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+@@ -6932,7 +7293,6 @@
+ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+-
+ /* USART.CTRLC bit masks and bit positions */
+ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+ #define USART_CMODE_gp 6 /* Communication Mode group position. */
+@@ -6960,7 +7320,6 @@
+ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+-
+ /* USART.BAUDCTRLA bit masks and bit positions */
+ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+@@ -6981,7 +7340,6 @@
+ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+-
+ /* USART.BAUDCTRLB bit masks and bit positions */
+ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+@@ -6994,17 +7352,8 @@
+ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+-/* USART_BSEL_gm Predefined. */
+-/* USART_BSEL_gp Predefined. */
+-/* USART_BSEL0_bm Predefined. */
+-/* USART_BSEL0_bp Predefined. */
+-/* USART_BSEL1_bm Predefined. */
+-/* USART_BSEL1_bp Predefined. */
+-/* USART_BSEL2_bm Predefined. */
+-/* USART_BSEL2_bp Predefined. */
+-/* USART_BSEL3_bm Predefined. */
+-/* USART_BSEL3_bp Predefined. */
+-
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
+
+ /* SPI - Serial Peripheral Interface */
+ /* SPI.CTRL bit masks and bit positions */
+@@ -7034,7 +7383,6 @@
+ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+-
+ /* SPI.INTCTRL bit masks and bit positions */
+ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+@@ -7043,7 +7391,6 @@
+ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+-
+ /* SPI.STATUS bit masks and bit positions */
+ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+@@ -7051,7 +7398,6 @@
+ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+-
+ /* IRCOM - IR Communication Module */
+ /* IRCOM.CTRL bit masks and bit positions */
+ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+@@ -7065,34 +7411,152 @@
+ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+-
+-/* PRESC - Prescaler */
+-/* PRESC.PRESCALER bit masks and bit positions */
+-#define PRESC_RESET_bm 0x01 /* Reset bit mask. */
+-#define PRESC_RESET_bp 0 /* Reset bit position. */
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+
+ // Generic Port Pins
+
+-#define PIN0_bm 0x01
++#define PIN0_bm 0x01
+ #define PIN0_bp 0
+ #define PIN1_bm 0x02
+ #define PIN1_bp 1
+-#define PIN2_bm 0x04
++#define PIN2_bm 0x04
+ #define PIN2_bp 2
+-#define PIN3_bm 0x08
++#define PIN3_bm 0x08
+ #define PIN3_bp 3
+-#define PIN4_bm 0x10
++#define PIN4_bm 0x10
+ #define PIN4_bp 4
+-#define PIN5_bm 0x20
++#define PIN5_bm 0x20
+ #define PIN5_bp 5
+-#define PIN6_bm 0x40
++#define PIN6_bm 0x40
+ #define PIN6_bp 6
+-#define PIN7_bm 0x80
++#define PIN7_bm 0x80
+ #define PIN7_bp 7
+
+-
+ /* ========== Interrupt Vector Definitions ========== */
+ /* Vector 0 is the reset vector */
+
+@@ -7137,17 +7601,51 @@
+ /* TCC0 interrupt vectors */
+ #define TCC0_OVF_vect_num 14
+ #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_ERR_vect_num 15
+ #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCA_vect_num 16
+ #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCB_vect_num 17
+ #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCC_vect_num 18
+ #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
+ #define TCC0_CCD_vect_num 19
+ #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
+ /* TCC1 interrupt vectors */
+ #define TCC1_OVF_vect_num 20
+ #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+@@ -7183,10 +7681,10 @@
+ #define AES_INT_vect _VECTOR(31) /* AES Interrupt */
+
+ /* NVM interrupt vectors */
+-#define NVM_SPM_vect_num 32
+-#define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */
+-#define NVM_EE_vect_num 33
+-#define NVM_EE_vect _VECTOR(33) /* EE Interrupt */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+ /* PORTB interrupt vectors */
+ #define PORTB_INT0_vect_num 34
+@@ -7227,17 +7725,51 @@
+ /* TCE0 interrupt vectors */
+ #define TCE0_OVF_vect_num 47
+ #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_ERR_vect_num 48
+ #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCA_vect_num 49
+ #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCB_vect_num 50
+ #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCC_vect_num 51
+ #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
+ #define TCE0_CCD_vect_num 52
+ #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
+ /* TCE1 interrupt vectors */
+ #define TCE1_OVF_vect_num 53
+ #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
+@@ -7307,17 +7839,51 @@
+ /* TCD0 interrupt vectors */
+ #define TCD0_OVF_vect_num 77
+ #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_ERR_vect_num 78
+ #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCA_vect_num 79
+ #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCB_vect_num 80
+ #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCC_vect_num 81
+ #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
+ #define TCD0_CCD_vect_num 82
+ #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
+ /* TCD1 interrupt vectors */
+ #define TCD1_OVF_vect_num 83
+ #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
+@@ -7387,17 +7953,51 @@
+ /* TCF0 interrupt vectors */
+ #define TCF0_OVF_vect_num 108
+ #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_ERR_vect_num 109
+ #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCA_vect_num 110
+ #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCB_vect_num 111
+ #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCC_vect_num 112
+ #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
+ #define TCF0_CCD_vect_num 113
+ #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
+ /* TCF1 interrupt vectors */
+ #define TCF1_OVF_vect_num 114
+ #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */
+@@ -7430,45 +8030,37 @@
+
+ /* USB interrupt vectors */
+ #define USB_BUSEVENT_vect_num 125
+-#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */
+-#define USB_TRNCOMPL_vect_num 127
+-#define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */
+-
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
+
+ #define _VECTOR_SIZE 4 /* Size of individual vector. */
+-#define _VECTORS_SIZE (128 * _VECTOR_SIZE)
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
+
+
+ /* ========== Constants ========== */
+
+-#define PROGMEM_START (0x00000)
++#define PROGMEM_START (0x0000)
+ #define PROGMEM_SIZE (69632)
+-#define PROGMEM_PAGE_SIZE (512)
+ #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+-#define APP_SECTION_START (0x00000)
++#define APP_SECTION_START (0x0000)
+ #define APP_SECTION_SIZE (65536)
+-#define APP_SECTION_PAGE_SIZE (512)
++#define APP_SECTION_PAGE_SIZE (256)
+ #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+-#define APPTABLE_SECTION_START (0x1E000)
++#define APPTABLE_SECTION_START (0xF000)
+ #define APPTABLE_SECTION_SIZE (4096)
+-#define APPTABLE_SECTION_PAGE_SIZE (512)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
+ #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+-#define BOOT_SECTION_START (0x20000)
++#define BOOT_SECTION_START (0x10000)
+ #define BOOT_SECTION_SIZE (4096)
+-#define BOOT_SECTION_PAGE_SIZE (512)
++#define BOOT_SECTION_PAGE_SIZE (256)
+ #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+-#define EEPROM_START (0x0000)
+-#define EEPROM_SIZE (2048)
+-#define EEPROM_PAGE_SIZE (32)
+-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+-
+ #define DATAMEM_START (0x0000)
+ #define DATAMEM_SIZE (16777216)
+-#define DATAMEM_PAGE_SIZE (0)
+ #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+ #define IO_START (0x0000)
+@@ -7486,51 +8078,95 @@
+ #define INTERNAL_SRAM_PAGE_SIZE (0)
+ #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+-#define EXTERNAL_SRAM_START (0x4000)
+-#define EXTERNAL_SRAM_SIZE (16760832)
+-#define EXTERNAL_SRAM_PAGE_SIZE (0)
+-#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)
+-
+-#define FUSE_START (0x0000)
+-#define FUSE_SIZE (6)
+-#define FUSE_PAGE_SIZE (0)
+-#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+-
+-#define LOCKBIT_START (0x0000)
+-#define LOCKBIT_SIZE (1)
+-#define LOCKBIT_PAGE_SIZE (0)
+-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+ #define SIGNATURES_START (0x0000)
+ #define SIGNATURES_SIZE (3)
+ #define SIGNATURES_PAGE_SIZE (0)
+ #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
+ #define USER_SIGNATURES_START (0x0000)
+-#define USER_SIGNATURES_SIZE (512)
+-#define USER_SIGNATURES_PAGE_SIZE (0)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
+ #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+ #define PROD_SIGNATURES_START (0x0000)
+-#define PROD_SIGNATURES_SIZE (52)
+-#define PROD_SIGNATURES_PAGE_SIZE (0)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
+ #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+ #define FLASHEND PROGMEM_END
+-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
++#define SPM_PAGESIZE 256
+ #define RAMSTART INTERNAL_SRAM_START
+ #define RAMSIZE INTERNAL_SRAM_SIZE
+ #define RAMEND INTERNAL_SRAM_END
+-#define XRAMSTART EXTERNAL_SRAM_START
+-#define XRAMSIZE EXTERNAL_SRAM_SIZE
+-#define XRAMEND EXTERNAL_SRAM_END
+ #define E2END EEPROM_END
+ #define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+ /* ========== Fuses ========== */
+-#define FUSE_MEMORY_SIZE 0
++#define FUSE_MEMORY_SIZE 6
+
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
+
+ /* ========== Lock Bits ========== */
+ #define __LOCK_BITS_EXIST
+@@ -7538,12 +8174,11 @@
+ #define __BOOT_LOCK_APPLICATION_BITS_EXIST
+ #define __BOOT_LOCK_BOOT_BITS_EXIST
+
+-
+ /* ========== Signature ========== */
+ #define SIGNATURE_0 0x1E
+ #define SIGNATURE_1 0x96
+ #define SIGNATURE_2 0x4E
+
+
+-#endif /* _AVR_ATxmega64A1U_H_ */
++#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */
+
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64a3u.h avr-libc-1.8.0/include/avr/iox64a3u.h
+--- avr-libc-1.8.0.orig/include/avr/iox64a3u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64a3u.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,7588 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64a3u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64A3U_H_INCLUDED
++#define _AVR_ATXMEGA64A3U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */
++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */
++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CH1RES _SFR_MEM16(0x0252)
++#define ADCB_CH2RES _SFR_MEM16(0x0254)
++#define ADCB_CH3RES _SFR_MEM16(0x0256)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
++#define ADCB_CH1_RES _SFR_MEM16(0x026C)
++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E)
++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
++#define ADCB_CH2_RES _SFR_MEM16(0x0274)
++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276)
++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
++#define ADCB_CH3_RES _SFR_MEM16(0x027C)
++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCE1_CTRLA _SFR_MEM8(0x0A40)
++#define TCE1_CTRLB _SFR_MEM8(0x0A41)
++#define TCE1_CTRLC _SFR_MEM8(0x0A42)
++#define TCE1_CTRLD _SFR_MEM8(0x0A43)
++#define TCE1_CTRLE _SFR_MEM8(0x0A44)
++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
++#define TCE1_TEMP _SFR_MEM8(0x0A4F)
++#define TCE1_CNT _SFR_MEM16(0x0A60)
++#define TCE1_PER _SFR_MEM16(0x0A66)
++#define TCE1_CCA _SFR_MEM16(0x0A68)
++#define TCE1_CCB _SFR_MEM16(0x0A6A)
++#define TCE1_PERBUF _SFR_MEM16(0x0A76)
++#define TCE1_CCABUF _SFR_MEM16(0x0A78)
++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXE_CTRL _SFR_MEM8(0x0A80)
++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
++#define AWEXE_STATUS _SFR_MEM8(0x0A84)
++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85)
++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
++#define AWEXE_DTLS _SFR_MEM8(0x0A88)
++#define AWEXE_DTHS _SFR_MEM8(0x0A89)
++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE1_DATA _SFR_MEM8(0x0AB0)
++#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIE_CTRL _SFR_MEM8(0x0AC0)
++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
++#define SPIE_STATUS _SFR_MEM8(0x0AC2)
++#define SPIE_DATA _SFR_MEM8(0x0AC3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTF0_DATA _SFR_MEM8(0x0BA0)
++#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 36
++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 37
++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 38
++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 39
++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
++#define ADCB_CH1_vect_num 40
++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
++#define ADCB_CH2_vect_num 41
++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
++#define ADCB_CH3_vect_num 42
++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* TCE1 interrupt vectors */
++#define TCE1_OVF_vect_num 53
++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
++#define TCE1_ERR_vect_num 54
++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
++#define TCE1_CCA_vect_num 55
++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
++#define TCE1_CCB_vect_num 56
++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
++
++/* SPIE interrupt vectors */
++#define SPIE_INT_vect_num 57
++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* USARTE1 interrupt vectors */
++#define USARTE1_RXC_vect_num 61
++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
++#define USARTE1_DRE_vect_num 62
++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
++#define USARTE1_TXC_vect_num 63
++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USARTF0 interrupt vectors */
++#define USARTF0_RXC_vect_num 119
++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
++#define USARTF0_DRE_vect_num 120
++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
++#define USARTF0_TXC_vect_num 121
++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xF000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x42
++
++
++#endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64a4u.h avr-libc-1.8.0/include/avr/iox64a4u.h
+--- avr-libc-1.8.0.orig/include/avr/iox64a4u.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64a4u.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,7200 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64a4u.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64A4U_H_INCLUDED
++#define _AVR_ATXMEGA64A4U_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t SRCADDR2; /* Channel Source Address 2 */
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t DESTADDR2; /* Channel Destination Address 2 */
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++ DMA_CH_t CH2; /* DMA Channel 2 */
++ DMA_CH_t CH3; /* DMA Channel 3 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ _WORDREGISTER(CH1RES); /* Channel 1 Result */
++ _WORDREGISTER(CH2RES); /* Channel 2 Result */
++ _WORDREGISTER(CH3RES); /* Channel 3 Result */
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++ ADC_CH_t CH1; /* ADC Channel 1 */
++ ADC_CH_t CH2; /* ADC Channel 2 */
++ ADC_CH_t CH3; /* ADC Channel 3 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Current Limitation Mode */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No Current Reduction */
++ ADC_CURRLIMIT_SMALL_gc = (0x01<<5), /* 10% current reduction */
++ ADC_CURRLIMIT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
++ ADC_CURRLIMIT_LARGE_gc = (0x03<<5), /* 30% current reduction */
++} ADC_CURRLIMIT_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Channel sweep selection */
++typedef enum ADC_SWEEP_enum
++{
++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
++} ADC_SWEEP_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* DMA request selection */
++typedef enum ADC_DMASEL_enum
++{
++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
++} ADC_DMASEL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */
++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */
++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */
++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
++#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
++#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
++#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
++#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
++#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
++#define GPIO_GPIORA _SFR_MEM8(0x000A)
++#define GPIO_GPIORB _SFR_MEM8(0x000B)
++#define GPIO_GPIORC _SFR_MEM8(0x000C)
++#define GPIO_GPIORD _SFR_MEM8(0x000D)
++#define GPIO_GPIORE _SFR_MEM8(0x000E)
++#define GPIO_GPIORF _SFR_MEM8(0x000F)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++#define GPIO_GPIO4 _SFR_MEM8(0x0004)
++#define GPIO_GPIO5 _SFR_MEM8(0x0005)
++#define GPIO_GPIO6 _SFR_MEM8(0x0006)
++#define GPIO_GPIO7 _SFR_MEM8(0x0007)
++#define GPIO_GPIO8 _SFR_MEM8(0x0008)
++#define GPIO_GPIO9 _SFR_MEM8(0x0009)
++#define GPIO_GPIOA _SFR_MEM8(0x000A)
++#define GPIO_GPIOB _SFR_MEM8(0x000B)
++#define GPIO_GPIOC _SFR_MEM8(0x000C)
++#define GPIO_GPIOD _SFR_MEM8(0x000D)
++#define GPIO_GPIOE _SFR_MEM8(0x000E)
++#define GPIO_GPIOF _SFR_MEM8(0x000F)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032)
++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036)
++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM16(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CH1RES _SFR_MEM16(0x0212)
++#define ADCA_CH2RES _SFR_MEM16(0x0214)
++#define ADCA_CH3RES _SFR_MEM16(0x0216)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
++#define ADCA_CH1_RES _SFR_MEM16(0x022C)
++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E)
++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
++#define ADCA_CH2_RES _SFR_MEM16(0x0234)
++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236)
++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
++#define ADCA_CH3_RES _SFR_MEM16(0x023C)
++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACB_CTRLA _SFR_MEM8(0x0320)
++#define DACB_CTRLB _SFR_MEM8(0x0321)
++#define DACB_CTRLC _SFR_MEM8(0x0322)
++#define DACB_EVCTRL _SFR_MEM8(0x0323)
++#define DACB_TIMCTRL _SFR_MEM8(0x0324)
++#define DACB_STATUS _SFR_MEM8(0x0325)
++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
++#define DACB_CH0DATA _SFR_MEM16(0x0338)
++#define DACB_CH1DATA _SFR_MEM16(0x033A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC1_DATA _SFR_MEM8(0x08B0)
++#define USARTC1_STATUS _SFR_MEM8(0x08B1)
++#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
++#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
++#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCD1_CTRLA _SFR_MEM8(0x0940)
++#define TCD1_CTRLB _SFR_MEM8(0x0941)
++#define TCD1_CTRLC _SFR_MEM8(0x0942)
++#define TCD1_CTRLD _SFR_MEM8(0x0943)
++#define TCD1_CTRLE _SFR_MEM8(0x0944)
++#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
++#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
++#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
++#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD1_TEMP _SFR_MEM8(0x094F)
++#define TCD1_CNT _SFR_MEM16(0x0960)
++#define TCD1_PER _SFR_MEM16(0x0966)
++#define TCD1_CCA _SFR_MEM16(0x0968)
++#define TCD1_CCB _SFR_MEM16(0x096A)
++#define TCD1_PERBUF _SFR_MEM16(0x0976)
++#define TCD1_CCABUF _SFR_MEM16(0x0978)
++#define TCD1_CCBBUF _SFR_MEM16(0x097A)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESD_CTRLA _SFR_MEM8(0x0990)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD1_DATA _SFR_MEM8(0x09B0)
++#define USARTD1_STATUS _SFR_MEM8(0x09B1)
++#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
++#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
++#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
++#define PR_EBI_bp 3 /* External Bus Interface bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_DAC Predefined. */
++/* PR_DAC Predefined. */
++
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART1 Predefined. */
++/* PR_USART1 Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_HIRES Predefined. */
++/* PR_HIRES Predefined. */
++
++/* PR_TC1 Predefined. */
++/* PR_TC1 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */
++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */
++
++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
++
++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */
++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */
++
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
++
++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
++
++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
++
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
++
++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_QDIRM Predefined. */
++/* EVSYS_QDIRM Predefined. */
++
++/* EVSYS_QDIEN Predefined. */
++/* EVSYS_QDIEN Predefined. */
++
++/* EVSYS_QDEN Predefined. */
++/* EVSYS_QDEN Predefined. */
++
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
++
++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
++
++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
++
++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
++
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */
++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */
++
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
++
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
++
++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
++
++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
++
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HSMODE Predefined. */
++/* AC_HSMODE Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++#define DMA_CH2_vect_num 8
++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
++#define DMA_CH3_vect_num 9
++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USARTC1 interrupt vectors */
++#define USARTC1_RXC_vect_num 28
++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
++#define USARTC1_DRE_vect_num 29
++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
++#define USARTC1_TXC_vect_num 30
++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 31
++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++#define ADCA_CH1_vect_num 72
++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
++#define ADCA_CH2_vect_num 73
++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
++#define ADCA_CH3_vect_num 74
++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* TCD1 interrupt vectors */
++#define TCD1_OVF_vect_num 83
++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
++#define TCD1_ERR_vect_num 84
++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
++#define TCD1_CCA_vect_num 85
++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
++#define TCD1_CCB_vect_num 86
++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* USARTD1 interrupt vectors */
++#define USARTD1_RXC_vect_num 91
++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
++#define USARTD1_DRE_vect_num 92
++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
++#define USARTD1_TXC_vect_num 93
++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xF000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x46
++
++
++#endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64b1.h avr-libc-1.8.0/include/avr/iox64b1.h
+--- avr-libc-1.8.0.orig/include/avr/iox64b1.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64b1.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,6360 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64b1.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64B1_H_INCLUDED
++#define _AVR_ATXMEGA64B1_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++PR - Power Reduction
++--------------------------------------------------------------------------
++*/
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t reserved_0x04;
++ register8_t PRPE; /* Power Reduction Port E */
++} PR_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */
++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */
++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LCD - LCD Controller
++--------------------------------------------------------------------------
++*/
++
++/* LCD Controller */
++typedef struct LCD_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t INTCTRL; /* Interrupt Enable Register */
++ register8_t INTFLAG; /* Interrupt Flag Register */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t CTRLH; /* Control Register H */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t DATA0; /* LCD Data Register 0 */
++ register8_t DATA1; /* LCD Data Register 1 */
++ register8_t DATA2; /* LCD Data Register 2 */
++ register8_t DATA3; /* LCD Data Register 3 */
++ register8_t DATA4; /* LCD Data Register 4 */
++ register8_t DATA5; /* LCD Data Register 5 */
++ register8_t DATA6; /* LCD Data Register 6 */
++ register8_t DATA7; /* LCD Data Register 7 */
++ register8_t DATA8; /* LCD Data Register 8 */
++ register8_t DATA9; /* LCD Data Register 9 */
++ register8_t DATA10; /* LCD Data Register 10 */
++ register8_t DATA11; /* LCD Data Register 11 */
++ register8_t DATA12; /* LCD Data Register 12 */
++ register8_t DATA13; /* LCD Data Register 13 */
++ register8_t DATA14; /* LCD Data Register 14 */
++ register8_t DATA15; /* LCD Data Register 15 */
++ register8_t DATA16; /* LCD Data Register 16 */
++ register8_t DATA17; /* LCD Data Register 17 */
++ register8_t DATA18; /* LCD Data Register 18 */
++ register8_t DATA19; /* LCD Data Register 19 */
++} LCD_t;
++
++/* LCD Blink Rate */
++typedef enum LCD_BLINKRATE_enum
++{
++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */
++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */
++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */
++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */
++} LCD_BLINKRATE_t;
++
++/* LCD Clock Divide */
++typedef enum LCD_CLKDIV_enum
++{
++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */
++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */
++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */
++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */
++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */
++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */
++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */
++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */
++} LCD_CLKDIV_t;
++
++/* Duty Select */
++typedef enum LCD_DUTY_enum
++{
++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */
++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */
++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */
++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */
++} LCD_DUTY_t;
++
++/* LCD Prescaler Select */
++typedef enum LCD_PRESC_enum
++{
++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */
++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */
++} LCD_PRESC_t;
++
++/* Type of Digit */
++typedef enum LCD_TDG_enum
++{
++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */
++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */
++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */
++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */
++} LCD_TDG_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */
++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPE _SFR_MEM8(0x0075)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM8(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++#define ACA_CURRCTRL _SFR_MEM8(0x0388)
++#define ACA_CURRCALIB _SFR_MEM8(0x0389)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++#define ACB_CURRCTRL _SFR_MEM8(0x0398)
++#define ACB_CURRCALIB _SFR_MEM8(0x0399)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTG_DIR _SFR_MEM8(0x06C0)
++#define PORTG_DIRSET _SFR_MEM8(0x06C1)
++#define PORTG_DIRCLR _SFR_MEM8(0x06C2)
++#define PORTG_DIRTGL _SFR_MEM8(0x06C3)
++#define PORTG_OUT _SFR_MEM8(0x06C4)
++#define PORTG_OUTSET _SFR_MEM8(0x06C5)
++#define PORTG_OUTCLR _SFR_MEM8(0x06C6)
++#define PORTG_OUTTGL _SFR_MEM8(0x06C7)
++#define PORTG_IN _SFR_MEM8(0x06C8)
++#define PORTG_INTCTRL _SFR_MEM8(0x06C9)
++#define PORTG_INT0MASK _SFR_MEM8(0x06CA)
++#define PORTG_INT1MASK _SFR_MEM8(0x06CB)
++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC)
++#define PORTG_REMAP _SFR_MEM8(0x06CE)
++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0)
++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1)
++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2)
++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3)
++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4)
++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5)
++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6)
++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7)
++
++/* PORT - I/O Ports */
++#define PORTM_DIR _SFR_MEM8(0x0760)
++#define PORTM_DIRSET _SFR_MEM8(0x0761)
++#define PORTM_DIRCLR _SFR_MEM8(0x0762)
++#define PORTM_DIRTGL _SFR_MEM8(0x0763)
++#define PORTM_OUT _SFR_MEM8(0x0764)
++#define PORTM_OUTSET _SFR_MEM8(0x0765)
++#define PORTM_OUTCLR _SFR_MEM8(0x0766)
++#define PORTM_OUTTGL _SFR_MEM8(0x0767)
++#define PORTM_IN _SFR_MEM8(0x0768)
++#define PORTM_INTCTRL _SFR_MEM8(0x0769)
++#define PORTM_INT0MASK _SFR_MEM8(0x076A)
++#define PORTM_INT1MASK _SFR_MEM8(0x076B)
++#define PORTM_INTFLAGS _SFR_MEM8(0x076C)
++#define PORTM_REMAP _SFR_MEM8(0x076E)
++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770)
++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771)
++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772)
++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773)
++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774)
++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775)
++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776)
++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* LCD - LCD Controller */
++#define LCD_CTRLA _SFR_MEM8(0x0D00)
++#define LCD_CTRLB _SFR_MEM8(0x0D01)
++#define LCD_CTRLC _SFR_MEM8(0x0D02)
++#define LCD_INTCTRL _SFR_MEM8(0x0D03)
++#define LCD_INTFLAG _SFR_MEM8(0x0D04)
++#define LCD_CTRLD _SFR_MEM8(0x0D05)
++#define LCD_CTRLE _SFR_MEM8(0x0D06)
++#define LCD_CTRLF _SFR_MEM8(0x0D07)
++#define LCD_CTRLG _SFR_MEM8(0x0D08)
++#define LCD_CTRLH _SFR_MEM8(0x0D09)
++#define LCD_DATA0 _SFR_MEM8(0x0D10)
++#define LCD_DATA1 _SFR_MEM8(0x0D11)
++#define LCD_DATA2 _SFR_MEM8(0x0D12)
++#define LCD_DATA3 _SFR_MEM8(0x0D13)
++#define LCD_DATA4 _SFR_MEM8(0x0D14)
++#define LCD_DATA5 _SFR_MEM8(0x0D15)
++#define LCD_DATA6 _SFR_MEM8(0x0D16)
++#define LCD_DATA7 _SFR_MEM8(0x0D17)
++#define LCD_DATA8 _SFR_MEM8(0x0D18)
++#define LCD_DATA9 _SFR_MEM8(0x0D19)
++#define LCD_DATA10 _SFR_MEM8(0x0D1A)
++#define LCD_DATA11 _SFR_MEM8(0x0D1B)
++#define LCD_DATA12 _SFR_MEM8(0x0D1C)
++#define LCD_DATA13 _SFR_MEM8(0x0D1D)
++#define LCD_DATA14 _SFR_MEM8(0x0D1E)
++#define LCD_DATA15 _SFR_MEM8(0x0D1F)
++#define LCD_DATA16 _SFR_MEM8(0x0D20)
++#define LCD_DATA17 _SFR_MEM8(0x0D21)
++#define LCD_DATA18 _SFR_MEM8(0x0D22)
++#define LCD_DATA19 _SFR_MEM8(0x0D23)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* PR - Power Reduction */
++/* PR.PRGEN bit masks and bit positions */
++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */
++#define PR_LCD_bp 7 /* LCD Module bit position. */
++
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */
++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */
++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */
++
++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */
++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */
++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* LCD - LCD Controller */
++/* LCD.CTRLA bit masks and bit positions */
++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */
++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */
++
++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */
++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */
++
++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */
++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */
++
++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */
++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */
++
++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */
++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */
++
++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */
++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */
++
++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */
++#define LCD_SEGON_bp 1 /* Segments On bit position. */
++
++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */
++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */
++
++/* LCD.CTRLB bit masks and bit positions */
++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */
++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */
++
++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */
++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */
++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */
++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */
++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */
++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */
++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */
++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */
++
++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */
++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */
++
++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */
++#define LCD_DUTY_gp 0 /* Duty Select group position. */
++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */
++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */
++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */
++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */
++
++/* LCD.CTRLC bit masks and bit positions */
++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */
++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */
++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */
++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */
++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */
++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */
++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */
++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */
++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */
++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */
++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */
++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */
++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */
++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */
++
++/* LCD.INTCTRL bit masks and bit positions */
++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */
++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */
++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */
++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */
++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */
++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */
++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */
++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */
++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */
++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */
++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */
++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */
++
++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */
++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* LCD.INTFLAG bit masks and bit positions */
++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */
++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */
++
++/* LCD.CTRLD bit masks and bit positions */
++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */
++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */
++
++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */
++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */
++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */
++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */
++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */
++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */
++
++/* LCD.CTRLE bit masks and bit positions */
++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */
++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */
++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */
++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */
++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */
++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */
++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */
++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */
++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */
++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */
++
++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */
++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */
++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */
++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */
++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */
++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */
++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */
++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */
++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */
++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */
++
++/* LCD.CTRLF bit masks and bit positions */
++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */
++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */
++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */
++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */
++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */
++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */
++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */
++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */
++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */
++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */
++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */
++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */
++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */
++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */
++
++/* LCD.CTRLG bit masks and bit positions */
++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */
++#define LCD_TDG_gp 6 /* Type of Digit group position. */
++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */
++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */
++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */
++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */
++
++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */
++#define LCD_STSEG_gp 0 /* Start Segment group position. */
++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */
++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */
++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */
++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */
++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */
++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */
++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */
++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */
++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */
++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */
++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */
++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */
++
++/* LCD.CTRLH bit masks and bit positions */
++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */
++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */
++
++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */
++#define LCD_DCODE_gp 0 /* Display Code group position. */
++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */
++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */
++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */
++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */
++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */
++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */
++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */
++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */
++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */
++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */
++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */
++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */
++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */
++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 31
++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 32
++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */
++
++/* LCD interrupt vectors */
++#define LCD_INT_vect_num 35
++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 36
++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 37
++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */
++#define NVM_SPM_vect_num 38
++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 39
++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 40
++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 41
++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 42
++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 43
++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 44
++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 48
++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 49
++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */
++
++/* PORTG interrupt vectors */
++#define PORTG_INT0_vect_num 50
++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */
++#define PORTG_INT1_vect_num 51
++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */
++
++/* PORTM interrupt vectors */
++#define PORTM_INT0_vect_num 52
++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */
++#define PORTM_INT1_vect_num 53
++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 54
++#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 55
++#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 58
++#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 59
++#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */
++#define TCE0_CCA_vect_num 60
++#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 61
++#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 62
++#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 63
++#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 69
++#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 70
++#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 71
++#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 75
++#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 76
++#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 77
++#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 78
++#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 79
++#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 80
++#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (81 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xF000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x52
++
++
++#endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64b3.h avr-libc-1.8.0/include/avr/iox64b3.h
+--- avr-libc-1.8.0.orig/include/avr/iox64b3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64b3.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,6194 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64b3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64B3_H_INCLUDED
++#define _AVR_ATXMEGA64B3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */
++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++PR - Power Reduction
++--------------------------------------------------------------------------
++*/
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t PRPB; /* Power Reduction Port B */
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t reserved_0x04;
++ register8_t PRPE; /* Power Reduction Port E */
++} PR_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t JTAGUID; /* JTAG User ID */
++ register8_t reserved_0x05;
++ register8_t MCUCR; /* MCU Control */
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */
++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */
++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */
++} PORTCFG_EVOUT_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++AES - AES Module
++--------------------------------------------------------------------------
++*/
++
++/* AES Module */
++typedef struct AES_struct
++{
++ register8_t CTRL; /* AES Control Register */
++ register8_t STATUS; /* AES Status Register */
++ register8_t STATE; /* AES State Register */
++ register8_t KEY; /* AES Key Register */
++ register8_t INTCTRL; /* AES Interrupt Control Register */
++} AES_t;
++
++/* Interrupt level */
++typedef enum AES_INTLVL_enum
++{
++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} AES_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++DMA - DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* DMA Channel */
++typedef struct DMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Address Control */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
++ register8_t REPCNT; /* Channel Repeat Count */
++ register8_t reserved_0x07;
++ register8_t SRCADDR0; /* Channel Source Address 0 */
++ register8_t SRCADDR1; /* Channel Source Address 1 */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDR0; /* Channel Destination Address 0 */
++ register8_t DESTADDR1; /* Channel Destination Address 1 */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} DMA_CH_t;
++
++
++/* DMA Controller */
++typedef struct DMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ DMA_CH_t CH0; /* DMA Channel 0 */
++ DMA_CH_t CH1; /* DMA Channel 1 */
++} DMA_t;
++
++/* Burst mode */
++typedef enum DMA_CH_BURSTLEN_enum
++{
++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
++} DMA_CH_BURSTLEN_t;
++
++/* Source address reload mode */
++typedef enum DMA_CH_SRCRELOAD_enum
++{
++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
++} DMA_CH_SRCRELOAD_t;
++
++/* Source addressing mode */
++typedef enum DMA_CH_SRCDIR_enum
++{
++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
++} DMA_CH_SRCDIR_t;
++
++/* Destination adress reload mode */
++typedef enum DMA_CH_DESTRELOAD_enum
++{
++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
++} DMA_CH_DESTRELOAD_t;
++
++/* Destination adressing mode */
++typedef enum DMA_CH_DESTDIR_enum
++{
++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
++} DMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum DMA_CH_TRIGSRC_enum
++{
++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
++} DMA_CH_TRIGSRC_t;
++
++/* Double buffering mode */
++typedef enum DMA_DBUFMODE_enum
++{
++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
++} DMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum DMA_PRIMODE_enum
++{
++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */
++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */
++} DMA_PRIMODE_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_ERRINTLVL_enum
++{
++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
++} DMA_CH_ERRINTLVL_t;
++
++/* Interrupt level */
++typedef enum DMA_CH_TRNINTLVL_enum
++{
++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
++} DMA_CH_TRNINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_CURRENTLIMITS_enum
++{
++ ADC_CURRENTLIMITS_NO_gc = (0x00<<5), /* No limit */
++ ADC_CURRENTLIMITS_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 225kSPS */
++ ADC_CURRENTLIMITS_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 150kSPS */
++ ADC_CURRENTLIMITS_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 75kSPS */
++} ADC_CURRENTLIMITS_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LCD - LCD Controller
++--------------------------------------------------------------------------
++*/
++
++/* LCD Controller */
++typedef struct LCD_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t INTCTRL; /* Interrupt Enable Register */
++ register8_t INTFLAG; /* Interrupt Flag Register */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t CTRLH; /* Control Register H */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t DATA0; /* LCD Data Register 0 */
++ register8_t DATA1; /* LCD Data Register 1 */
++ register8_t DATA2; /* LCD Data Register 2 */
++ register8_t DATA3; /* LCD Data Register 3 */
++ register8_t DATA4; /* LCD Data Register 4 */
++ register8_t DATA5; /* LCD Data Register 5 */
++ register8_t DATA6; /* LCD Data Register 6 */
++ register8_t DATA7; /* LCD Data Register 7 */
++ register8_t DATA8; /* LCD Data Register 8 */
++ register8_t DATA9; /* LCD Data Register 9 */
++ register8_t DATA10; /* LCD Data Register 10 */
++ register8_t DATA11; /* LCD Data Register 11 */
++ register8_t DATA12; /* LCD Data Register 12 */
++ register8_t DATA13; /* LCD Data Register 13 */
++ register8_t DATA14; /* LCD Data Register 14 */
++ register8_t DATA15; /* LCD Data Register 15 */
++ register8_t DATA16; /* LCD Data Register 16 */
++ register8_t DATA17; /* LCD Data Register 17 */
++ register8_t DATA18; /* LCD Data Register 18 */
++ register8_t DATA19; /* LCD Data Register 19 */
++} LCD_t;
++
++/* LCD Blink Rate */
++typedef enum LCD_BLINKRATE_enum
++{
++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */
++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */
++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */
++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */
++} LCD_BLINKRATE_t;
++
++/* LCD Clock Divide */
++typedef enum LCD_CLKDIV_enum
++{
++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */
++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */
++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */
++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */
++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */
++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */
++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */
++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */
++} LCD_CLKDIV_t;
++
++/* Duty Select */
++typedef enum LCD_DUTY_enum
++{
++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */
++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */
++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */
++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */
++} LCD_DUTY_t;
++
++/* LCD Prescaler Select */
++typedef enum LCD_PRESC_enum
++{
++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */
++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */
++} LCD_PRESC_t;
++
++/* Type of Digit */
++typedef enum LCD_TDG_enum
++{
++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */
++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */
++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */
++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */
++} LCD_TDG_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t FUSEBYTE0; /* JTAG User ID */
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++ register8_t reserved_0x40;
++ register8_t reserved_0x41;
++ register8_t reserved_0x42;
++ register8_t reserved_0x43;
++ register8_t reserved_0x44;
++ register8_t reserved_0x45;
++ register8_t reserved_0x46;
++ register8_t reserved_0x47;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define AES (*(AES_t *) 0x00C0) /* AES Module */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */
++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */
++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000)
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024)
++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPB _SFR_MEM8(0x0072)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPE _SFR_MEM8(0x0075)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_JTAGUID _SFR_MEM8(0x0094)
++#define MCU_MCUCR _SFR_MEM8(0x0096)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* AES - AES Module */
++#define AES_CTRL _SFR_MEM8(0x00C0)
++#define AES_STATUS _SFR_MEM8(0x00C1)
++#define AES_STATE _SFR_MEM8(0x00C2)
++#define AES_KEY _SFR_MEM8(0x00C3)
++#define AES_INTCTRL _SFR_MEM8(0x00C4)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* DMA - DMA Controller */
++#define DMA_CTRL _SFR_MEM8(0x0100)
++#define DMA_INTFLAGS _SFR_MEM8(0x0103)
++#define DMA_STATUS _SFR_MEM8(0x0104)
++#define DMA_TEMP _SFR_MEM8(0x0106)
++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCB_CTRLA _SFR_MEM8(0x0240)
++#define ADCB_CTRLB _SFR_MEM8(0x0241)
++#define ADCB_REFCTRL _SFR_MEM8(0x0242)
++#define ADCB_EVCTRL _SFR_MEM8(0x0243)
++#define ADCB_PRESCALER _SFR_MEM8(0x0244)
++#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
++#define ADCB_TEMP _SFR_MEM8(0x0247)
++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248)
++#define ADCB_CAL _SFR_MEM16(0x024C)
++#define ADCB_CH0RES _SFR_MEM16(0x0250)
++#define ADCB_CMP _SFR_MEM16(0x0258)
++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
++#define ADCB_CH0_RES _SFR_MEM16(0x0264)
++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266)
++
++/* AC - Analog Comparator */
++#define ACB_AC0CTRL _SFR_MEM8(0x0390)
++#define ACB_AC1CTRL _SFR_MEM8(0x0391)
++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
++#define ACB_CTRLA _SFR_MEM8(0x0394)
++#define ACB_CTRLB _SFR_MEM8(0x0395)
++#define ACB_WINCTRL _SFR_MEM8(0x0396)
++#define ACB_STATUS _SFR_MEM8(0x0397)
++#define ACB_CURRCTRL _SFR_MEM8(0x0398)
++#define ACB_CURRCALIB _SFR_MEM8(0x0399)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTG_DIR _SFR_MEM8(0x06C0)
++#define PORTG_DIRSET _SFR_MEM8(0x06C1)
++#define PORTG_DIRCLR _SFR_MEM8(0x06C2)
++#define PORTG_DIRTGL _SFR_MEM8(0x06C3)
++#define PORTG_OUT _SFR_MEM8(0x06C4)
++#define PORTG_OUTSET _SFR_MEM8(0x06C5)
++#define PORTG_OUTCLR _SFR_MEM8(0x06C6)
++#define PORTG_OUTTGL _SFR_MEM8(0x06C7)
++#define PORTG_IN _SFR_MEM8(0x06C8)
++#define PORTG_INTCTRL _SFR_MEM8(0x06C9)
++#define PORTG_INT0MASK _SFR_MEM8(0x06CA)
++#define PORTG_INT1MASK _SFR_MEM8(0x06CB)
++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC)
++#define PORTG_REMAP _SFR_MEM8(0x06CE)
++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0)
++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1)
++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2)
++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3)
++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4)
++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5)
++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6)
++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7)
++
++/* PORT - I/O Ports */
++#define PORTM_DIR _SFR_MEM8(0x0760)
++#define PORTM_DIRSET _SFR_MEM8(0x0761)
++#define PORTM_DIRCLR _SFR_MEM8(0x0762)
++#define PORTM_DIRTGL _SFR_MEM8(0x0763)
++#define PORTM_OUT _SFR_MEM8(0x0764)
++#define PORTM_OUTSET _SFR_MEM8(0x0765)
++#define PORTM_OUTCLR _SFR_MEM8(0x0766)
++#define PORTM_OUTTGL _SFR_MEM8(0x0767)
++#define PORTM_IN _SFR_MEM8(0x0768)
++#define PORTM_INTCTRL _SFR_MEM8(0x0769)
++#define PORTM_INT0MASK _SFR_MEM8(0x076A)
++#define PORTM_INT1MASK _SFR_MEM8(0x076B)
++#define PORTM_INTFLAGS _SFR_MEM8(0x076C)
++#define PORTM_REMAP _SFR_MEM8(0x076E)
++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770)
++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771)
++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772)
++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773)
++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774)
++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775)
++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776)
++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* LCD - LCD Controller */
++#define LCD_CTRLA _SFR_MEM8(0x0D00)
++#define LCD_CTRLB _SFR_MEM8(0x0D01)
++#define LCD_CTRLC _SFR_MEM8(0x0D02)
++#define LCD_INTCTRL _SFR_MEM8(0x0D03)
++#define LCD_INTFLAG _SFR_MEM8(0x0D04)
++#define LCD_CTRLD _SFR_MEM8(0x0D05)
++#define LCD_CTRLE _SFR_MEM8(0x0D06)
++#define LCD_CTRLF _SFR_MEM8(0x0D07)
++#define LCD_CTRLG _SFR_MEM8(0x0D08)
++#define LCD_CTRLH _SFR_MEM8(0x0D09)
++#define LCD_DATA0 _SFR_MEM8(0x0D10)
++#define LCD_DATA1 _SFR_MEM8(0x0D11)
++#define LCD_DATA2 _SFR_MEM8(0x0D12)
++#define LCD_DATA3 _SFR_MEM8(0x0D13)
++#define LCD_DATA4 _SFR_MEM8(0x0D14)
++#define LCD_DATA5 _SFR_MEM8(0x0D15)
++#define LCD_DATA6 _SFR_MEM8(0x0D16)
++#define LCD_DATA7 _SFR_MEM8(0x0D17)
++#define LCD_DATA8 _SFR_MEM8(0x0D18)
++#define LCD_DATA9 _SFR_MEM8(0x0D19)
++#define LCD_DATA10 _SFR_MEM8(0x0D1A)
++#define LCD_DATA11 _SFR_MEM8(0x0D1B)
++#define LCD_DATA12 _SFR_MEM8(0x0D1C)
++#define LCD_DATA13 _SFR_MEM8(0x0D1D)
++#define LCD_DATA14 _SFR_MEM8(0x0D1E)
++#define LCD_DATA15 _SFR_MEM8(0x0D1F)
++#define LCD_DATA16 _SFR_MEM8(0x0D20)
++#define LCD_DATA17 _SFR_MEM8(0x0D21)
++#define LCD_DATA18 _SFR_MEM8(0x0D22)
++#define LCD_DATA19 _SFR_MEM8(0x0D23)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* PR - Power Reduction */
++/* PR.PRGEN bit masks and bit positions */
++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */
++#define PR_LCD_bp 7 /* LCD Module bit position. */
++
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPB bit masks and bit positions */
++/* PR_ADC Predefined. */
++/* PR_ADC Predefined. */
++
++/* PR_AC Predefined. */
++/* PR_AC Predefined. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.MCUCR bit masks and bit positions */
++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
++
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */
++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */
++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */
++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */
++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */
++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */
++
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */
++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */
++
++/* AES - AES Module */
++/* AES.CTRL bit masks and bit positions */
++#define AES_START_bm 0x80 /* Start/Run bit mask. */
++#define AES_START_bp 7 /* Start/Run bit position. */
++
++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
++
++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
++#define AES_RESET_bp 5 /* AES Software Reset bit position. */
++
++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
++
++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
++
++/* AES.STATUS bit masks and bit positions */
++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
++#define AES_ERROR_bp 7 /* AES Error bit position. */
++
++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
++
++/* AES.INTCTRL bit masks and bit positions */
++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define AES_INTLVL_gp 0 /* Interrupt level group position. */
++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* DMA - DMA Controller */
++/* DMA_CH.CTRLA bit masks and bit positions */
++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */
++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */
++
++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */
++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */
++
++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
++
++/* DMA_CH.CTRLB bit masks and bit positions */
++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
++
++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
++
++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
++
++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
++
++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
++
++/* DMA_CH.ADDRCTRL bit masks and bit positions */
++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
++
++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
++
++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
++
++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
++
++/* DMA_CH.TRIGSRC bit masks and bit positions */
++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* DMA.CTRL bit masks and bit positions */
++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define DMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define DMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */
++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */
++
++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */
++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */
++
++/* DMA.INTFLAGS bit masks and bit positions */
++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
++
++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* DMA.STATUS bit masks and bit positions */
++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
++
++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
++
++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
++
++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */
++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* LCD - LCD Controller */
++/* LCD.CTRLA bit masks and bit positions */
++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */
++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */
++
++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */
++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */
++
++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */
++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */
++
++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */
++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */
++
++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */
++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */
++
++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */
++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */
++
++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */
++#define LCD_SEGON_bp 1 /* Segments On bit position. */
++
++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */
++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */
++
++/* LCD.CTRLB bit masks and bit positions */
++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */
++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */
++
++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */
++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */
++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */
++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */
++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */
++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */
++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */
++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */
++
++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */
++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */
++
++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */
++#define LCD_DUTY_gp 0 /* Duty Select group position. */
++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */
++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */
++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */
++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */
++
++/* LCD.CTRLC bit masks and bit positions */
++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */
++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */
++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */
++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */
++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */
++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */
++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */
++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */
++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */
++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */
++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */
++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */
++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */
++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */
++
++/* LCD.INTCTRL bit masks and bit positions */
++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */
++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */
++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */
++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */
++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */
++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */
++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */
++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */
++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */
++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */
++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */
++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */
++
++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */
++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* LCD.INTFLAG bit masks and bit positions */
++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */
++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */
++
++/* LCD.CTRLD bit masks and bit positions */
++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */
++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */
++
++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */
++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */
++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */
++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */
++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */
++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */
++
++/* LCD.CTRLE bit masks and bit positions */
++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */
++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */
++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */
++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */
++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */
++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */
++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */
++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */
++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */
++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */
++
++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */
++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */
++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */
++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */
++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */
++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */
++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */
++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */
++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */
++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */
++
++/* LCD.CTRLF bit masks and bit positions */
++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */
++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */
++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */
++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */
++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */
++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */
++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */
++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */
++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */
++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */
++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */
++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */
++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */
++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */
++
++/* LCD.CTRLG bit masks and bit positions */
++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */
++#define LCD_TDG_gp 6 /* Type of Digit group position. */
++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */
++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */
++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */
++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */
++
++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */
++#define LCD_STSEG_gp 0 /* Start Segment group position. */
++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */
++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */
++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */
++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */
++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */
++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */
++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */
++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */
++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */
++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */
++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */
++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */
++
++/* LCD.CTRLH bit masks and bit positions */
++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */
++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */
++
++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */
++#define LCD_DCODE_gp 0 /* Display Code group position. */
++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */
++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */
++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */
++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */
++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */
++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */
++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */
++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */
++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */
++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */
++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */
++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */
++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */
++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* DMA interrupt vectors */
++#define DMA_CH0_vect_num 6
++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
++#define DMA_CH1_vect_num 7
++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 31
++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 32
++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */
++
++/* LCD interrupt vectors */
++#define LCD_INT_vect_num 35
++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */
++
++/* AES interrupt vectors */
++#define AES_INT_vect_num 36
++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 37
++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */
++#define NVM_SPM_vect_num 38
++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 39
++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 40
++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */
++
++/* ACB interrupt vectors */
++#define ACB_AC0_vect_num 41
++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */
++#define ACB_AC1_vect_num 42
++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */
++#define ACB_ACW_vect_num 43
++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */
++
++/* ADCB interrupt vectors */
++#define ADCB_CH0_vect_num 44
++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 48
++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 49
++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */
++
++/* PORTG interrupt vectors */
++#define PORTG_INT0_vect_num 50
++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */
++#define PORTG_INT1_vect_num 51
++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */
++
++/* PORTM interrupt vectors */
++#define PORTM_INT0_vect_num 52
++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */
++#define PORTM_INT1_vect_num 53
++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (54 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xF000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 */
++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
++#define FUSE0_DEFAULT (0xFF)
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x51
++
++
++#endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64c3.h avr-libc-1.8.0/include/avr/iox64c3.h
+--- avr-libc-1.8.0.orig/include/avr/iox64c3.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64c3.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,6145 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64c3.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64C3_H_INCLUDED
++#define _AVR_ATXMEGA64C3_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t USBCTRL; /* USB Control Register */
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++/* USB Prescaler Division Factor */
++typedef enum CLK_USBPSDIV_enum
++{
++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
++} CLK_USBPSDIV_t;
++
++/* USB Clock Source */
++typedef enum CLK_USBSRC_enum
++{
++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */
++} CLK_USBSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++USB - USB
++--------------------------------------------------------------------------
++*/
++
++/* USB Endpoint */
++typedef struct USB_EP_struct
++{
++ register8_t STATUS; /* Endpoint Status */
++ register8_t CTRL; /* Endpoint Control */
++ _WORDREGISTER(CNT); /* USB Endpoint Counter */
++ _WORDREGISTER(DATAPTR); /* Data Pointer */
++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */
++} USB_EP_t;
++
++
++/* Universal Serial Bus */
++typedef struct USB_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t FIFOWP; /* FIFO Write Pointer Register */
++ register8_t FIFORP; /* FIFO Read Pointer Register */
++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t reserved_0x20;
++ register8_t reserved_0x21;
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t CAL0; /* Calibration Byte 0 */
++ register8_t CAL1; /* Calibration Byte 1 */
++} USB_t;
++
++
++/* USB Endpoint Table */
++typedef struct USB_EP_TABLE_struct
++{
++ USB_EP_t EP0OUT; /* Endpoint 0 */
++ USB_EP_t EP0IN; /* Endpoint 0 */
++ USB_EP_t EP1OUT; /* Endpoint 1 */
++ USB_EP_t EP1IN; /* Endpoint 1 */
++ USB_EP_t EP2OUT; /* Endpoint 2 */
++ USB_EP_t EP2IN; /* Endpoint 2 */
++ USB_EP_t EP3OUT; /* Endpoint 3 */
++ USB_EP_t EP3IN; /* Endpoint 3 */
++ USB_EP_t EP4OUT; /* Endpoint 4 */
++ USB_EP_t EP4IN; /* Endpoint 4 */
++ USB_EP_t EP5OUT; /* Endpoint 5 */
++ USB_EP_t EP5IN; /* Endpoint 5 */
++ USB_EP_t EP6OUT; /* Endpoint 6 */
++ USB_EP_t EP6IN; /* Endpoint 6 */
++ USB_EP_t EP7OUT; /* Endpoint 7 */
++ USB_EP_t EP7IN; /* Endpoint 7 */
++ USB_EP_t EP8OUT; /* Endpoint 8 */
++ USB_EP_t EP8IN; /* Endpoint 8 */
++ USB_EP_t EP9OUT; /* Endpoint 9 */
++ USB_EP_t EP9IN; /* Endpoint 9 */
++ USB_EP_t EP10OUT; /* Endpoint 10 */
++ USB_EP_t EP10IN; /* Endpoint 10 */
++ USB_EP_t EP11OUT; /* Endpoint 11 */
++ USB_EP_t EP11IN; /* Endpoint 11 */
++ USB_EP_t EP12OUT; /* Endpoint 12 */
++ USB_EP_t EP12IN; /* Endpoint 12 */
++ USB_EP_t EP13OUT; /* Endpoint 13 */
++ USB_EP_t EP13IN; /* Endpoint 13 */
++ USB_EP_t EP14OUT; /* Endpoint 14 */
++ USB_EP_t EP14IN; /* Endpoint 14 */
++ USB_EP_t EP15OUT; /* Endpoint 15 */
++ USB_EP_t EP15IN; /* Endpoint 15 */
++ register8_t reserved_0x100;
++ register8_t reserved_0x101;
++ register8_t reserved_0x102;
++ register8_t reserved_0x103;
++ register8_t reserved_0x104;
++ register8_t reserved_0x105;
++ register8_t reserved_0x106;
++ register8_t reserved_0x107;
++ register8_t reserved_0x108;
++ register8_t reserved_0x109;
++ register8_t reserved_0x10A;
++ register8_t reserved_0x10B;
++ register8_t reserved_0x10C;
++ register8_t reserved_0x10D;
++ register8_t reserved_0x10E;
++ register8_t reserved_0x10F;
++ register8_t FRAMENUML; /* Frame Number Low Byte */
++ register8_t FRAMENUMH; /* Frame Number High Byte */
++} USB_EP_TABLE_t;
++
++/* Interrupt level */
++typedef enum USB_INTLVL_enum
++{
++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */
++} USB_INTLVL_t;
++
++/* USB Endpoint Type */
++typedef enum USB_EP_TYPE_enum
++{
++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
++} USB_EP_TYPE_t;
++
++/* USB Endpoint Buffersize */
++typedef enum USB_EP_BUFSIZE_enum
++{
++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
++} USB_EP_BUFSIZE_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t USBCAL0; /* USB Calibration Byte 0 */
++ register8_t USBCAL1; /* USB Calibration Byte 1 */
++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */
++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */
++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */
++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A)
++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B)
++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C)
++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++#define CLK_USBCTRL _SFR_MEM8(0x0044)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* USB - Universal Serial Bus */
++#define USB_CTRLA _SFR_MEM8(0x04C0)
++#define USB_CTRLB _SFR_MEM8(0x04C1)
++#define USB_STATUS _SFR_MEM8(0x04C2)
++#define USB_ADDR _SFR_MEM8(0x04C3)
++#define USB_FIFOWP _SFR_MEM8(0x04C4)
++#define USB_FIFORP _SFR_MEM8(0x04C5)
++#define USB_EPPTR _SFR_MEM16(0x04C6)
++#define USB_INTCTRLA _SFR_MEM8(0x04C8)
++#define USB_INTCTRLB _SFR_MEM8(0x04C9)
++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
++#define USB_CAL0 _SFR_MEM8(0x04FA)
++#define USB_CAL1 _SFR_MEM8(0x04FB)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTF_DIR _SFR_MEM8(0x06A0)
++#define PORTF_DIRSET _SFR_MEM8(0x06A1)
++#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
++#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
++#define PORTF_OUT _SFR_MEM8(0x06A4)
++#define PORTF_OUTSET _SFR_MEM8(0x06A5)
++#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
++#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
++#define PORTF_IN _SFR_MEM8(0x06A8)
++#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
++#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
++#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
++#define PORTF_REMAP _SFR_MEM8(0x06AE)
++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCE2_CTRLA _SFR_MEM8(0x0A00)
++#define TCE2_CTRLB _SFR_MEM8(0x0A01)
++#define TCE2_CTRLC _SFR_MEM8(0x0A02)
++#define TCE2_CTRLE _SFR_MEM8(0x0A04)
++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE2_CTRLF _SFR_MEM8(0x0A09)
++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE2_LCNT _SFR_MEM8(0x0A20)
++#define TCE2_HCNT _SFR_MEM8(0x0A21)
++#define TCE2_LPER _SFR_MEM8(0x0A26)
++#define TCE2_HPER _SFR_MEM8(0x0A27)
++#define TCE2_LCMPA _SFR_MEM8(0x0A28)
++#define TCE2_HCMPA _SFR_MEM8(0x0A29)
++#define TCE2_LCMPB _SFR_MEM8(0x0A2A)
++#define TCE2_HCMPB _SFR_MEM8(0x0A2B)
++#define TCE2_LCMPC _SFR_MEM8(0x0A2C)
++#define TCE2_HCMPC _SFR_MEM8(0x0A2D)
++#define TCE2_LCMPD _SFR_MEM8(0x0A2E)
++#define TCE2_HCMPD _SFR_MEM8(0x0A2F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTE0_DATA _SFR_MEM8(0x0AA0)
++#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCF0_CTRLA _SFR_MEM8(0x0B00)
++#define TCF0_CTRLB _SFR_MEM8(0x0B01)
++#define TCF0_CTRLC _SFR_MEM8(0x0B02)
++#define TCF0_CTRLD _SFR_MEM8(0x0B03)
++#define TCF0_CTRLE _SFR_MEM8(0x0B04)
++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF0_TEMP _SFR_MEM8(0x0B0F)
++#define TCF0_CNT _SFR_MEM16(0x0B20)
++#define TCF0_PER _SFR_MEM16(0x0B26)
++#define TCF0_CCA _SFR_MEM16(0x0B28)
++#define TCF0_CCB _SFR_MEM16(0x0B2A)
++#define TCF0_CCC _SFR_MEM16(0x0B2C)
++#define TCF0_CCD _SFR_MEM16(0x0B2E)
++#define TCF0_PERBUF _SFR_MEM16(0x0B36)
++#define TCF0_CCABUF _SFR_MEM16(0x0B38)
++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCF2_CTRLA _SFR_MEM8(0x0B00)
++#define TCF2_CTRLB _SFR_MEM8(0x0B01)
++#define TCF2_CTRLC _SFR_MEM8(0x0B02)
++#define TCF2_CTRLE _SFR_MEM8(0x0B04)
++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06)
++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07)
++#define TCF2_CTRLF _SFR_MEM8(0x0B09)
++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C)
++#define TCF2_LCNT _SFR_MEM8(0x0B20)
++#define TCF2_HCNT _SFR_MEM8(0x0B21)
++#define TCF2_LPER _SFR_MEM8(0x0B26)
++#define TCF2_HPER _SFR_MEM8(0x0B27)
++#define TCF2_LCMPA _SFR_MEM8(0x0B28)
++#define TCF2_HCMPA _SFR_MEM8(0x0B29)
++#define TCF2_LCMPB _SFR_MEM8(0x0B2A)
++#define TCF2_HCMPB _SFR_MEM8(0x0B2B)
++#define TCF2_LCMPC _SFR_MEM8(0x0B2C)
++#define TCF2_HCMPC _SFR_MEM8(0x0B2D)
++#define TCF2_LCMPD _SFR_MEM8(0x0B2E)
++#define TCF2_HCMPD _SFR_MEM8(0x0B2F)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* CLK.USBCTRL bit masks and bit positions */
++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */
++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */
++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */
++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */
++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */
++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */
++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */
++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */
++
++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */
++#define CLK_USBSRC_gp 1 /* Clock Source group position. */
++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */
++
++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_USB_bm 0x40 /* USB bit mask. */
++#define PR_USB_bp 6 /* USB bit position. */
++
++#define PR_AES_bm 0x10 /* AES bit mask. */
++#define PR_AES_bp 4 /* AES bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
++#define PR_DMA_bp 0 /* DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
++#define PR_USART1_bp 5 /* Port C USART1 bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* USB - USB */
++/* USB_EP.STATUS bit masks and bit positions */
++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */
++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */
++
++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */
++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */
++
++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */
++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */
++
++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */
++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */
++
++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */
++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */
++
++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */
++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */
++
++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */
++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */
++
++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */
++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */
++
++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */
++
++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */
++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */
++
++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */
++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */
++
++/* USB_EP.CTRL bit masks and bit positions */
++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */
++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */
++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */
++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */
++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */
++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */
++
++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */
++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */
++
++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */
++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */
++
++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */
++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */
++
++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */
++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */
++
++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */
++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */
++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */
++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */
++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */
++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */
++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */
++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */
++
++/* USB_EP.CNT bit masks and bit positions */
++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */
++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */
++
++/* USB.CTRLA bit masks and bit positions */
++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */
++#define USB_ENABLE_bp 7 /* USB Enable bit position. */
++
++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */
++#define USB_SPEED_bp 6 /* Speed Select bit position. */
++
++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */
++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */
++
++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */
++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */
++
++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */
++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */
++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */
++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */
++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */
++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */
++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */
++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */
++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */
++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */
++
++/* USB.CTRLB bit masks and bit positions */
++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */
++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */
++
++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */
++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */
++
++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */
++#define USB_GNACK_bp 1 /* Global NACK bit position. */
++
++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */
++#define USB_ATTACH_bp 0 /* Attach bit position. */
++
++/* USB.STATUS bit masks and bit positions */
++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */
++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */
++
++#define USB_RESUME_bm 0x04 /* Resume bit mask. */
++#define USB_RESUME_bp 2 /* Resume bit position. */
++
++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */
++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */
++
++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */
++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */
++
++/* USB.ADDR bit masks and bit positions */
++#define USB_ADDR_gm 0x7F /* Device Address group mask. */
++#define USB_ADDR_gp 0 /* Device Address group position. */
++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */
++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */
++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */
++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */
++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */
++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */
++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */
++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */
++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */
++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */
++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */
++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */
++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */
++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */
++
++/* USB.FIFOWP bit masks and bit positions */
++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */
++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */
++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */
++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */
++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */
++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */
++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */
++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */
++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */
++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */
++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */
++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */
++
++/* USB.FIFORP bit masks and bit positions */
++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */
++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */
++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */
++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */
++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */
++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */
++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */
++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */
++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */
++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */
++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */
++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */
++
++/* USB.INTCTRLA bit masks and bit positions */
++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */
++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */
++
++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */
++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */
++
++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */
++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */
++
++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */
++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */
++
++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */
++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* USB.INTCTRLB bit masks and bit positions */
++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */
++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */
++
++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */
++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */
++
++/* USB.INTFLAGSACLR bit masks and bit positions */
++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */
++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */
++
++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */
++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */
++
++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */
++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */
++
++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */
++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */
++
++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */
++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */
++
++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */
++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */
++
++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */
++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */
++
++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */
++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */
++
++/* USB.INTFLAGSASET bit masks and bit positions */
++/* USB_SOFIF Predefined. */
++/* USB_SOFIF Predefined. */
++
++/* USB_SUSPENDIF Predefined. */
++/* USB_SUSPENDIF Predefined. */
++
++/* USB_RESUMEIF Predefined. */
++/* USB_RESUMEIF Predefined. */
++
++/* USB_RSTIF Predefined. */
++/* USB_RSTIF Predefined. */
++
++/* USB_CRCIF Predefined. */
++/* USB_CRCIF Predefined. */
++
++/* USB_UNFIF Predefined. */
++/* USB_UNFIF Predefined. */
++
++/* USB_OVFIF Predefined. */
++/* USB_OVFIF Predefined. */
++
++/* USB_STALLIF Predefined. */
++/* USB_STALLIF Predefined. */
++
++/* USB.INTFLAGSBCLR bit masks and bit positions */
++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */
++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */
++
++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */
++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */
++
++/* USB.INTFLAGSBSET bit masks and bit positions */
++/* USB_TRNIF Predefined. */
++/* USB_TRNIF Predefined. */
++
++/* USB_SETUPIF Predefined. */
++/* USB_SETUPIF Predefined. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LUNF_vect_num 47
++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_HUNF_vect_num 48
++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPA_vect_num 49
++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPB_vect_num 50
++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPC_vect_num 51
++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* TCE2 interrupt vectors */
++#define TCE2_LCMPD_vect_num 52
++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++/* PORTF interrupt vectors */
++#define PORTF_INT0_vect_num 104
++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
++#define PORTF_INT1_vect_num 105
++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
++
++/* TCF0 interrupt vectors */
++#define TCF0_OVF_vect_num 108
++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LUNF_vect_num 108
++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_ERR_vect_num 109
++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_HUNF_vect_num 109
++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCA_vect_num 110
++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPA_vect_num 110
++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCB_vect_num 111
++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPB_vect_num 111
++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCC_vect_num 112
++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPC_vect_num 112
++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */
++
++/* TCF0 interrupt vectors */
++#define TCF0_CCD_vect_num 113
++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
++
++/* TCF2 interrupt vectors */
++#define TCF2_LCMPD_vect_num 113
++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */
++
++/* USB interrupt vectors */
++#define USB_BUSEVENT_vect_num 125
++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */
++#define USB_TRNCOMPL_vect_num 126
++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (127 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xE000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x49
++
++
++#endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox64d4.h avr-libc-1.8.0/include/avr/iox64d4.h
+--- avr-libc-1.8.0.orig/include/avr/iox64d4.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox64d4.h 2013-01-18 09:50:27.000000000 +0100
+@@ -0,0 +1,5444 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox64d4.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA64D4_H_INCLUDED
++#define _AVR_ATXMEGA64D4_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t PRPE; /* Power Reduction Port E */
++ register8_t PRPF; /* Power Reduction Port F */
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 2 MHz DFLL Calibration Reference */
++typedef enum OSC_RC2MCREF_enum
++{
++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC2MCREF_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t AWEXLOCK; /* AWEX Lock */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t VPCTRLA; /* Virtual Port Control Register A */
++ register8_t VPCTRLB; /* Virtual Port Control Register B */
++ register8_t CLKEVOUT; /* Clock and Event Out Register */
++ register8_t reserved_0x05;
++ register8_t EVOUTSEL; /* Event Output Select */
++} PORTCFG_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP02MAP_enum
++{
++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
++} PORTCFG_VP02MAP_t;
++
++/* Virtual Port Mapping */
++typedef enum PORTCFG_VP13MAP_enum
++{
++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
++} PORTCFG_VP13MAP_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */
++} PORTCFG_CLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++} EVSYS_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
++} EVSYS_CHMUX_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t reserved_0x07;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
++} ADC_CH_MUXNEG_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
++} ADC_CH_INPUTMODE_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
++ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
++} ADC_EVACT_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Counter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - I/O Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INT0MASK; /* Port Interrupt 0 Mask */
++ register8_t INT1MASK; /* Port Interrupt 1 Mask */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* I/O Port Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt 0 Level */
++typedef enum PORT_INT0LVL_enum
++{
++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INT0LVL_t;
++
++/* Port Interrupt 1 Level */
++typedef enum PORT_INT1LVL_enum
++{
++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
++} PORT_INT1LVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 0 */
++typedef struct TC0_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC0_t;
++
++
++/* 16-bit Timer/Counter 1 */
++typedef struct TC1_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLFCLR; /* Control Register F Clear */
++ register8_t CTRLFSET; /* Control Register F Set */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++} TC1_t;
++
++/* Clock Selection */
++typedef enum TC_CLKSEL_enum
++{
++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_CLKSEL_t;
++
++/* Waveform Generation Mode */
++typedef enum TC_WGMODE_enum
++{
++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */
++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC_WGMODE_t;
++
++/* Byte Mode */
++typedef enum TC_BYTEM_enum
++{
++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */
++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */
++} TC_BYTEM_t;
++
++/* Event Action */
++typedef enum TC_EVACT_enum
++{
++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
++} TC_EVACT_t;
++
++/* Event Selection */
++typedef enum TC_EVSEL_enum
++{
++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC_EVSEL_t;
++
++/* Error Interrupt Level */
++typedef enum TC_ERRINTLVL_enum
++{
++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC_OVFINTLVL_enum
++{
++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_OVFINTLVL_t;
++
++/* Compare or Capture D Interrupt Level */
++typedef enum TC_CCDINTLVL_enum
++{
++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC_CCDINTLVL_t;
++
++/* Compare or Capture C Interrupt Level */
++typedef enum TC_CCCINTLVL_enum
++{
++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC_CCCINTLVL_t;
++
++/* Compare or Capture B Interrupt Level */
++typedef enum TC_CCBINTLVL_enum
++{
++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC_CCBINTLVL_t;
++
++/* Compare or Capture A Interrupt Level */
++typedef enum TC_CCAINTLVL_enum
++{
++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC_CCAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC_CMD_enum
++{
++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC2 - 16-bit Timer/Counter type 2
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter type 2 */
++typedef struct TC2_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t reserved_0x03;
++ register8_t CTRLE; /* Control Register E */
++ register8_t reserved_0x05;
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t reserved_0x08;
++ register8_t CTRLF; /* Control Register F */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t LCNT; /* Low Byte Count */
++ register8_t HCNT; /* High Byte Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t LPER; /* Low Byte Period */
++ register8_t HPER; /* High Byte Period */
++ register8_t LCMPA; /* Low Byte Compare A */
++ register8_t HCMPA; /* High Byte Compare A */
++ register8_t LCMPB; /* Low Byte Compare B */
++ register8_t HCMPB; /* High Byte Compare B */
++ register8_t LCMPC; /* Low Byte Compare C */
++ register8_t HCMPC; /* High Byte Compare C */
++ register8_t LCMPD; /* Low Byte Compare D */
++ register8_t HCMPD; /* High Byte Compare D */
++} TC2_t;
++
++/* Clock Selection */
++typedef enum TC2_CLKSEL_enum
++{
++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++} TC2_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC2_BYTEM_enum
++{
++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */
++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */
++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */
++} TC2_BYTEM_t;
++
++/* High Byte Underflow Interrupt Level */
++typedef enum TC2_HUNFINTLVL_enum
++{
++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_HUNFINTLVL_t;
++
++/* Low Byte Underflow Interrupt Level */
++typedef enum TC2_LUNFINTLVL_enum
++{
++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LUNFINTLVL_t;
++
++/* Low Byte Compare D Interrupt Level */
++typedef enum TC2_LCMPDINTLVL_enum
++{
++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC2_LCMPDINTLVL_t;
++
++/* Low Byte Compare C Interrupt Level */
++typedef enum TC2_LCMPCINTLVL_enum
++{
++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC2_LCMPCINTLVL_t;
++
++/* Low Byte Compare B Interrupt Level */
++typedef enum TC2_LCMPBINTLVL_enum
++{
++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC2_LCMPBINTLVL_t;
++
++/* Low Byte Compare A Interrupt Level */
++typedef enum TC2_LCMPAINTLVL_enum
++{
++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC2_LCMPAINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMD_enum
++{
++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC2_CMD_t;
++
++/* Timer/Counter Command */
++typedef enum TC2_CMDEN_enum
++{
++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */
++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */
++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */
++} TC2_CMDEN_t;
++
++
++/*
++--------------------------------------------------------------------------
++AWEX - Timer/Counter Advanced Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Advanced Waveform Extension */
++typedef struct AWEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t FDEMASK; /* Fault Detection Event Mask */
++ register8_t FDCTRL; /* Fault Detection Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t DTBOTH; /* Dead Time Both Sides */
++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
++ register8_t DTLS; /* Dead Time Low Side */
++ register8_t DTHS; /* Dead Time High Side */
++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
++ register8_t DTHSBUF; /* Dead Time High Side Buffer */
++ register8_t OUTOVEN; /* Output Override Enable */
++} AWEX_t;
++
++/* Fault Detect Action */
++typedef enum AWEX_FDACT_enum
++{
++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
++} AWEX_FDACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - Timer/Counter High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register */
++} HIRES_t;
++
++/* High Resolution Enable */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++} NVM_FUSES_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* Timer Oscillator pin location */
++typedef enum TOSCSEL_enum
++{
++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */
++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */
++} TOSCSEL_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
++} BOD_t;
++
++/* BOD operation */
++typedef enum BODACT_enum
++{
++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BODACT_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WDP_enum
++{
++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */
++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */
++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */
++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */
++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */
++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */
++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */
++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */
++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */
++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */
++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */
++} WDP_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++LOCKBIT - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */
++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t reserved_0x28;
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */
++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */
++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */
++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */
++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */
++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */
++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* DFLL - DFLL */
++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
++#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
++#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++#define PR_PRPE _SFR_MEM8(0x0075)
++#define PR_PRPF _SFR_MEM8(0x0076)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* TWI - Two-Wire Interface */
++#define TWIE_CTRL _SFR_MEM8(0x04A0)
++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INT0MASK _SFR_MEM8(0x060A)
++#define PORTA_INT1MASK _SFR_MEM8(0x060B)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTB_DIR _SFR_MEM8(0x0620)
++#define PORTB_DIRSET _SFR_MEM8(0x0621)
++#define PORTB_DIRCLR _SFR_MEM8(0x0622)
++#define PORTB_DIRTGL _SFR_MEM8(0x0623)
++#define PORTB_OUT _SFR_MEM8(0x0624)
++#define PORTB_OUTSET _SFR_MEM8(0x0625)
++#define PORTB_OUTCLR _SFR_MEM8(0x0626)
++#define PORTB_OUTTGL _SFR_MEM8(0x0627)
++#define PORTB_IN _SFR_MEM8(0x0628)
++#define PORTB_INTCTRL _SFR_MEM8(0x0629)
++#define PORTB_INT0MASK _SFR_MEM8(0x062A)
++#define PORTB_INT1MASK _SFR_MEM8(0x062B)
++#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
++#define PORTB_REMAP _SFR_MEM8(0x062E)
++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INT0MASK _SFR_MEM8(0x064A)
++#define PORTC_INT1MASK _SFR_MEM8(0x064B)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INT0MASK _SFR_MEM8(0x066A)
++#define PORTD_INT1MASK _SFR_MEM8(0x066B)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTE_DIR _SFR_MEM8(0x0680)
++#define PORTE_DIRSET _SFR_MEM8(0x0681)
++#define PORTE_DIRCLR _SFR_MEM8(0x0682)
++#define PORTE_DIRTGL _SFR_MEM8(0x0683)
++#define PORTE_OUT _SFR_MEM8(0x0684)
++#define PORTE_OUTSET _SFR_MEM8(0x0685)
++#define PORTE_OUTCLR _SFR_MEM8(0x0686)
++#define PORTE_OUTTGL _SFR_MEM8(0x0687)
++#define PORTE_IN _SFR_MEM8(0x0688)
++#define PORTE_INTCTRL _SFR_MEM8(0x0689)
++#define PORTE_INT0MASK _SFR_MEM8(0x068A)
++#define PORTE_INT1MASK _SFR_MEM8(0x068B)
++#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
++#define PORTE_REMAP _SFR_MEM8(0x068E)
++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
++#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCC0_CTRLA _SFR_MEM8(0x0800)
++#define TCC0_CTRLB _SFR_MEM8(0x0801)
++#define TCC0_CTRLC _SFR_MEM8(0x0802)
++#define TCC0_CTRLD _SFR_MEM8(0x0803)
++#define TCC0_CTRLE _SFR_MEM8(0x0804)
++#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
++#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
++#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
++#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC0_TEMP _SFR_MEM8(0x080F)
++#define TCC0_CNT _SFR_MEM16(0x0820)
++#define TCC0_PER _SFR_MEM16(0x0826)
++#define TCC0_CCA _SFR_MEM16(0x0828)
++#define TCC0_CCB _SFR_MEM16(0x082A)
++#define TCC0_CCC _SFR_MEM16(0x082C)
++#define TCC0_CCD _SFR_MEM16(0x082E)
++#define TCC0_PERBUF _SFR_MEM16(0x0836)
++#define TCC0_CCABUF _SFR_MEM16(0x0838)
++#define TCC0_CCBBUF _SFR_MEM16(0x083A)
++#define TCC0_CCCBUF _SFR_MEM16(0x083C)
++#define TCC0_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCC2_CTRLA _SFR_MEM8(0x0800)
++#define TCC2_CTRLB _SFR_MEM8(0x0801)
++#define TCC2_CTRLC _SFR_MEM8(0x0802)
++#define TCC2_CTRLE _SFR_MEM8(0x0804)
++#define TCC2_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC2_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC2_CTRLF _SFR_MEM8(0x0809)
++#define TCC2_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC2_LCNT _SFR_MEM8(0x0820)
++#define TCC2_HCNT _SFR_MEM8(0x0821)
++#define TCC2_LPER _SFR_MEM8(0x0826)
++#define TCC2_HPER _SFR_MEM8(0x0827)
++#define TCC2_LCMPA _SFR_MEM8(0x0828)
++#define TCC2_HCMPA _SFR_MEM8(0x0829)
++#define TCC2_LCMPB _SFR_MEM8(0x082A)
++#define TCC2_HCMPB _SFR_MEM8(0x082B)
++#define TCC2_LCMPC _SFR_MEM8(0x082C)
++#define TCC2_HCMPC _SFR_MEM8(0x082D)
++#define TCC2_LCMPD _SFR_MEM8(0x082E)
++#define TCC2_HCMPD _SFR_MEM8(0x082F)
++
++/* TC1 - 16-bit Timer/Counter 1 */
++#define TCC1_CTRLA _SFR_MEM8(0x0840)
++#define TCC1_CTRLB _SFR_MEM8(0x0841)
++#define TCC1_CTRLC _SFR_MEM8(0x0842)
++#define TCC1_CTRLD _SFR_MEM8(0x0843)
++#define TCC1_CTRLE _SFR_MEM8(0x0844)
++#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
++#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
++#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
++#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC1_TEMP _SFR_MEM8(0x084F)
++#define TCC1_CNT _SFR_MEM16(0x0860)
++#define TCC1_PER _SFR_MEM16(0x0866)
++#define TCC1_CCA _SFR_MEM16(0x0868)
++#define TCC1_CCB _SFR_MEM16(0x086A)
++#define TCC1_PERBUF _SFR_MEM16(0x0876)
++#define TCC1_CCABUF _SFR_MEM16(0x0878)
++#define TCC1_CCBBUF _SFR_MEM16(0x087A)
++
++/* AWEX - Advanced Waveform Extension */
++#define AWEXC_CTRL _SFR_MEM8(0x0880)
++#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
++#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
++#define AWEXC_STATUS _SFR_MEM8(0x0884)
++#define AWEXC_STATUSSET _SFR_MEM8(0x0885)
++#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
++#define AWEXC_DTLS _SFR_MEM8(0x0888)
++#define AWEXC_DTHS _SFR_MEM8(0x0889)
++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x0890)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08A0)
++#define USARTC0_STATUS _SFR_MEM8(0x08A1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
++#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
++#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPIC_CTRL _SFR_MEM8(0x08C0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
++#define SPIC_STATUS _SFR_MEM8(0x08C2)
++#define SPIC_DATA _SFR_MEM8(0x08C3)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCD0_CTRLA _SFR_MEM8(0x0900)
++#define TCD0_CTRLB _SFR_MEM8(0x0901)
++#define TCD0_CTRLC _SFR_MEM8(0x0902)
++#define TCD0_CTRLD _SFR_MEM8(0x0903)
++#define TCD0_CTRLE _SFR_MEM8(0x0904)
++#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
++#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
++#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
++#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD0_TEMP _SFR_MEM8(0x090F)
++#define TCD0_CNT _SFR_MEM16(0x0920)
++#define TCD0_PER _SFR_MEM16(0x0926)
++#define TCD0_CCA _SFR_MEM16(0x0928)
++#define TCD0_CCB _SFR_MEM16(0x092A)
++#define TCD0_CCC _SFR_MEM16(0x092C)
++#define TCD0_CCD _SFR_MEM16(0x092E)
++#define TCD0_PERBUF _SFR_MEM16(0x0936)
++#define TCD0_CCABUF _SFR_MEM16(0x0938)
++#define TCD0_CCBBUF _SFR_MEM16(0x093A)
++#define TCD0_CCCBUF _SFR_MEM16(0x093C)
++#define TCD0_CCDBUF _SFR_MEM16(0x093E)
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++#define TCD2_CTRLA _SFR_MEM8(0x0900)
++#define TCD2_CTRLB _SFR_MEM8(0x0901)
++#define TCD2_CTRLC _SFR_MEM8(0x0902)
++#define TCD2_CTRLE _SFR_MEM8(0x0904)
++#define TCD2_INTCTRLA _SFR_MEM8(0x0906)
++#define TCD2_INTCTRLB _SFR_MEM8(0x0907)
++#define TCD2_CTRLF _SFR_MEM8(0x0909)
++#define TCD2_INTFLAGS _SFR_MEM8(0x090C)
++#define TCD2_LCNT _SFR_MEM8(0x0920)
++#define TCD2_HCNT _SFR_MEM8(0x0921)
++#define TCD2_LPER _SFR_MEM8(0x0926)
++#define TCD2_HPER _SFR_MEM8(0x0927)
++#define TCD2_LCMPA _SFR_MEM8(0x0928)
++#define TCD2_HCMPA _SFR_MEM8(0x0929)
++#define TCD2_LCMPB _SFR_MEM8(0x092A)
++#define TCD2_HCMPB _SFR_MEM8(0x092B)
++#define TCD2_LCMPC _SFR_MEM8(0x092C)
++#define TCD2_HCMPC _SFR_MEM8(0x092D)
++#define TCD2_LCMPD _SFR_MEM8(0x092E)
++#define TCD2_HCMPD _SFR_MEM8(0x092F)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09A0)
++#define USARTD0_STATUS _SFR_MEM8(0x09A1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
++#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
++#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
++
++/* SPI - Serial Peripheral Interface */
++#define SPID_CTRL _SFR_MEM8(0x09C0)
++#define SPID_INTCTRL _SFR_MEM8(0x09C1)
++#define SPID_STATUS _SFR_MEM8(0x09C2)
++#define SPID_DATA _SFR_MEM8(0x09C3)
++
++/* TC0 - 16-bit Timer/Counter 0 */
++#define TCE0_CTRLA _SFR_MEM8(0x0A00)
++#define TCE0_CTRLB _SFR_MEM8(0x0A01)
++#define TCE0_CTRLC _SFR_MEM8(0x0A02)
++#define TCE0_CTRLD _SFR_MEM8(0x0A03)
++#define TCE0_CTRLE _SFR_MEM8(0x0A04)
++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
++#define TCE0_TEMP _SFR_MEM8(0x0A0F)
++#define TCE0_CNT _SFR_MEM16(0x0A20)
++#define TCE0_PER _SFR_MEM16(0x0A26)
++#define TCE0_CCA _SFR_MEM16(0x0A28)
++#define TCE0_CCB _SFR_MEM16(0x0A2A)
++#define TCE0_CCC _SFR_MEM16(0x0A2C)
++#define TCE0_CCD _SFR_MEM16(0x0A2E)
++#define TCE0_PERBUF _SFR_MEM16(0x0A36)
++#define TCE0_CCABUF _SFR_MEM16(0x0A38)
++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
++
++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
++
++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_SPI Predefined. */
++/* PR_SPI Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPE bit masks and bit positions */
++/* PR_TWI Predefined. */
++/* PR_TWI Predefined. */
++
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* PR.PRPF bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC0 Predefined. */
++/* PR_TC0 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */
++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.AWEXLOCK bit masks and bit positions */
++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.VPCTRLA bit masks and bit positions */
++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
++
++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
++
++/* PORTCFG.VPCTRLB bit masks and bit positions */
++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
++
++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
++
++/* PORTCFG.CLKEVOUT bit masks and bit positions */
++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
++
++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */
++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */
++
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */
++
++/* PORTCFG.EVOUTSEL bit masks and bit positions */
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
++
++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
++
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */
++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */
++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */
++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */
++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */
++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */
++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */
++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */
++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */
++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */
++
++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */
++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */
++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */
++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */
++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */
++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */
++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */
++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */
++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */
++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* RTC - Real-Time Counter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* PORT - I/O Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
++
++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_SPI_bm 0x20 /* SPI bit mask. */
++#define PORT_SPI_bp 5 /* SPI bit position. */
++
++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */
++#define PORT_USART0_bp 4 /* USART0 bit position. */
++
++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */
++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */
++
++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */
++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */
++
++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */
++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */
++
++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */
++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
++
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_SRLEN Predefined. */
++/* PORT_SRLEN Predefined. */
++
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC0.CTRLA bit masks and bit positions */
++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC0.CTRLB bit masks and bit positions */
++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
++
++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
++
++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC0.CTRLC bit masks and bit positions */
++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
++
++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
++
++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC0.CTRLD bit masks and bit positions */
++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC0_EVACT_gp 5 /* Event Action group position. */
++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC0.CTRLE bit masks and bit positions */
++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC0.INTCTRLA bit masks and bit positions */
++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC0.INTCTRLB bit masks and bit positions */
++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
++
++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
++
++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC0.CTRLFCLR bit masks and bit positions */
++#define TC0_CMD_gm 0x0C /* Command group mask. */
++#define TC0_CMD_gp 2 /* Command group position. */
++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC0_CMD0_bp 2 /* Command bit 0 position. */
++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC0_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC0_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC0_DIR_bm 0x01 /* Direction bit mask. */
++#define TC0_DIR_bp 0 /* Direction bit position. */
++
++/* TC0.CTRLFSET bit masks and bit positions */
++/* TC0_CMD Predefined. */
++/* TC0_CMD Predefined. */
++
++/* TC0_LUPD Predefined. */
++/* TC0_LUPD Predefined. */
++
++/* TC0_DIR Predefined. */
++/* TC0_DIR Predefined. */
++
++/* TC0.CTRLGCLR bit masks and bit positions */
++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
++
++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
++
++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC0.CTRLGSET bit masks and bit positions */
++/* TC0_CCDBV Predefined. */
++/* TC0_CCDBV Predefined. */
++
++/* TC0_CCCBV Predefined. */
++/* TC0_CCCBV Predefined. */
++
++/* TC0_CCBBV Predefined. */
++/* TC0_CCBBV Predefined. */
++
++/* TC0_CCABV Predefined. */
++/* TC0_CCABV Predefined. */
++
++/* TC0_PERBV Predefined. */
++/* TC0_PERBV Predefined. */
++
++/* TC0.INTFLAGS bit masks and bit positions */
++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
++
++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
++
++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC1.CTRLA bit masks and bit positions */
++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC1.CTRLB bit masks and bit positions */
++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
++
++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
++
++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
++
++/* TC1.CTRLC bit masks and bit positions */
++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
++
++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
++
++/* TC1.CTRLD bit masks and bit positions */
++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC1_EVACT_gp 5 /* Event Action group position. */
++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC1.CTRLE bit masks and bit positions */
++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
++
++/* TC1.INTCTRLA bit masks and bit positions */
++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
++
++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
++
++/* TC1.INTCTRLB bit masks and bit positions */
++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
++
++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
++
++/* TC1.CTRLFCLR bit masks and bit positions */
++#define TC1_CMD_gm 0x0C /* Command group mask. */
++#define TC1_CMD_gp 2 /* Command group position. */
++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC1_CMD0_bp 2 /* Command bit 0 position. */
++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC1_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC1_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC1_DIR_bm 0x01 /* Direction bit mask. */
++#define TC1_DIR_bp 0 /* Direction bit position. */
++
++/* TC1.CTRLFSET bit masks and bit positions */
++/* TC1_CMD Predefined. */
++/* TC1_CMD Predefined. */
++
++/* TC1_LUPD Predefined. */
++/* TC1_LUPD Predefined. */
++
++/* TC1_DIR Predefined. */
++/* TC1_DIR Predefined. */
++
++/* TC1.CTRLGCLR bit masks and bit positions */
++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
++
++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
++
++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++/* TC1.CTRLGSET bit masks and bit positions */
++/* TC1_CCBBV Predefined. */
++/* TC1_CCBBV Predefined. */
++
++/* TC1_CCABV Predefined. */
++/* TC1_CCABV Predefined. */
++
++/* TC1_PERBV Predefined. */
++/* TC1_PERBV Predefined. */
++
++/* TC1.INTFLAGS bit masks and bit positions */
++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
++
++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
++
++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* TC2 - 16-bit Timer/Counter type 2 */
++/* TC2.CTRLA bit masks and bit positions */
++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */
++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* TC2.CTRLB bit masks and bit positions */
++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */
++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */
++
++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */
++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */
++
++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */
++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */
++
++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */
++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */
++
++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */
++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */
++
++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */
++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */
++
++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */
++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */
++
++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */
++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */
++
++/* TC2.CTRLC bit masks and bit positions */
++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */
++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */
++
++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */
++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */
++
++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */
++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */
++
++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */
++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */
++
++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */
++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */
++
++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */
++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */
++
++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */
++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */
++
++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */
++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */
++
++/* TC2.CTRLE bit masks and bit positions */
++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */
++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */
++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */
++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */
++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */
++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */
++
++/* TC2.INTCTRLA bit masks and bit positions */
++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */
++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */
++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */
++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */
++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */
++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */
++
++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */
++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */
++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */
++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */
++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */
++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */
++
++/* TC2.INTCTRLB bit masks and bit positions */
++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */
++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */
++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */
++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */
++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */
++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */
++
++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */
++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */
++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */
++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */
++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */
++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */
++
++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */
++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */
++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */
++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */
++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */
++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */
++
++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */
++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */
++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */
++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */
++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */
++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */
++
++/* TC2.CTRLF bit masks and bit positions */
++#define TC2_CMD_gm 0x0C /* Command group mask. */
++#define TC2_CMD_gp 2 /* Command group position. */
++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC2_CMD0_bp 2 /* Command bit 0 position. */
++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC2_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */
++#define TC2_CMDEN_gp 0 /* Command Enable group position. */
++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */
++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */
++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */
++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */
++
++/* TC2.INTFLAGS bit masks and bit positions */
++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */
++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */
++
++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */
++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */
++
++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */
++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */
++
++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */
++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */
++
++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */
++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */
++
++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */
++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */
++
++/* AWEX - Timer/Counter Advanced Waveform Extension */
++/* AWEX.CTRL bit masks and bit positions */
++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
++
++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
++
++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
++
++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
++
++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
++
++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
++
++/* AWEX.FDCTRL bit masks and bit positions */
++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
++
++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
++
++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
++
++/* AWEX.STATUS bit masks and bit positions */
++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
++
++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
++
++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
++
++/* AWEX.STATUSSET bit masks and bit positions */
++/* AWEX_FDF Predefined. */
++/* AWEX_FDF Predefined. */
++
++/* AWEX_DTHSBUFV Predefined. */
++/* AWEX_DTHSBUFV Predefined. */
++
++/* AWEX_DTLSBUFV Predefined. */
++/* AWEX_DTLSBUFV Predefined. */
++
++/* HIRES - Timer/Counter High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */
++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* LOCKBIT - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT0_vect_num 2
++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
++#define PORTC_INT1_vect_num 3
++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT0_vect_num 4
++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
++#define PORTR_INT1_vect_num 5
++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 10
++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 11
++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 12
++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 13
++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_OVF_vect_num 14
++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LUNF_vect_num 14
++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_ERR_vect_num 15
++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_HUNF_vect_num 15
++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCA_vect_num 16
++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPA_vect_num 16
++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCB_vect_num 17
++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPB_vect_num 17
++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCC_vect_num 18
++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPC_vect_num 18
++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */
++
++/* TCC0 interrupt vectors */
++#define TCC0_CCD_vect_num 19
++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
++
++/* TCC2 interrupt vectors */
++#define TCC2_LCMPD_vect_num 19
++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */
++
++/* TCC1 interrupt vectors */
++#define TCC1_OVF_vect_num 20
++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
++#define TCC1_ERR_vect_num 21
++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
++#define TCC1_CCA_vect_num 22
++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
++#define TCC1_CCB_vect_num 23
++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 24
++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 25
++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 26
++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 27
++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 32
++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
++#define NVM_SPM_vect_num 33
++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
++
++/* PORTB interrupt vectors */
++#define PORTB_INT0_vect_num 34
++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
++#define PORTB_INT1_vect_num 35
++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
++
++/* PORTE interrupt vectors */
++#define PORTE_INT0_vect_num 43
++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
++#define PORTE_INT1_vect_num 44
++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
++
++/* TWIE interrupt vectors */
++#define TWIE_TWIS_vect_num 45
++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
++#define TWIE_TWIM_vect_num 46
++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
++
++/* TCE0 interrupt vectors */
++#define TCE0_OVF_vect_num 47
++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
++#define TCE0_ERR_vect_num 48
++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
++#define TCE0_CCA_vect_num 49
++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
++#define TCE0_CCB_vect_num 50
++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
++#define TCE0_CCC_vect_num 51
++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
++#define TCE0_CCD_vect_num 52
++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
++
++/* USARTE0 interrupt vectors */
++#define USARTE0_RXC_vect_num 58
++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
++#define USARTE0_DRE_vect_num 59
++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
++#define USARTE0_TXC_vect_num 60
++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT0_vect_num 64
++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
++#define PORTD_INT1_vect_num 65
++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT0_vect_num 66
++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
++#define PORTA_INT1_vect_num 67
++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 68
++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 69
++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 70
++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 71
++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
++
++/* TCD0 interrupt vectors */
++#define TCD0_OVF_vect_num 77
++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LUNF_vect_num 77
++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_ERR_vect_num 78
++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_HUNF_vect_num 78
++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCA_vect_num 79
++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPA_vect_num 79
++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCB_vect_num 80
++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPB_vect_num 80
++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCC_vect_num 81
++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPC_vect_num 81
++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */
++
++/* TCD0 interrupt vectors */
++#define TCD0_CCD_vect_num 82
++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
++
++/* TCD2 interrupt vectors */
++#define TCD2_LCMPD_vect_num 82
++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */
++
++/* SPID interrupt vectors */
++#define SPID_INT_vect_num 87
++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 88
++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 89
++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 90
++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (69632)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (65536)
++#define APP_SECTION_PAGE_SIZE (256)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0xF000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (256)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x10000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (256)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (2048)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (2048)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (256)
++#define USER_SIGNATURES_PAGE_SIZE (256)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (64)
++#define PROD_SIGNATURES_PAGE_SIZE (256)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 256
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 6
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x96
++#define SIGNATURE_2 0x47
++
++
++#endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/power.h avr-libc-1.8.0/include/avr/power.h
+--- avr-libc-1.8.0.orig/include/avr/power.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/power.h 2013-01-18 09:50:27.000000000 +0100
+@@ -73,1046 +73,1136 @@
+
+ <tr>
+ <td>power_aca_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable The Analog Comparator On PortA </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_aca_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable The Analog Comparator On PortA </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_acb_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable The Analog Comparator On PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_acb_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable The Analog Comparator On PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_adc_disable()</td>
+ <td>Disable the Analog to Digital Converter module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_adc_enable()</td>
+ <td>Enable the Analog to Digital Converter module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_adca_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the Analog to Digital Converter module On PortA </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_adca_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the Analog to Digital Converter module On PortA </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_adcb_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the Analog to Digital Converter module On PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_adcb_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the Analog to Digital Converter module On PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_aes_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90SCR100</td>
++ <td> Disable the AES module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_aes_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90SCR100</td>
++ <td> Enable the AES module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_all_disable()</td>
+ <td>Disable all modules.</td>
+- <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64D4, ATxmega128D4, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny828, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64D4, ATxmega128D4, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny828, ATtiny841, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_all_enable()</td>
+ <td>Enable all modules.</td>
+- <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64D4, ATxmega128D4, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny828, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64D4, ATxmega128D4, ATxmega16D4, ATxmega32D4, ATxmega64D3, ATxmega128D3, ATxmega192D3, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA, ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny828, ATtiny841, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_can_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
++ <td> Disable the CAN module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
+ </tr>
+
+ <tr>
+ <td>power_can_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
++ <td> Enable the CAN module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
+ </tr>
+
+ <tr>
+ <td>power_cinterface_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Disable the CINTERFACE module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+ <td>power_cinterface_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Enable the CINTERFACE module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
++ </tr>
++
++ <tr>
++ <td>power_clock_output_disable()</td>
++ <td>Enable clock output module</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_clock_output_enable()</td>
++ <td>Enable clock output module</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_cpld_disable()</td>
++ <td> Disable CPLD module </td>
++ <td>ATxmega32E5</td>
++ </tr>
++
++ <tr>
++ <td>power_cpld_enable()</td>
++ <td> Enable CPLD module </td>
++ <td>ATxmega32E5</td>
++ </tr>
++
++ <tr>
++ <td>power_crc_disable()</td>
++ <td>Disable CRC module</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_crc_enable()</td>
++ <td>Enable CRC module</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_crypto_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Disable the CRYPTO module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+ <td>power_crypto_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Enable the CRYPTO module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
++ </tr>
++
++ <tr>
++ <td>power_ctm_disable()</td>
++ <td> Disable CTM module </td>
++ <td>ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
++ </tr>
++
++ <tr>
++ <td>power_ctm_enable()</td>
++ <td> Enable CTM module </td>
++ <td>ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_daca_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td> Disable the DAC module on PortA </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_daca_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td> Enable the DAC module on PortA </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_dacb_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the DAC module on PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_dacb_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the DAC module on PortB </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+- <td>power_dma_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td>power_data_fifo_disable()</td>
++ <td>Disable data FIFO</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_dma_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td>power_data_fifo_enable()</td>
++ <td>Enable data FIFO</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_ebi_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>power_dma_disable()</td>
++ <td> Disable the DMA module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+- <td>power_ebi_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>power_dma_enable()</td>
++ <td> Enable the DMA module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+- <td>power_edma_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td>power_ebi_disable()</td>
++ <td> Disable the EBI module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+- <td>power_edma_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td>power_ebi_enable()</td>
++ <td> Enable the EBI module </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_evsys_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the EVSYS module </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_evsys_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the EVSYS module </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresc_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the HIRES module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresc_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the HIRES module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresd_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the HIRES module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresd_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the HIRES module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hirese_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the HIRES module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hirese_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the HIRES module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresf_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the HIRES module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hiresf_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the HIRES module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_hsspi_disable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Disable the HSPPI module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_hsspi_enable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Enable the HSPPI module </td>
++ <td>AT90SCR100</td>
++ </tr>
++
++ <tr>
++ <td>power_id_scan_disable()</td>
++ <td>Disable ID Scan</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_id_scan_enable()</td>
++ <td>Enable ID Scan</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_irdriver_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Disable the IRDRIVER module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+ <td>power_irdriver_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Enable the IRDRIVER module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+ <td>power_kb_disable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Disable the KB module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_kb_enable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Enable the KB module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_lcd_disable()</td>
+ <td>Disable the LCD module.</td>
+- <td>ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P</td>
++ <td>ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P</td>
+ </tr>
+
+ <tr>
+ <td>power_lcd_enable()</td>
+ <td>Enable the LCD module.</td>
+- <td>ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P</td>
++ <td>ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P</td>
+ </tr>
+
+ <tr>
+ <td>power_lfreceiver_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790</td>
++ <td> Disable the LFRECEIVER module </td>
++ <td>ATA5790, ATA5790N</td>
+ </tr>
+
+ <tr>
+ <td>power_lfreceiver_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790</td>
++ <td> Enable the LFRECEIVER module </td>
++ <td>ATA5790, ATA5790N</td>
+ </tr>
+
+ <tr>
+ <td>power_lin_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272</td>
++ <td> Disable the LIN module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272</td>
+ </tr>
+
+ <tr>
+ <td>power_lin_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272</td>
++ <td> Enable the LIN module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272</td>
+ </tr>
+
+ <tr>
+ <td>power_pga_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Disable PGA module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_pga_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Enable PGA module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
++ </tr>
++
++ <tr>
++ <td>power_preamble_rssi_fifo_disable()</td>
++ <td>Disable preamble/RSSI FIFO</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_preamble_rssi_fifo_enable()</td>
++ <td>Enable preamble/RSSI FIFO</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_psc0_disable()</td>
+ <td>Disable the Power Stage Controller 0 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_psc0_enable()</td>
+ <td>Enable the Power Stage Controller 0 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_psc1_disable()</td>
+ <td>Disable the Power Stage Controller 1 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_psc1_enable()</td>
+ <td>Enable the Power Stage Controller 1 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_psc2_disable()</td>
+ <td>Disable the Power Stage Controller 2 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161</td>
+ </tr>
+
+ <tr>
+ <td>power_psc2_enable()</td>
+ <td>Enable the Power Stage Controller 2 module.</td>
+- <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161</td>
++ <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161</td>
+ </tr>
+
+ <tr>
+ <td>power_psc_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
++ <td> Disable the Power Stage Controller module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
+ </tr>
+
+ <tr>
+ <td>power_psc_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
++ <td> Enable the Power Stage Controller module </td>
++ <td>ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1</td>
+ </tr>
+
+ <tr>
+ <td>power_pscr_disable()</td>
+ <td>Disable the Reduced Power Stage Controller module.</td>
+- <td>AT90PWM81, AT90PWM161</td>
++ <td>AT90PWM81, AT90PWM161</td>
+ </tr>
+
+ <tr>
+ <td>power_pscr_enable()</td>
+ <td>Enable the Reduced Power Stage Controller module.</td>
+- <td>AT90PWM81, AT90PWM161</td>
++ <td>AT90PWM81, AT90PWM161</td>
+ </tr>
+
+ <tr>
+ <td>power_ram0_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Disable Ram0 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram0_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Enable Ram0 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram1_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Disable Ram1 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram1_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Enable Ram1 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram2_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Disable Ram2 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram2_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Enable Ram2 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram3_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Disable Ram3 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+ <td>power_ram3_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td> Enable Ram3 module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
++ </tr>
++
++ <tr>
++ <td>power_receive_dsp_control_disable()</td>
++ <td>Disable Receive DSP control module</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_receive_dsp_control_enable()</td>
++ <td>Enable Receive DSP control module</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_rssi_buffer_disable()</td>
++ <td>Disable RSSI buffer</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_rssi_buffer_enable()</td>
++ <td>Enable RSSI buffer</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_rtc_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the RTC module </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_rtc_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the RTC module </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_sci_disable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Disable the SCI module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_sci_enable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Enable the SCI module </td>
++ <td>AT90SCR100</td>
++ </tr>
++
++ <tr>
++ <td>power_sequencer_state_machine_disable()</td>
++ <td>Disable power sequencer state machine</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_sequencer_state_machine_enable()</td>
++ <td>Enable power sequencer state machine</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_spi_disable()</td>
+ <td>Disable the Serial Peripheral Interface module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_spi_enable()</td>
+ <td>Enable the Serial Peripheral Interface module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_spic_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the SPI module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
++ </tr>
++
++ <tr>
++ <td>power_spic_disalbe()</td>
++ <td> Disable SPI module on PortC </td>
++ <td>ATxmega32E5</td>
+ </tr>
+
+ <tr>
+ <td>power_spic_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the SPI module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spid_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Disable the SPI module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spid_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Enable the SPI module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spie_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the SPI module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spie_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the SPI module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spif_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the SPI module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_spif_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the SPI module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0c_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the TC0 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0c_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the TC0 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0d_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Disable the TC0 module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0d_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Enable the TC0 module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0e_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the TC0 module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0e_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the TC0 module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0f_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Disable the TC0 module on PortF </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc0f_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Enable the TC0 module on PortF </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1c_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the TC1 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1c_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the TC1 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1d_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the TC1 module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1d_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the TC1 module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1e_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the TC1 module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1e_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the TC1 module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1f_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the TC1 module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_tc1f_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc4c_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc4c_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc5c_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc5c_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc5d_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
+- </tr>
+-
+- <tr>
+- <td>power_tc5d_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td> Enable the TC1 module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_timer0_disable()</td>
+ <td>Disable the Timer 0 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_timer0_enable()</td>
+ <td>Enable the Timer 0 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_timer1_disable()</td>
+ <td>Disable the Timer 1 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_timer1_enable()</td>
+ <td>Enable the Timer 1 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATA5790, ATA5790N, ATA5795, ATA5831, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_timer2_disable()</td>
+ <td>Disable the Timer 2 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATA5790, ATA5795, AT90SCR100</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATtiny841, ATmega1284, ATmega1284P, ATA5790, ATA5790N, ATA5795, ATA5831, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_timer2_enable()</td>
+ <td>Enable the Timer 2 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATA5790, ATA5795, AT90SCR100</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATtiny841, ATmega1284, ATmega1284P, ATA5790, ATA5790N, ATA5795, ATA5831, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_timer3_disable()</td>
+ <td>Disable the Timer 3 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega1284, ATmega1284P, ATA5790, ATA5795</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega1284, ATmega1284P, ATA5790, ATA5790N, ATA5795, ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_timer3_enable()</td>
+ <td>Enable the Timer 3 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega1284, ATmega1284P, ATA5790, ATA5795</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega1284, ATmega1284P, ATA5790, ATA5790N, ATA5795, ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_timer4_disable()</td>
+ <td>Disable the Timer 4 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_timer4_enable()</td>
+ <td>Enable the Timer 4 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_timer5_disable()</td>
+- <td>Disable the Timer 5 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>power_timermodulator_disable()</td>
++ <td> Disable the TIMERMODULATOR module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+- <td>power_timer5_enable()</td>
+- <td>Enable the Timer 5 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>power_timermodulator_enable()</td>
++ <td> Enable the TIMERMODULATOR module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+- <td>power_timermodulator_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td>power_transceiver_disable()</td>
++ <td> Disable transceiver module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+- <td>power_timermodulator_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td>power_transceiver_enable()</td>
++ <td> Enable transceiver module </td>
++ <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2</td>
+ </tr>
+
+ <tr>
+- <td>power_transceiver_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>power_transmit_dsp_control_disable()</td>
++ <td>Disable Transmit DSP control module</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_transceiver_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega256RFR2, ATmega128RFR2, ATmega64RFR2</td>
++ <td>power_transmit_dsp_control_enable()</td>
++ <td>Enable Transmit DSP control module</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_twi_disable()</td>
+ <td>Disable the Two Wire Interface module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_twi_enable()</td>
+ <td>Enable the Two Wire Interface module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATtiny841, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40</td>
+ </tr>
+
+ <tr>
+ <td>power_twic_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td>Disable the Two Wire Interface module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twic_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td>Enable the Two Wire Interface module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twid_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>Disable the Two Wire Interface module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twid_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>Enable the Two Wire Interface module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twie_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td>Disable the Two Wire Interface module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twie_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td>Enable the Two Wire Interface module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twif_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>Disable the Two Wire Interface module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_twif_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td>Disable the Two Wire Interface module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
++ </tr>
++
++ <tr>
++ <td>power_tx_modulator_disable()</td>
++ <td>Disable Tx modulator</td>
++ <td>ATA5831</td>
++ </tr>
++
++ <tr>
++ <td>power_tx_modulator_enable()</td>
++ <td>Enable Tx modulator</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+ <td>power_usart0_disable()</td>
+ <td>Disable the USART 0 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usart0_enable()</td>
+ <td>Enable the USART 0 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny841, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usart1_disable()</td>
+ <td>Disable the USART 1 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega1284P, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATtiny841, ATmega1284P, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2</td>
+ </tr>
+
+ <tr>
+ <td>power_usart1_enable()</td>
+ <td>Enable the USART 1 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega1284P, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega256RFR2, ATmega128RFR2, ATmega64RFR2, ATmega256RFA2, ATmega128RFA2, ATmega64RFA2, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATtiny841, ATmega1284P, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2</td>
+ </tr>
+
+ <tr>
+ <td>power_usart2_disable()</td>
+ <td>Disable the USART 2 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usart2_enable()</td>
+ <td>Enable the USART 2 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usart3_disable()</td>
+ <td>Disable the USART 3 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usart3_enable()</td>
+ <td>Enable the USART 3 module.</td>
+- <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
++ <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
+ </tr>
+
+ <tr>
+ <td>power_usart_disable()</td>
+ <td>Disable the USART module.</td>
+- <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_usart_enable()</td>
+ <td>Enable the USART module.</td>
+- <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
++ <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316</td>
+ </tr>
+
+ <tr>
+ <td>power_usartc0_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the USART0 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartc0_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the USART0 module on PortC </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartc1_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3</td>
++ <td> Disable the USART1 module on PortC </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartc1_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3</td>
++ <td> Enable the USART1 module on PortC </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd0_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td> Disable the USART0 module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd0_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td> Enable the USART0 module on PortD </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega32E5, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd1_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the USART1 module on PortD </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartd1_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the USART1 module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte0_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Disable the USART0 module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte0_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3</td>
++ <td> Enable the USART0 module on PortE </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte1_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the USART1 module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usarte1_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the USART1 module on PortE </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf0_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Disable the USART0 module on PortF </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf0_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4</td>
++ <td> Enable the USART0 module on PortF </td>
++ <td>ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega16A4, ATxmega16A4U, ATxmega16D4, ATxmega32A4, ATxmega32A4U, ATxmega32D4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega64D3, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega128D3, ATxmega192A3, ATxmega192A3U, ATxmega192D3, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATxmega64D4, ATxmega128D4, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf1_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Disable the USART1 module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usartf1_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3</td>
++ <td> Enable the USART1 module on PortF </td>
++ <td>ATxmega16A4, ATxmega16A4U, ATxmega32A4U, ATxmega32A4, ATxmega64A1, ATxmega64A1U, ATxmega64A3, ATxmega64A3U, ATxmega64A4U, ATxmega128A1, ATxmega128A1U, ATxmega128A3, ATxmega128A3U, ATxmega128A4U, ATxmega192A3, ATxmega192A3U, ATxmega256A3, ATxmega256A3U, ATxmega256A3B, ATxmega256A3BU, ATxmega384C3, ATMXT112SL, ATMXT224, ATMXT224E, ATMXT336S, ATMXT540S, ATMXT540SREVA</td>
+ </tr>
+
+ <tr>
+ <td>power_usb_disable()</td>
+ <td>Disable the USB module.</td>
+- <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100</td>
++ <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usb_enable()</td>
+ <td>Enable the USB module.</td>
+- <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100</td>
++ <td>ATxmega384C3, ATxmega256A3BU, ATxmega16A4U, ATxmega32A4U, ATxmega64A3U, ATxmega64A4U, ATxmega128A3U, ATxmega128A4U, ATxmega192A3U, ATxmega256A3U, ATxmega16C4, ATxmega32C4, ATxmega64C3, ATxmega128C3, ATxmega192C3, ATxmega256C3, ATxmega64B1, ATxmega64B3, ATxmega128B1, ATxmega128B3, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usbh_disable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Disable the USBH module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usbh_enable()</td>
+- <td> Enter Description Here </td>
+- <td>AT90SCR100</td>
++ <td> Enable the USBH module </td>
++ <td>AT90SCR100</td>
+ </tr>
+
+ <tr>
+ <td>power_usi_disable()</td>
+ <td>Disable the Universal Serial Interface module.</td>
+- <td>ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634</td>
++ <td>ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634</td>
+ </tr>
+
+ <tr>
+ <td>power_usi_enable()</td>
+ <td>Enable the Universal Serial Interface module.</td>
+- <td>ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634</td>
++ <td>ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATtiny167, ATtiny87, ATA5505, ATA5272, ATtiny1634</td>
+ </tr>
+
+ <tr>
+ <td>power_vadc_disable()</td>
+ <td>Disable the Voltage ADC module.</td>
+- <td>ATmega406, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB</td>
++ <td>ATmega406, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF</td>
+ </tr>
+
+ <tr>
+ <td>power_vadc_enable()</td>
+ <td>Enable the Voltage ADC module.</td>
+- <td>ATmega406, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB</td>
++ <td>ATmega406, ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF</td>
+ </tr>
+
+ <tr>
+ <td>power_vmonitor_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Disable the VMONITOR module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+ <td>power_vmonitor_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATA5790, ATA5795</td>
++ <td> Enable the VMONITOR module </td>
++ <td>ATA5790, ATA5790N, ATA5795</td>
+ </tr>
+
+ <tr>
+- <td>power_vrm_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB</td>
++ <td>power_voltage_monitor_disable()</td>
++ <td>Disable voltage monitor module</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_vrm_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB</td>
++ <td>power_voltage_monitor_enable()</td>
++ <td>Enable voltage monitor module</td>
++ <td>ATA5831</td>
+ </tr>
+
+ <tr>
+- <td>power_xcl_disable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td>power_vrm_disable()</td>
++ <td> Disable the VRM module </td>
++ <td>ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF</td>
+ </tr>
+
+ <tr>
+- <td>power_xcl_enable()</td>
+- <td> Enter Description Here </td>
+- <td>ATxmega32E5, ATxmega16E5, ATxmega8E5</td>
++ <td>power_vrm_enable()</td>
++ <td> Enable the VRM module </td>
++ <td>ATmega32HVB, ATmega32HVBREVB, ATmega16HVB, ATmega16HVBREVB, ATmega26HVG, ATmega48HVF</td>
+ </tr>
+ </table>
+ </center>
+@@ -1520,12 +1610,10 @@
+ } while(0)
+
+
+-#elif defined(__AVR_ATxmega32E5__) \
+-|| defined(__AVR_ATxmega16E5__) \
+-|| defined(__AVR_ATxmega8E5__)
++#elif defined(__AVR_ATxmega32E5__)
+
+-#define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm))
+-#define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm)
++#define power_cpld_enable() (PR_PRGEN &= (uint8_t)~(PR_CPLD_bm))
++#define power_cpld_disable() (PR_PRGEN |= (uint8_t)PR_CPLD_bm)
+
+ #define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
+ #define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
+@@ -1533,8 +1621,8 @@
+ #define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
+ #define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
+
+-#define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm))
+-#define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm)
++#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
++#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
+
+ #define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
+ #define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
+@@ -1552,38 +1640,38 @@
+ #define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
+
+ #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
+-#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
++#define power_spic_disalbe() (PR_PRPC |= (uint8_t)PR_SPI_bm)
+
+ #define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
+ #define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
+
+-#define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm))
+-#define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm)
++#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
+
+-#define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm))
+-#define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm)
++#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
++#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
+
+ #define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
+ #define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
+
+-#define power_tc5d_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm))
+-#define power_tc5d_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm)
++#define power_tc1d_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1d_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
+
+ #define power_all_enable() \
+ do { \
+- PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm|PR_XCL_bm|PR_EDMA_bm); \
++ PR_PRGEN &= (uint8_t)~(PR_RTC_bm|PR_EVSYS_bm|PR_CPLD_bm|PR_DMA_bm); \
+ PR_PRPA &= (uint8_t)~(PR_ADC_bm|PR_AC_bm|PR_DAC_bm); \
+- PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm); \
+- PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_TC5_bm); \
++ PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPD &= (uint8_t)~(PR_USART0_bm|PR_TC1_bm); \
+ } while(0)
+
+
+ #define power_all_disable() \
+ do { \
+- PR_PRGEN|= (uint8_t)(PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm); \
++ PR_PRGEN|= (uint8_t)(PR_CPLD_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
+ PR_PRPA |= (uint8_t)(PR_ADC_bm|PR_AC_bm|PR_DAC_bm); \
+- PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm); \
+- PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_TC5_bm); \
++ PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPD |= (uint8_t)(PR_USART0_bm|PR_TC1_bm); \
+ } while(0)
+
+
+@@ -1659,6 +1747,131 @@
+ PR_PRPE |= (uint8_t)(PR_USART0_bm|PR_TC0_bm); \
+ } while(0)
+
++#elif defined (__AVR_ATMXT112SL__) \
++|| defined (__AVR_ATMXT224__) \
++|| defined (__AVR_ATMXT224E__) \
++|| defined (__AVR_ATMXT336S__) \
++|| defined (__AVR_ATMXT540S__) \
++|| defined (__AVR_ATMXT540SREVA__)
++
++#define power_ctm_enable() (PR_PRGEN &= (uint8_t)~(PR_CTM_bm))
++#define power_ctm_disable() (PR_PRGEN |= (uint8_t)PR_CTM_bm)
++
++#define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm))
++#define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm)
++
++#define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm))
++#define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm)
++
++#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm))
++#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm)
++
++#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm))
++#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm)
++
++#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm))
++#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm)
++
++#define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm))
++#define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm)
++#define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm))
++#define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm)
++
++#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm))
++#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm)
++#define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm))
++#define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm)
++
++#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm))
++#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm)
++#define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm))
++#define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm)
++
++#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm))
++#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm)
++#define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm))
++#define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm)
++#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm))
++#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm)
++#define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm))
++#define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm)
++
++#define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm))
++#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm)
++#define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm))
++#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm)
++#define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm))
++#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm)
++#define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm))
++#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm)
++
++#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm))
++#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm)
++#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm))
++#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm)
++#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm))
++#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm)
++#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm))
++#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm)
++
++#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm))
++#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm)
++#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm))
++#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm)
++#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm))
++#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm)
++#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm))
++#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm)
++
++#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm))
++#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm)
++#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm))
++#define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm)
++#define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm))
++#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm)
++#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm))
++#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm)
++
++#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm)
++#define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm)
++#define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm)
++#define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm))
++#define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm)
++
++#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm))
++#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm)
++#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm))
++#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm)
++#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm))
++#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm)
++#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm))
++#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm)
++
++#define power_all_enable() \
++do { \
++ PR_PRGEN &= (uint8_t)~(PR_CTM_bm|PR_EBI_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
++ PR_PRPA &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
++ PR_PRPB &= (uint8_t)~(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
++ PR_PRPC &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPD &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPE &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPF &= (uint8_t)~(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ } while(0)
++
++#define power_all_disable() \
++do { \
++ PR_PRGEN |= (uint8_t)(PR_CTM_bm|PR_EBI_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm); \
++ PR_PRPA |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
++ PR_PRPB |= (uint8_t)(PR_DAC_bm|PR_ADC_bm|PR_AC_bm); \
++ PR_PRPC |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPD |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPE |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ PR_PRPF |= (uint8_t)(PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm); \
++ } while(0)
++
+ #elif defined(__AVR_ATmega640__) \
+ || defined(__AVR_ATmega1280__) \
+ || defined(__AVR_ATmega1281__) \
+@@ -1766,7 +1979,10 @@
+
+ #elif defined(__AVR_ATmega256RFR2__) \
+ || defined(__AVR_ATmega128RFR2__) \
+-|| defined(__AVR_ATmega64RFR2__)
++|| defined(__AVR_ATmega64RFR2__) \
++|| defined(__AVR_ATmega256RFA2__) \
++|| defined(__AVR_ATmega128RFA2__) \
++|| defined(__AVR_ATmega64RFA2__)
+
+ #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
+ #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
+@@ -2249,7 +2465,8 @@
+ || defined(__AVR_ATmega168PA__) \
+ || defined(__AVR_ATmega328__) \
+ || defined(__AVR_ATmega328P__) \
+-|| defined(__AVR_ATtiny828__)
++|| defined(__AVR_ATtiny828__) \
++|| defined(__AVR_ATtiny841__)
+
+ #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
+ #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
+@@ -2260,6 +2477,13 @@
+ #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0))
+ #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0))
+
++#if defined(__AVR_ATtiny841__)
++
++#define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1))
++#define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1))
++
++#endif
++
+ #define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
+ #define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
+
+@@ -2281,6 +2505,11 @@
+ #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTWI)))
+ #define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTWI)))
+
++#elif defined(__AVR_ATtiny841__)
++
++#define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
++#define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRUSART1)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
++
+ #else
+
+ #define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM0)|(1<<PRTIM1)|(1<<PRTIM2)|(1<<PRTWI)))
+@@ -2427,7 +2656,9 @@
+ #elif defined(__AVR_ATmega32HVB__) \
+ || defined(__AVR_ATmega32HVBREVB__) \
+ || defined(__AVR_ATmega16HVB__) \
+-|| defined(__AVR_ATmega16HVBREVB__)
++|| defined(__AVR_ATmega16HVBREVB__) \
++|| defined(__AVR_ATmega26HVG__) \
++|| defined(__AVR_ATmega48HVF__)
+
+
+ #define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI))
+@@ -2454,6 +2685,7 @@
+
+
+ #elif defined (__AVR_ATA5790__) \
++|| defined (__AVR_ATA5790N__) \
+ || defined (__AVR_ATA5795__)
+
+ // Enable the voltage monitor
+@@ -2484,7 +2716,8 @@
+ #define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI))
+ #define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI))
+
+-#if defined(__AVR_ATA5790__)
++#if defined(__AVR_ATA5790__) \
++|| defined(__AVR_ATA5790N__)
+
+ #define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR))
+ #define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR))
+@@ -2517,6 +2750,79 @@
+
+ #endif
+
++#elif defined(__AVR_ATA5831__)
++
++#define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO))
++#define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO))
++
++#define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM))
++#define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM))
++
++#define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC))
++#define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC))
++
++#define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC))
++#define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC))
++
++#define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC))
++#define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC))
++
++#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
++#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
++
++#define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1))
++#define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1))
++
++#define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2))
++#define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2))
++
++#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3))
++#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3))
++
++#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4))
++#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4))
++
++#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5))
++#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5))
++
++#define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM))
++#define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM))
++
++#define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM))
++#define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM))
++
++#define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS))
++#define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS))
++
++#define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS))
++#define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS))
++
++#define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF))
++#define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF))
++
++#define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF))
++#define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF))
++
++#define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA))
++#define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA))
++
++#define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB))
++#define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB))
++
++#define power_all_enable() \
++do{ \
++ PRR0 &= (uint8_t)~((1 << PRCO) | (1 << PRVM) | (1 << PRCRC) | (1 << PRTXDC) | (1 << PRRXDC) | (1 << PRSPI)); \
++ PRR1 &= (uint8_t)~((1 << PRT1) | (1 << PRT2) | (1 << PRT3) | (1 << PRT4) | (1 << PRT5)); \
++ PRR2 &= (uint8_t)~((1 << PRSSM) | (1 << PRTM) | (1 << PRRS) | (1 << PRIDS) | (1 << PRDF) | (1 << PRSF) | (1 << PRXA) | (1 << PRXB)); \
++}while(0)
++
++#define power_all_disable() \
++do{ \
++ PRR0 |= (uint8_t)((1 << PRCO) | (1 << PRVM) | (1 << PRCRC) | (1 << PRTXDC) | (1 << PRRXDC) | (1 << PRSPI)); \
++ PRR1 |= (uint8_t)((1 << PRT1) | (1 << PRT2) | (1 << PRT3) | (1 << PRT4) | (1 << PRT5)); \
++ PRR2 |= (uint8_t)((1 << PRSSM) | (1 << PRTM) | (1 << PRRS) | (1 << PRIDS) | (1 << PRDF) | (1 << PRSF) | (1 << PRXA) | (1 << PRXB)); \
++}while(0)
++
+ #elif defined(__AVR_ATmega64HVE__)
+
+
+@@ -2770,6 +3076,7 @@
+ || defined(__AVR_ATmega1281__) \
+ || defined(__AVR_ATmega1284__) \
+ || defined(__AVR_ATmega128RFA1__) \
++|| defined(__AVR_ATmega128RFA2__) \
+ || defined(__AVR_ATmega128RFR2__) \
+ || defined(__AVR_ATmega1284P__) \
+ || defined(__AVR_ATmega162__) \
+@@ -2794,6 +3101,7 @@
+ || defined(__AVR_ATmega16U4__) \
+ || defined(__AVR_ATmega2560__) \
+ || defined(__AVR_ATmega2561__) \
++|| defined(__AVR_ATmega256RFA2__) \
+ || defined(__AVR_ATmega256RFR2__) \
+ || defined(__AVR_ATmega324A__) \
+ || defined(__AVR_ATmega324P__) \
+@@ -2845,6 +3153,7 @@
+ || defined(__AVR_ATmega6490__) \
+ || defined(__AVR_ATmega6490A__) \
+ || defined(__AVR_ATmega6490P__) \
++|| defined(__AVR_ATmega64RFA2__) \
+ || defined(__AVR_ATmega64RFR2__) \
+ || defined(__AVR_ATmega88__) \
+ || defined(__AVR_ATmega88P__) \
+@@ -2901,6 +3210,9 @@
+ clock_div_128 = 7,
+ clock_div_256 = 8
+ #if defined(__AVR_ATmega128RFA1__) \
++|| defined(__AVR_ATmega256RFA2__) \
++|| defined(__AVR_ATmega128RFA2__) \
++|| defined(__AVR_ATmega64RFA2__) \
+ || defined(__AVR_ATmega256RFR2__) \
+ || defined(__AVR_ATmega128RFR2__) \
+ || defined(__AVR_ATmega64RFR2__)
+@@ -2943,11 +3255,13 @@
+ */
+ #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
+
+-#elif defined(__AVR_ATmega16HVB__) \
++#elif defined(__AVR_ATmega48HVF__) \
++|| defined(__AVR_ATmega26HVG__) \
++|| defined(__AVR_ATmega16HVB__) \
+ || defined(__AVR_ATmega16HVBREVB__) \
+ || defined(__AVR_ATmega64HVE__) \
+ || defined(__AVR_ATmega32HVB__) \
+-|| defined(__AVR_ATmega32HVBREVB__)
++|| defined(__AVR_ATmega32HVBREVB__)
+
+ typedef enum
+ {
+@@ -2978,6 +3292,7 @@
+ #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)))
+
+ #elif defined(__AVR_ATA5790__) \
++|| defined (__AVR_ATA5790N__) \
+ || defined (__AVR_ATA5795__)
+
+ typedef enum
+@@ -3050,9 +3365,7 @@
+
+ #define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
+
+-#elif defined(__AVR_ATA6285__) \
+-|| defined(__AVR_ATA6286__) \
+-|| defined(__AVR_ATA6289__)
++#elif defined(__AVR_ATA5831__)
+
+ typedef enum
+ {
+@@ -3083,14 +3396,14 @@
+ "out __SREG__,__tmp_reg__" "\n\t"
+ : /* no outputs */
+ : [temp] "r" (__t),
+- [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
++ [clpr] "I" (_SFR_IO_ADDR(CLPR)),
+ [enable] "r" _BV(CLPCE),
+ [not_CLKPS] "M" (0xFF & (~ ((1 << CLKPS2) | (1 << CLKPS1) | (1 << CLKPS0)))),
+ [set_value] "r" (__x & 7)
+ : "r0");
+ }
+
+-#define system_clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
++#define system_clock_prescale_get() (clock_div_t)(CLPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)))
+
+ typedef enum
+ {
+@@ -3121,14 +3434,14 @@
+ "out __SREG__,__tmp_reg__" "\n\t"
+ : /* no outputs */
+ : [temp] "r" (__t),
+- [clpr] "I" (_SFR_IO_ADDR(CLKPR)),
+- [enable] "r" (_BV(CLPCE)),
++ [clpr] "I" (_SFR_IO_ADDR(CLPR)),
++ [enable] "r" (_BV(CLPCE)),
+ [not_CLTPS] "M" (0xFF & (~ ((1 << CLTPS2) | (1 << CLTPS1) | (1 << CLTPS0)))),
+ [set_value] "r" ((__x & 7) << 3)
+ : "r0");
+ }
+
+-#define timer_clock_prescale_get() (timer_clock_div_t)(CLKPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
++#define timer_clock_prescale_get() (timer_clock_div_t)(CLPR & (uint8_t)((1<<CLTPS0)|(1<<CLTPS1)|(1<<CLTPS2)))
+
+ #elif defined(__AVR_ATtiny24__) \
+ || defined(__AVR_ATtiny24A__) \
+@@ -3183,6 +3496,43 @@
+ : "r0");
+ }
+
++
++#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
++
++#elif defined(__AVR_ATtiny841__)
++
++typedef enum
++{
++ clock_div_1 = 0,
++ clock_div_2 = 1,
++ clock_div_4 = 2,
++ clock_div_8 = 3,
++ clock_div_16 = 4,
++ clock_div_32 = 5,
++ clock_div_64 = 6,
++ clock_div_128 = 7,
++ clock_div_256 = 8
++} clock_div_t;
++
++static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
++
++void clock_prescale_set(clock_div_t __x)
++{
++
++ __asm__ __volatile__ (
++ "in __tmp_reg__,__SREG__" "\n\t"
++ "cli" "\n\t"
++ "sts %2, %3" "\n\t"
++ "sts %1, %0" "\n\t"
++ "out __SREG__, __tmp_reg__"
++ : /* no outputs */
++ : "d" (__x),
++ "M" (_SFR_MEM_ADDR(CLKPR)),
++ "M" (_SFR_MEM_ADDR(CCP)),
++ "r" ((uint8_t)0xD8)
++ : "r0");
++}
++
+
+ #define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
+
+diff -urN avr-libc-1.8.0.orig/include/avr/sleep.h avr-libc-1.8.0/include/avr/sleep.h
+--- avr-libc-1.8.0.orig/include/avr/sleep.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/sleep.h 2013-01-18 09:50:27.000000000 +0100
+@@ -211,7 +211,8 @@
+
+ #elif defined(__AVR_ATtiny167__) \
+ || defined(__AVR_ATtiny87__) \
+-|| defined(__AVR_ATtiny828__)
++|| defined(__AVR_ATtiny828__) \
++|| defined(__AVR_ATtiny841__)
+
+ #define SLEEP_MODE_IDLE 0
+ #define SLEEP_MODE_ADC _BV(SM0)
+@@ -259,6 +260,20 @@
+ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+ } while(0)
+
++#elif defined(__AVR_ATmega48HVF__) \
++|| defined(__AVR_ATmega26HVG__)
++
++ #define SLEEP_MODE_IDLE (0)
++ #define SLEEP_MODE_ADC _BV(SM0)
++ #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
++ #define SLEEP_MODE_PWR_OFF _BV(SM2)
++
++
++ #define set_sleep_mode(mode) \
++ do { \
++ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
++ } while(0)
++
+ #elif defined(__AVR_ATtiny2313__) \
+ || defined(__AVR_ATtiny2313A__) \
+ || defined(__AVR_ATtiny4313__)
+@@ -339,6 +354,7 @@
+ || defined(__AVR_ATmega1284__) \
+ || defined(__AVR_ATmega1284P__) \
+ || defined(__AVR_ATmega128RFA1__) \
++|| defined(__AVR_ATmega128RFA2__) \
+ || defined(__AVR_ATmega128RFR2__) \
+ || defined(__AVR_ATmega16__) \
+ || defined(__AVR_ATmega16A__) \
+@@ -365,6 +381,7 @@
+ || defined(__AVR_ATmega16U4__) \
+ || defined(__AVR_ATmega2560__) \
+ || defined(__AVR_ATmega2561__) \
++|| defined(__AVR_ATmega256RFA2__) \
+ || defined(__AVR_ATmega256RFR2__) \
+ || defined(__AVR_ATmega32__) \
+ || defined(__AVR_ATmega32A__) \
+@@ -422,6 +439,7 @@
+ || defined(__AVR_ATmega64C1__) \
+ || defined(__AVR_ATmega64HVE__) \
+ || defined(__AVR_ATmega64M1__) \
++|| defined(__AVR_ATmega64RFA2__) \
+ || defined(__AVR_ATmega64RFR2__) \
+ || defined(__AVR_ATmega8__) \
+ || defined(__AVR_ATmega8515__) \
+@@ -461,7 +479,13 @@
+ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
+ } while(0)
+
+-#elif defined(__AVR_ATxmega16A4__) \
++#elif defined(__AVR_ATMXT112SL__) \
++|| defined(__AVR_ATMXT224__) \
++|| defined(__AVR_ATMXT224E__) \
++|| defined(__AVR_ATMXT336S__) \
++|| defined(__AVR_ATMXT540S__) \
++|| defined(__AVR_ATMXT540SREVA__) \
++|| defined(__AVR_ATxmega16A4__) \
+ || defined(__AVR_ATxmega16A4U__) \
+ || defined(__AVR_ATxmega16C4__) \
+ || defined(__AVR_ATxmega16D4__) \
+@@ -469,8 +493,6 @@
+ || defined(__AVR_ATxmega32A4U__) \
+ || defined(__AVR_ATxmega32C4__) \
+ || defined(__AVR_ATxmega32D4__) \
+-|| defined(__AVR_ATxmega8E5__) \
+-|| defined(__AVR_ATxmega16E5__) \
+ || defined(__AVR_ATxmega32E5__) \
+ || defined(__AVR_ATxmega64A1__) \
+ || defined(__AVR_ATxmega64A1U__) \
+@@ -516,6 +538,17 @@
+ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
+ } while(0)
+
++#elif defined(__AVR_ATxmega32X1__)
++ #define SLEEP_MODE_IDLE (0)
++ #define SLEEP_MODE_PWR_SAVE (SLEEP_SMODE0_bm)
++ #define SLEEP_MODE_PWR_DOWN (SLEEP_SMODE1_bm)
++ #define SLEEP_MODE_PWR_OFF (SLEEP_SMODE0_bm | SLEEP_SMODE1_bm)
++
++ #define set_sleep_mode(mode) \
++ do { \
++ _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
++ } while(0)
++
+ #elif defined(__AVR_AT90SCR100__)
+
+ #define SLEEP_MODE_IDLE (0)
+@@ -543,7 +576,9 @@
+ } while(0)
+
+ #elif defined (__AVR_ATA5790__) \
+-|| defined (__AVR_ATA5795__)
++|| defined (__AVR_ATA5790N__) \
++|| defined (__AVR_ATA5795__) \
++|| defined (__AVR_ATA5831__)
+
+ #define SLEEP_MODE_IDLE (0)
+ #define SLEEP_MODE_EXT_PWR_SAVE (_BV(SM0))
+diff -urN avr-libc-1.8.0.orig/include/avr/wdt.h avr-libc-1.8.0/include/avr/wdt.h
+--- avr-libc-1.8.0.orig/include/avr/wdt.h 2013-01-18 09:49:50.000000000 +0100
++++ avr-libc-1.8.0/include/avr/wdt.h 2013-01-18 09:50:27.000000000 +0100
+@@ -132,7 +132,13 @@
+ */
+
+
+-#if defined(__AVR_ATxmega16A4__) \
++#if defined(__AVR_ATMXT112SL__) \
++|| defined(__AVR_ATMXT224__) \
++|| defined(__AVR_ATMXT224E__) \
++|| defined(__AVR_ATMXT336S__) \
++|| defined(__AVR_ATMXT540S__) \
++|| defined(__AVR_ATMXT540SREVA__) \
++|| defined(__AVR_ATxmega16A4__) \
+ || defined(__AVR_ATxmega16A4U__) \
+ || defined(__AVR_ATxmega16C4__) \
+ || defined(__AVR_ATxmega16D4__) \
+@@ -140,8 +146,6 @@
+ || defined(__AVR_ATxmega32A4U__) \
+ || defined(__AVR_ATxmega32C4__) \
+ || defined(__AVR_ATxmega32D4__) \
+-|| defined(__AVR_ATxmega8E5__) \
+-|| defined(__AVR_ATxmega16E5__) \
+ || defined(__AVR_ATxmega32E5__) \
+ || defined(__AVR_ATxmega64A1U__) \
+ || defined(__AVR_ATxmega64A3__) \
+@@ -248,6 +252,7 @@
+ || defined(__AVR_ATmega2561__) \
+ || defined(__AVR_ATmega256RFA2__) \
+ || defined(__AVR_ATmega256RFR2__) \
++|| defined(__AVR_ATmega26HVG__) \
+ || defined(__AVR_ATmega32A__) \
+ || defined(__AVR_ATmega324__) \
+ || defined(__AVR_ATmega324A__) \
+@@ -279,6 +284,7 @@
+ || defined(__AVR_ATmega32U4__) \
+ || defined(__AVR_ATmega32U6__) \
+ || defined(__AVR_ATmega406__) \
++|| defined(__AVR_ATmega48HVF__) \
+ || defined(__AVR_ATmega48__) \
+ || defined(__AVR_ATmega48A__) \
+ || defined(__AVR_ATmega48PA__) \
+@@ -324,7 +330,9 @@
+ || defined(__AVR_ATA5272__) \
+ || defined(__AVR_ATA5505__) \
+ || defined(__AVR_ATA5790__) \
+-|| defined(__AVR_ATA5795__)
++|| defined(__AVR_ATA5790N__) \
++|| defined(__AVR_ATA5795__) \
++|| defined(__AVR_ATA5831__)
+
+ /* Use STS instruction. */
+
+@@ -357,6 +365,50 @@
+ : "r0" \
+ )
+
++
++#elif defined(__AVR_ATtiny841__)
++
++/* Use STS instruction. */
++
++#define wdt_enable(value) \
++__asm__ __volatile__ ( \
++ "in __tmp_reg__,__SREG__" "\n\t" \
++ "cli" "\n\t" \
++ "wdr" "\n\t" \
++ "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
++ "out %[WDTREG],%[WDVALUE]" "\n\t" \
++ "out __SREG__,__tmp_reg__" "\n\t" \
++ : /* no outputs */ \
++ : [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
++ [SIGNATURE] "r" ((uint8_t)0xD8), \
++ [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
++ [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \
++ | _BV(WDE) | (value & 0x07) )) \
++ : "r0" \
++)
++
++#define wdt_disable() \
++do { \
++uint8_t temp_wd; \
++__asm__ __volatile__ ( \
++ "in __tmp_reg__,__SREG__" "\n\t" \
++ "cli" "\n\t" \
++ "wdr" "\n\t" \
++ "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" \
++ "in %[TEMP_WD],%[WDTREG]" "\n\t" \
++ "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \
++ "out %[WDTREG],%[TEMP_WD]" "\n\t" \
++ "out __SREG__,__tmp_reg__" "\n\t" \
++ : /*no output */ \
++ : [CCPADDRESS] "M" (_SFR_MEM_ADDR(CCP)), \
++ [SIGNATURE] "r" ((uint8_t)0xD8), \
++ [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
++ [TEMP_WD] "d" (temp_wd), \
++ [WDVALUE] "I" (1 << WDE) \
++ : "r0" \
++); \
++}while(0)
++
+ #elif defined(__AVR_ATtiny1634__) \
+ || defined(__AVR_ATtiny828__)
+
+@@ -488,6 +540,7 @@
+ || defined(__AVR_M3000__)
+ #undef wdt_enable
+ #undef wdt_disale
++
+ #else
+
+ /* Use OUT instruction. */
+@@ -595,8 +648,8 @@
+ ATmega48P, ATmega88P, ATmega168P, ATmega328P,
+ ATmega164P, ATmega324P, ATmega644P, ATmega644,
+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
+- ATmega8HVA, ATmega16HVA, ATmega32HVB,
+- ATmega406, ATmega1284P,
++ ATmega8HVA, ATmega16HVA, ATmega26HVG, ATmega32HVB,
++ ATmega406, ATmega48HVF, ATmega1284P,
+ ATmega256RFA2, ATmega256RFR2, ATmega128RFA2, ATmega128RFR2, ATmega64RFA2, ATmega64RFR2,
+ AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
+ AT90PWM81, AT90PWM161,
+@@ -617,8 +670,8 @@
+ ATmega48P, ATmega88P, ATmega168P, ATmega328P,
+ ATmega164P, ATmega324P, ATmega644P, ATmega644,
+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
+- ATmega8HVA, ATmega16HVA, ATmega32HVB,
+- ATmega406, ATmega1284P,
++ ATmega8HVA, ATmega16HVA, ATmega26HVG, ATmega32HVB,
++ ATmega406, ATmega48HVF, ATmega1284P,
+ ATmega256RFA2, ATmega256RFR2, ATmega128RFA2, ATmega128RFR2, ATmega64RFA2, ATmega64RFR2,
+ AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
+ AT90PWM81, AT90PWM161,
+diff -urN avr-libc-1.8.0.orig/include/avr/iom128rfr2.h avr-libc-1.8.0/include/avr/iom128rfr2.h
+--- avr-libc-1.8.0.orig/include/avr/iom128rfr2.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom128rfr2.h 2013-01-18 10:08:38.000000000 +0100
+@@ -0,0 +1,2571 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA128RFR2_H_INCLUDED
++#define _AVR_ATMEGA128RFR2_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom128rfr2.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++#define Res0 3
++#define Res1 4
++#define Res2 5
++#define Res3 6
++#define Res4 7
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define OCF1C 3
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++#define TIFR3 _SFR_IO8(0x18)
++#define TOV3 0
++#define OCF3A 1
++#define OCF3B 2
++#define OCF3C 3
++#define ICF3 5
++
++#define TIFR4 _SFR_IO8(0x19)
++#define TOV4 0
++#define OCF4A 1
++#define OCF4B 2
++#define OCF4C 3
++#define ICF4 5
++
++#define TIFR5 _SFR_IO8(0x1A)
++#define TOV5 0
++#define OCF5A 1
++#define OCF5B 2
++#define OCF5C 3
++#define ICF5 5
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++#define INTF3 3
++#define INTF4 4
++#define INTF5 5
++#define INTF6 6
++#define INTF7 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++#define INT3 3
++#define INT4 4
++#define INT5 5
++#define INT6 6
++#define INT7 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define PSRASY 1
++#define TSM 7
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR0 0
++#define OCDR1 1
++#define OCDR2 2
++#define OCDR3 3
++#define OCDR4 4
++#define OCDR5 5
++#define OCDR6 6
++#define OCDR7 7
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3A] */
++
++#define RAMPZ _SFR_IO8(0x3B)
++#define RAMPZ0 0
++#define Res5 6
++#define Res6 7
++
++/* Reserved [0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62] */
++
++#define PRR2 _SFR_MEM8(0x63)
++#define PRRAM0 0
++#define PRRAM1 1
++#define PRRAM2 2
++#define PRRAM3 3
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRPGA 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++#define PRR1 _SFR_MEM8(0x65)
++#define PRUSART1 0
++#define PRTIM3 3
++#define PRTIM4 4
++#define PRTIM5 5
++#define PRTRX24 6
++#define Res 7
++
++#define OSCCAL _SFR_MEM8(0x66)
++#define CAL0 0
++#define CAL1 1
++#define CAL2 2
++#define CAL3 3
++#define CAL4 4
++#define CAL5 5
++#define CAL6 6
++#define CAL7 7
++
++#define BGCR _SFR_MEM8(0x67)
++#define BGCAL0 0
++#define BGCAL1 1
++#define BGCAL2 2
++#define BGCAL_FINE0 3
++#define BGCAL_FINE1 4
++#define BGCAL_FINE2 5
++#define BGCAL_FINE3 6
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++#define ISC30 6
++#define ISC31 7
++
++#define EICRB _SFR_MEM8(0x6A)
++#define ISC40 0
++#define ISC41 1
++#define ISC50 2
++#define ISC51 3
++#define ISC60 4
++#define ISC61 5
++#define ISC70 6
++#define ISC71 7
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define OCIE1C 3
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++#define TIMSK3 _SFR_MEM8(0x71)
++#define TOIE3 0
++#define OCIE3A 1
++#define OCIE3B 2
++#define OCIE3C 3
++#define ICIE3 5
++
++#define TIMSK4 _SFR_MEM8(0x72)
++#define TOIE4 0
++#define OCIE4A 1
++#define OCIE4B 2
++#define OCIE4C 3
++#define ICIE4 5
++
++#define TIMSK5 _SFR_MEM8(0x73)
++#define TOIE5 0
++#define OCIE5A 1
++#define OCIE5B 2
++#define OCIE5C 3
++#define ICIE5 5
++
++/* Reserved [0x74] */
++
++#define NEMCR _SFR_MEM8(0x75)
++#define AEAM0 4
++#define AEAM1 5
++#define ENEAM 6
++
++/* Reserved [0x76] */
++
++#define ADCSRC _SFR_MEM8(0x77)
++#define ADSUT0 0
++#define ADSUT1 1
++#define ADSUT2 2
++#define ADSUT3 3
++#define ADSUT4 4
++#define ADTHT0 6
++#define ADTHT1 7
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define MUX5 3
++#define ACCH 4
++#define REFOK 5
++#define AVDDOK 7
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define DIDR2 _SFR_MEM8(0x7D)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++#define ADC11D 3
++#define ADC12D 4
++#define ADC13D 5
++#define ADC14D 6
++#define ADC15D 7
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1C0 2
++#define COM1C1 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1C 5
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Combine OCR1CL and OCR1CH */
++#define OCR1C _SFR_MEM16(0x8C)
++
++#define OCR1CL _SFR_MEM8(0x8C)
++#define OCR1CH _SFR_MEM8(0x8D)
++
++/* Reserved [0x8E..0x8F] */
++
++#define TCCR3A _SFR_MEM8(0x90)
++#define WGM30 0
++#define WGM31 1
++#define COM3C0 2
++#define COM3C1 3
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3B _SFR_MEM8(0x91)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3C _SFR_MEM8(0x92)
++#define FOC3C 5
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x93] */
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x94)
++
++#define TCNT3L _SFR_MEM8(0x94)
++#define TCNT3H _SFR_MEM8(0x95)
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x96)
++
++#define ICR3L _SFR_MEM8(0x96)
++#define ICR3H _SFR_MEM8(0x97)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x98)
++
++#define OCR3AL _SFR_MEM8(0x98)
++#define OCR3AH _SFR_MEM8(0x99)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x9A)
++
++#define OCR3BL _SFR_MEM8(0x9A)
++#define OCR3BH _SFR_MEM8(0x9B)
++
++/* Combine OCR3CL and OCR3CH */
++#define OCR3C _SFR_MEM16(0x9C)
++
++#define OCR3CL _SFR_MEM8(0x9C)
++#define OCR3CH _SFR_MEM8(0x9D)
++
++/* Reserved [0x9E..0x9F] */
++
++#define TCCR4A _SFR_MEM8(0xA0)
++#define WGM40 0
++#define WGM41 1
++#define COM4C0 2
++#define COM4C1 3
++#define COM4B0 4
++#define COM4B1 5
++#define COM4A0 6
++#define COM4A1 7
++
++#define TCCR4B _SFR_MEM8(0xA1)
++#define CS40 0
++#define CS41 1
++#define CS42 2
++#define WGM42 3
++#define WGM43 4
++#define ICES4 6
++#define ICNC4 7
++
++#define TCCR4C _SFR_MEM8(0xA2)
++#define FOC4C 5
++#define FOC4B 6
++#define FOC4A 7
++
++/* Reserved [0xA3] */
++
++/* Combine TCNT4L and TCNT4H */
++#define TCNT4 _SFR_MEM16(0xA4)
++
++#define TCNT4L _SFR_MEM8(0xA4)
++#define TCNT4H _SFR_MEM8(0xA5)
++
++/* Combine ICR4L and ICR4H */
++#define ICR4 _SFR_MEM16(0xA6)
++
++#define ICR4L _SFR_MEM8(0xA6)
++#define ICR4H _SFR_MEM8(0xA7)
++
++/* Combine OCR4AL and OCR4AH */
++#define OCR4A _SFR_MEM16(0xA8)
++
++#define OCR4AL _SFR_MEM8(0xA8)
++#define OCR4AH _SFR_MEM8(0xA9)
++
++/* Combine OCR4BL and OCR4BH */
++#define OCR4B _SFR_MEM16(0xAA)
++
++#define OCR4BL _SFR_MEM8(0xAA)
++#define OCR4BH _SFR_MEM8(0xAB)
++
++/* Combine OCR4CL and OCR4CH */
++#define OCR4C _SFR_MEM16(0xAC)
++
++#define OCR4CL _SFR_MEM8(0xAC)
++#define OCR4CH _SFR_MEM8(0xAD)
++
++/* Reserved [0xAE..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++#define EXCLKAMR 7
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++#define IRQ_MASK1 _SFR_MEM8(0xBE)
++#define TX_START_EN 0
++#define MAF_0_AMI_EN 1
++#define MAF_1_AMI_EN 2
++#define MAF_2_AMI_EN 3
++#define MAF_3_AMI_EN 4
++
++#define IRQ_STATUS1 _SFR_MEM8(0xBF)
++#define TX_START 0
++#define MAF_0_AMI 1
++#define MAF_1_AMI 2
++#define MAF_2_AMI 3
++#define MAF_3_AMI 4
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++#define UCPHA0 1
++#define UDORD0 2
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++#define UCPHA1 1
++#define UDORD1 2
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++/* Reserved [0xCF..0xD6] */
++
++#define SCRSTRLL _SFR_MEM8(0xD7)
++#define SCRSTRLL0 0
++#define SCRSTRLL1 1
++#define SCRSTRLL2 2
++#define SCRSTRLL3 3
++#define SCRSTRLL4 4
++#define SCRSTRLL5 5
++#define SCRSTRLL6 6
++#define SCRSTRLL7 7
++
++#define SCRSTRLH _SFR_MEM8(0xD8)
++#define SCRSTRLH0 0
++#define SCRSTRLH1 1
++#define SCRSTRLH2 2
++#define SCRSTRLH3 3
++#define SCRSTRLH4 4
++#define SCRSTRLH5 5
++#define SCRSTRLH6 6
++#define SCRSTRLH7 7
++
++#define SCRSTRHL _SFR_MEM8(0xD9)
++#define SCRSTRHL0 0
++#define SCRSTRHL1 1
++#define SCRSTRHL2 2
++#define SCRSTRHL3 3
++#define SCRSTRHL4 4
++#define SCRSTRHL5 5
++#define SCRSTRHL6 6
++#define SCRSTRHL7 7
++
++#define SCRSTRHH _SFR_MEM8(0xDA)
++#define SCRSTRHH0 0
++#define SCRSTRHH1 1
++#define SCRSTRHH2 2
++#define SCRSTRHH3 3
++#define SCRSTRHH4 4
++#define SCRSTRHH5 5
++#define SCRSTRHH6 6
++#define SCRSTRHH7 7
++
++#define SCCSR _SFR_MEM8(0xDB)
++#define SCCS10 0
++#define SCCS11 1
++#define SCCS20 2
++#define SCCS21 3
++#define SCCS30 4
++#define SCCS31 5
++
++#define SCCR0 _SFR_MEM8(0xDC)
++#define SCCMP1 0
++#define SCCMP2 1
++#define SCCMP3 2
++#define SCTSE 3
++#define SCCKSEL 4
++#define SCEN 5
++#define SCMBTS 6
++#define SCRES 7
++
++#define SCCR1 _SFR_MEM8(0xDD)
++#define SCENBO 0
++#define SCEECLK 1
++#define SCCKDIV0 2
++#define SCCKDIV1 3
++#define SCCKDIV2 4
++#define SCBTSM 5
++
++#define SCSR _SFR_MEM8(0xDE)
++#define SCBSY 0
++
++#define SCIRQM _SFR_MEM8(0xDF)
++#define IRQMCP1 0
++#define IRQMCP2 1
++#define IRQMCP3 2
++#define IRQMOF 3
++#define IRQMBO 4
++
++#define SCIRQS _SFR_MEM8(0xE0)
++#define IRQSCP1 0
++#define IRQSCP2 1
++#define IRQSCP3 2
++#define IRQSOF 3
++#define IRQSBO 4
++
++#define SCCNTLL _SFR_MEM8(0xE1)
++#define SCCNTLL0 0
++#define SCCNTLL1 1
++#define SCCNTLL2 2
++#define SCCNTLL3 3
++#define SCCNTLL4 4
++#define SCCNTLL5 5
++#define SCCNTLL6 6
++#define SCCNTLL7 7
++
++#define SCCNTLH _SFR_MEM8(0xE2)
++#define SCCNTLH0 0
++#define SCCNTLH1 1
++#define SCCNTLH2 2
++#define SCCNTLH3 3
++#define SCCNTLH4 4
++#define SCCNTLH5 5
++#define SCCNTLH6 6
++#define SCCNTLH7 7
++
++#define SCCNTHL _SFR_MEM8(0xE3)
++#define SCCNTHL0 0
++#define SCCNTHL1 1
++#define SCCNTHL2 2
++#define SCCNTHL3 3
++#define SCCNTHL4 4
++#define SCCNTHL5 5
++#define SCCNTHL6 6
++#define SCCNTHL7 7
++
++#define SCCNTHH _SFR_MEM8(0xE4)
++#define SCCNTHH0 0
++#define SCCNTHH1 1
++#define SCCNTHH2 2
++#define SCCNTHH3 3
++#define SCCNTHH4 4
++#define SCCNTHH5 5
++#define SCCNTHH6 6
++#define SCCNTHH7 7
++
++#define SCBTSRLL _SFR_MEM8(0xE5)
++#define SCBTSRLL0 0
++#define SCBTSRLL1 1
++#define SCBTSRLL2 2
++#define SCBTSRLL3 3
++#define SCBTSRLL4 4
++#define SCBTSRLL5 5
++#define SCBTSRLL6 6
++#define SCBTSRLL7 7
++
++#define SCBTSRLH _SFR_MEM8(0xE6)
++#define SCBTSRLH0 0
++#define SCBTSRLH1 1
++#define SCBTSRLH2 2
++#define SCBTSRLH3 3
++#define SCBTSRLH4 4
++#define SCBTSRLH5 5
++#define SCBTSRLH6 6
++#define SCBTSRLH7 7
++
++#define SCBTSRHL _SFR_MEM8(0xE7)
++#define SCBTSRHL0 0
++#define SCBTSRHL1 1
++#define SCBTSRHL2 2
++#define SCBTSRHL3 3
++#define SCBTSRHL4 4
++#define SCBTSRHL5 5
++#define SCBTSRHL6 6
++#define SCBTSRHL7 7
++
++#define SCBTSRHH _SFR_MEM8(0xE8)
++#define SCBTSRHH0 0
++#define SCBTSRHH1 1
++#define SCBTSRHH2 2
++#define SCBTSRHH3 3
++#define SCBTSRHH4 4
++#define SCBTSRHH5 5
++#define SCBTSRHH6 6
++#define SCBTSRHH7 7
++
++#define SCTSRLL _SFR_MEM8(0xE9)
++#define SCTSRLL0 0
++#define SCTSRLL1 1
++#define SCTSRLL2 2
++#define SCTSRLL3 3
++#define SCTSRLL4 4
++#define SCTSRLL5 5
++#define SCTSRLL6 6
++#define SCTSRLL7 7
++
++#define SCTSRLH _SFR_MEM8(0xEA)
++#define SCTSRLH0 0
++#define SCTSRLH1 1
++#define SCTSRLH2 2
++#define SCTSRLH3 3
++#define SCTSRLH4 4
++#define SCTSRLH5 5
++#define SCTSRLH6 6
++#define SCTSRLH7 7
++
++#define SCTSRHL _SFR_MEM8(0xEB)
++#define SCTSRHL0 0
++#define SCTSRHL1 1
++#define SCTSRHL2 2
++#define SCTSRHL3 3
++#define SCTSRHL4 4
++#define SCTSRHL5 5
++#define SCTSRHL6 6
++#define SCTSRHL7 7
++
++#define SCTSRHH _SFR_MEM8(0xEC)
++#define SCTSRHH0 0
++#define SCTSRHH1 1
++#define SCTSRHH2 2
++#define SCTSRHH3 3
++#define SCTSRHH4 4
++#define SCTSRHH5 5
++#define SCTSRHH6 6
++#define SCTSRHH7 7
++
++#define SCOCR3LL _SFR_MEM8(0xED)
++#define SCOCR3LL0 0
++#define SCOCR3LL1 1
++#define SCOCR3LL2 2
++#define SCOCR3LL3 3
++#define SCOCR3LL4 4
++#define SCOCR3LL5 5
++#define SCOCR3LL6 6
++#define SCOCR3LL7 7
++
++#define SCOCR3LH _SFR_MEM8(0xEE)
++#define SCOCR3LH0 0
++#define SCOCR3LH1 1
++#define SCOCR3LH2 2
++#define SCOCR3LH3 3
++#define SCOCR3LH4 4
++#define SCOCR3LH5 5
++#define SCOCR3LH6 6
++#define SCOCR3LH7 7
++
++#define SCOCR3HL _SFR_MEM8(0xEF)
++#define SCOCR3HL0 0
++#define SCOCR3HL1 1
++#define SCOCR3HL2 2
++#define SCOCR3HL3 3
++#define SCOCR3HL4 4
++#define SCOCR3HL5 5
++#define SCOCR3HL6 6
++#define SCOCR3HL7 7
++
++#define SCOCR3HH _SFR_MEM8(0xF0)
++#define SCOCR3HH0 0
++#define SCOCR3HH1 1
++#define SCOCR3HH2 2
++#define SCOCR3HH3 3
++#define SCOCR3HH4 4
++#define SCOCR3HH5 5
++#define SCOCR3HH6 6
++#define SCOCR3HH7 7
++
++#define SCOCR2LL _SFR_MEM8(0xF1)
++#define SCOCR2LL0 0
++#define SCOCR2LL1 1
++#define SCOCR2LL2 2
++#define SCOCR2LL3 3
++#define SCOCR2LL4 4
++#define SCOCR2LL5 5
++#define SCOCR2LL6 6
++#define SCOCR2LL7 7
++
++#define SCOCR2LH _SFR_MEM8(0xF2)
++#define SCOCR2LH0 0
++#define SCOCR2LH1 1
++#define SCOCR2LH2 2
++#define SCOCR2LH3 3
++#define SCOCR2LH4 4
++#define SCOCR2LH5 5
++#define SCOCR2LH6 6
++#define SCOCR2LH7 7
++
++#define SCOCR2HL _SFR_MEM8(0xF3)
++#define SCOCR2HL0 0
++#define SCOCR2HL1 1
++#define SCOCR2HL2 2
++#define SCOCR2HL3 3
++#define SCOCR2HL4 4
++#define SCOCR2HL5 5
++#define SCOCR2HL6 6
++#define SCOCR2HL7 7
++
++#define SCOCR2HH _SFR_MEM8(0xF4)
++#define SCOCR2HH0 0
++#define SCOCR2HH1 1
++#define SCOCR2HH2 2
++#define SCOCR2HH3 3
++#define SCOCR2HH4 4
++#define SCOCR2HH5 5
++#define SCOCR2HH6 6
++#define SCOCR2HH7 7
++
++#define SCOCR1LL _SFR_MEM8(0xF5)
++#define SCOCR1LL0 0
++#define SCOCR1LL1 1
++#define SCOCR1LL2 2
++#define SCOCR1LL3 3
++#define SCOCR1LL4 4
++#define SCOCR1LL5 5
++#define SCOCR1LL6 6
++#define SCOCR1LL7 7
++
++#define SCOCR1LH _SFR_MEM8(0xF6)
++#define SCOCR1LH0 0
++#define SCOCR1LH1 1
++#define SCOCR1LH2 2
++#define SCOCR1LH3 3
++#define SCOCR1LH4 4
++#define SCOCR1LH5 5
++#define SCOCR1LH6 6
++#define SCOCR1LH7 7
++
++#define SCOCR1HL _SFR_MEM8(0xF7)
++#define SCOCR1HL0 0
++#define SCOCR1HL1 1
++#define SCOCR1HL2 2
++#define SCOCR1HL3 3
++#define SCOCR1HL4 4
++#define SCOCR1HL5 5
++#define SCOCR1HL6 6
++#define SCOCR1HL7 7
++
++#define SCOCR1HH _SFR_MEM8(0xF8)
++#define SCOCR1HH0 0
++#define SCOCR1HH1 1
++#define SCOCR1HH2 2
++#define SCOCR1HH3 3
++#define SCOCR1HH4 4
++#define SCOCR1HH5 5
++#define SCOCR1HH6 6
++#define SCOCR1HH7 7
++
++#define SCTSTRLL _SFR_MEM8(0xF9)
++#define SCTSTRLL0 0
++#define SCTSTRLL1 1
++#define SCTSTRLL2 2
++#define SCTSTRLL3 3
++#define SCTSTRLL4 4
++#define SCTSTRLL5 5
++#define SCTSTRLL6 6
++#define SCTSTRLL7 7
++
++#define SCTSTRLH _SFR_MEM8(0xFA)
++#define SCTSTRLH0 0
++#define SCTSTRLH1 1
++#define SCTSTRLH2 2
++#define SCTSTRLH3 3
++#define SCTSTRLH4 4
++#define SCTSTRLH5 5
++#define SCTSTRLH6 6
++#define SCTSTRLH7 7
++
++#define SCTSTRHL _SFR_MEM8(0xFB)
++#define SCTSTRHL0 0
++#define SCTSTRHL1 1
++#define SCTSTRHL2 2
++#define SCTSTRHL3 3
++#define SCTSTRHL4 4
++#define SCTSTRHL5 5
++#define SCTSTRHL6 6
++#define SCTSTRHL7 7
++
++#define SCTSTRHH _SFR_MEM8(0xFC)
++#define SCTSTRHH0 0
++#define SCTSTRHH1 1
++#define SCTSTRHH2 2
++#define SCTSTRHH3 3
++#define SCTSTRHH4 4
++#define SCTSTRHH5 5
++#define SCTSTRHH6 6
++#define SCTSTRHH7 7
++
++/* Reserved [0xFD..0x10B] */
++
++#define MAFCR0 _SFR_MEM8(0x10C)
++#define MAF0EN 0
++#define MAF1EN 1
++#define MAF2EN 2
++#define MAF3EN 3
++
++#define MAFCR1 _SFR_MEM8(0x10D)
++#define AACK_0_I_AM_COORD 0
++#define AACK_0_SET_PD 1
++#define AACK_1_I_AM_COORD 2
++#define AACK_1_SET_PD 3
++#define AACK_2_I_AM_COORD 4
++#define AACK_2_SET_PD 5
++#define AACK_3_I_AM_COORD 6
++#define AACK_3_SET_PD 7
++
++#define MAFSA0L _SFR_MEM8(0x10E)
++#define MAFSA0L0 0
++#define MAFSA0L1 1
++#define MAFSA0L2 2
++#define MAFSA0L3 3
++#define MAFSA0L4 4
++#define MAFSA0L5 5
++#define MAFSA0L6 6
++#define MAFSA0L7 7
++
++#define MAFSA0H _SFR_MEM8(0x10F)
++#define MAFSA0H0 0
++#define MAFSA0H1 1
++#define MAFSA0H2 2
++#define MAFSA0H3 3
++#define MAFSA0H4 4
++#define MAFSA0H5 5
++#define MAFSA0H6 6
++#define MAFSA0H7 7
++
++#define MAFPA0L _SFR_MEM8(0x110)
++#define MAFPA0L0 0
++#define MAFPA0L1 1
++#define MAFPA0L2 2
++#define MAFPA0L3 3
++#define MAFPA0L4 4
++#define MAFPA0L5 5
++#define MAFPA0L6 6
++#define MAFPA0L7 7
++
++#define MAFPA0H _SFR_MEM8(0x111)
++#define MAFPA0H0 0
++#define MAFPA0H1 1
++#define MAFPA0H2 2
++#define MAFPA0H3 3
++#define MAFPA0H4 4
++#define MAFPA0H5 5
++#define MAFPA0H6 6
++#define MAFPA0H7 7
++
++#define MAFSA1L _SFR_MEM8(0x112)
++#define MAFSA1L0 0
++#define MAFSA1L1 1
++#define MAFSA1L2 2
++#define MAFSA1L3 3
++#define MAFSA1L4 4
++#define MAFSA1L5 5
++#define MAFSA1L6 6
++#define MAFSA1L7 7
++
++#define MAFSA1H _SFR_MEM8(0x113)
++#define MAFSA1H0 0
++#define MAFSA1H1 1
++#define MAFSA1H2 2
++#define MAFSA1H3 3
++#define MAFSA1H4 4
++#define MAFSA1H5 5
++#define MAFSA1H6 6
++#define MAFSA1H7 7
++
++#define MAFPA1L _SFR_MEM8(0x114)
++#define MAFPA1L0 0
++#define MAFPA1L1 1
++#define MAFPA1L2 2
++#define MAFPA1L3 3
++#define MAFPA1L4 4
++#define MAFPA1L5 5
++#define MAFPA1L6 6
++#define MAFPA1L7 7
++
++#define MAFPA1H _SFR_MEM8(0x115)
++#define MAFPA1H0 0
++#define MAFPA1H1 1
++#define MAFPA1H2 2
++#define MAFPA1H3 3
++#define MAFPA1H4 4
++#define MAFPA1H5 5
++#define MAFPA1H6 6
++#define MAFPA1H7 7
++
++#define MAFSA2L _SFR_MEM8(0x116)
++#define MAFSA2L0 0
++#define MAFSA2L1 1
++#define MAFSA2L2 2
++#define MAFSA2L3 3
++#define MAFSA2L4 4
++#define MAFSA2L5 5
++#define MAFSA2L6 6
++#define MAFSA2L7 7
++
++#define MAFSA2H _SFR_MEM8(0x117)
++#define MAFSA2H0 0
++#define MAFSA2H1 1
++#define MAFSA2H2 2
++#define MAFSA2H3 3
++#define MAFSA2H4 4
++#define MAFSA2H5 5
++#define MAFSA2H6 6
++#define MAFSA2H7 7
++
++#define MAFPA2L _SFR_MEM8(0x118)
++#define MAFPA2L0 0
++#define MAFPA2L1 1
++#define MAFPA2L2 2
++#define MAFPA2L3 3
++#define MAFPA2L4 4
++#define MAFPA2L5 5
++#define MAFPA2L6 6
++#define MAFPA2L7 7
++
++#define MAFPA2H _SFR_MEM8(0x119)
++#define MAFPA2H0 0
++#define MAFPA2H1 1
++#define MAFPA2H2 2
++#define MAFPA2H3 3
++#define MAFPA2H4 4
++#define MAFPA2H5 5
++#define MAFPA2H6 6
++#define MAFPA2H7 7
++
++#define MAFSA3L _SFR_MEM8(0x11A)
++#define MAFSA3L0 0
++#define MAFSA3L1 1
++#define MAFSA3L2 2
++#define MAFSA3L3 3
++#define MAFSA3L4 4
++#define MAFSA3L5 5
++#define MAFSA3L6 6
++#define MAFSA3L7 7
++
++#define MAFSA3H _SFR_MEM8(0x11B)
++#define MAFSA3H0 0
++#define MAFSA3H1 1
++#define MAFSA3H2 2
++#define MAFSA3H3 3
++#define MAFSA3H4 4
++#define MAFSA3H5 5
++#define MAFSA3H6 6
++#define MAFSA3H7 7
++
++#define MAFPA3L _SFR_MEM8(0x11C)
++#define MAFPA3L0 0
++#define MAFPA3L1 1
++#define MAFPA3L2 2
++#define MAFPA3L3 3
++#define MAFPA3L4 4
++#define MAFPA3L5 5
++#define MAFPA3L6 6
++#define MAFPA3L7 7
++
++#define MAFPA3H _SFR_MEM8(0x11D)
++#define MAFPA3H0 0
++#define MAFPA3H1 1
++#define MAFPA3H2 2
++#define MAFPA3H3 3
++#define MAFPA3H4 4
++#define MAFPA3H5 5
++#define MAFPA3H6 6
++#define MAFPA3H7 7
++
++/* Reserved [0x11E..0x11F] */
++
++#define TCCR5A _SFR_MEM8(0x120)
++#define WGM50 0
++#define WGM51 1
++#define COM5C0 2
++#define COM5C1 3
++#define COM5B0 4
++#define COM5B1 5
++#define COM5A0 6
++#define COM5A1 7
++
++#define TCCR5B _SFR_MEM8(0x121)
++#define CS50 0
++#define CS51 1
++#define CS52 2
++#define WGM52 3
++#define WGM53 4
++#define ICES5 6
++#define ICNC5 7
++
++#define TCCR5C _SFR_MEM8(0x122)
++#define FOC5C 5
++#define FOC5B 6
++#define FOC5A 7
++
++/* Reserved [0x123] */
++
++/* Combine TCNT5L and TCNT5H */
++#define TCNT5 _SFR_MEM16(0x124)
++
++#define TCNT5L _SFR_MEM8(0x124)
++#define TCNT5H _SFR_MEM8(0x125)
++
++/* Combine ICR5L and ICR5H */
++#define ICR5 _SFR_MEM16(0x126)
++
++#define ICR5L _SFR_MEM8(0x126)
++#define ICR5H _SFR_MEM8(0x127)
++
++/* Combine OCR5AL and OCR5AH */
++#define OCR5A _SFR_MEM16(0x128)
++
++#define OCR5AL _SFR_MEM8(0x128)
++#define OCR5AH _SFR_MEM8(0x129)
++
++/* Combine OCR5BL and OCR5BH */
++#define OCR5B _SFR_MEM16(0x12A)
++
++#define OCR5BL _SFR_MEM8(0x12A)
++#define OCR5BH _SFR_MEM8(0x12B)
++
++/* Combine OCR5CL and OCR5CH */
++#define OCR5C _SFR_MEM16(0x12C)
++
++#define OCR5CL _SFR_MEM8(0x12C)
++#define OCR5CH _SFR_MEM8(0x12D)
++
++/* Reserved [0x12E] */
++
++#define LLCR _SFR_MEM8(0x12F)
++#define LLENCAL 0
++#define LLSHORT 1
++#define LLTCO 2
++#define LLCAL 3
++#define LLCOMP 4
++#define LLDONE 5
++
++#define LLDRL _SFR_MEM8(0x130)
++#define LLDRL0 0
++#define LLDRL1 1
++#define LLDRL2 2
++#define LLDRL3 3
++
++#define LLDRH _SFR_MEM8(0x131)
++#define LLDRH0 0
++#define LLDRH1 1
++#define LLDRH2 2
++#define LLDRH3 3
++#define LLDRH4 4
++
++#define DRTRAM3 _SFR_MEM8(0x132)
++#define ENDRT 4
++#define DRTSWOK 5
++
++#define DRTRAM2 _SFR_MEM8(0x133)
++
++#define DRTRAM1 _SFR_MEM8(0x134)
++
++#define DRTRAM0 _SFR_MEM8(0x135)
++
++#define DPDS0 _SFR_MEM8(0x136)
++#define PBDRV0 0
++#define PBDRV1 1
++#define PDDRV0 2
++#define PDDRV1 3
++#define PEDRV0 4
++#define PEDRV1 5
++#define PFDRV0 6
++#define PFDRV1 7
++
++#define DPDS1 _SFR_MEM8(0x137)
++#define PGDRV0 0
++#define PGDRV1 1
++
++#define PARCR _SFR_MEM8(0x138)
++#define PARUFI 0
++#define PARDFI 1
++#define PALTU0 2
++#define PALTU1 3
++#define PALTU2 4
++#define PALTD0 5
++#define PALTD1 6
++#define PALTD2 7
++
++#define TRXPR _SFR_MEM8(0x139)
++#define TRXRST 0
++#define SLPTR 1
++
++/* Reserved [0x13A..0x13B] */
++
++#define AES_CTRL _SFR_MEM8(0x13C)
++#define AES_IM 2
++#define AES_DIR 3
++#define AES_MODE 5
++#define AES_REQUEST 7
++
++#define AES_STATUS _SFR_MEM8(0x13D)
++#define AES_DONE 0
++#define AES_ER 7
++
++#define AES_STATE _SFR_MEM8(0x13E)
++#define AES_STATE0 0
++#define AES_STATE1 1
++#define AES_STATE2 2
++#define AES_STATE3 3
++#define AES_STATE4 4
++#define AES_STATE5 5
++#define AES_STATE6 6
++#define AES_STATE7 7
++
++#define AES_KEY _SFR_MEM8(0x13F)
++#define AES_KEY0 0
++#define AES_KEY1 1
++#define AES_KEY2 2
++#define AES_KEY3 3
++#define AES_KEY4 4
++#define AES_KEY5 5
++#define AES_KEY6 6
++#define AES_KEY7 7
++
++/* Reserved [0x140] */
++
++#define TRX_STATUS _SFR_MEM8(0x141)
++#define TRX_STATUS0 0
++#define TRX_STATUS1 1
++#define TRX_STATUS2 2
++#define TRX_STATUS3 3
++#define TRX_STATUS4 4
++#define TST_STATUS 5
++#define CCA_STATUS 6
++#define CCA_DONE 7
++
++#define TRX_STATE _SFR_MEM8(0x142)
++#define TRX_CMD0 0
++#define TRX_CMD1 1
++#define TRX_CMD2 2
++#define TRX_CMD3 3
++#define TRX_CMD4 4
++#define TRAC_STATUS0 5
++#define TRAC_STATUS1 6
++#define TRAC_STATUS2 7
++
++#define TRX_CTRL_0 _SFR_MEM8(0x143)
++#define PMU_IF_INV 4
++#define PMU_START 5
++#define PMU_EN 6
++#define Res7 7
++
++#define TRX_CTRL_1 _SFR_MEM8(0x144)
++#define PLL_TX_FLT 4
++#define TX_AUTO_CRC_ON 5
++#define IRQ_2_EXT_EN 6
++#define PA_EXT_EN 7
++
++#define PHY_TX_PWR _SFR_MEM8(0x145)
++#define TX_PWR0 0
++#define TX_PWR1 1
++#define TX_PWR2 2
++#define TX_PWR3 3
++
++#define PHY_RSSI _SFR_MEM8(0x146)
++#define RSSI0 0
++#define RSSI1 1
++#define RSSI2 2
++#define RSSI3 3
++#define RSSI4 4
++#define RND_VALUE0 5
++#define RND_VALUE1 6
++#define RX_CRC_VALID 7
++
++#define PHY_ED_LEVEL _SFR_MEM8(0x147)
++#define ED_LEVEL0 0
++#define ED_LEVEL1 1
++#define ED_LEVEL2 2
++#define ED_LEVEL3 3
++#define ED_LEVEL4 4
++#define ED_LEVEL5 5
++#define ED_LEVEL6 6
++#define ED_LEVEL7 7
++
++#define PHY_CC_CCA _SFR_MEM8(0x148)
++#define CHANNEL0 0
++#define CHANNEL1 1
++#define CHANNEL2 2
++#define CHANNEL3 3
++#define CHANNEL4 4
++#define CCA_MODE0 5
++#define CCA_MODE1 6
++#define CCA_REQUEST 7
++
++#define CCA_THRES _SFR_MEM8(0x149)
++#define CCA_ED_THRES0 0
++#define CCA_ED_THRES1 1
++#define CCA_ED_THRES2 2
++#define CCA_ED_THRES3 3
++#define CCA_CS_THRES0 4
++#define CCA_CS_THRES1 5
++#define CCA_CS_THRES2 6
++#define CCA_CS_THRES3 7
++
++#define RX_CTRL _SFR_MEM8(0x14A)
++#define PDT_THRES0 0
++#define PDT_THRES1 1
++#define PDT_THRES2 2
++#define PDT_THRES3 3
++
++#define SFD_VALUE _SFR_MEM8(0x14B)
++#define SFD_VALUE0 0
++#define SFD_VALUE1 1
++#define SFD_VALUE2 2
++#define SFD_VALUE3 3
++#define SFD_VALUE4 4
++#define SFD_VALUE5 5
++#define SFD_VALUE6 6
++#define SFD_VALUE7 7
++
++#define TRX_CTRL_2 _SFR_MEM8(0x14C)
++#define OQPSK_DATA_RATE0 0
++#define OQPSK_DATA_RATE1 1
++#define RX_SAFE_MODE 7
++
++#define ANT_DIV _SFR_MEM8(0x14D)
++#define ANT_CTRL0 0
++#define ANT_CTRL1 1
++#define ANT_EXT_SW_EN 2
++#define ANT_DIV_EN 3
++#define ANT_SEL 7
++
++#define IRQ_MASK _SFR_MEM8(0x14E)
++#define PLL_LOCK_EN 0
++#define PLL_UNLOCK_EN 1
++#define RX_START_EN 2
++#define RX_END_EN 3
++#define CCA_ED_DONE_EN 4
++#define AMI_EN 5
++#define TX_END_EN 6
++#define AWAKE_EN 7
++
++#define IRQ_STATUS _SFR_MEM8(0x14F)
++#define PLL_LOCK 0
++#define PLL_UNLOCK 1
++#define RX_START 2
++#define RX_END 3
++#define CCA_ED_DONE 4
++#define AMI 5
++#define TX_END 6
++#define AWAKE 7
++
++#define VREG_CTRL _SFR_MEM8(0x150)
++#define DVDD_OK 2
++#define DVREG_EXT 3
++#define AVDD_OK 6
++#define AVREG_EXT 7
++
++#define BATMON _SFR_MEM8(0x151)
++#define BATMON_VTH0 0
++#define BATMON_VTH1 1
++#define BATMON_VTH2 2
++#define BATMON_VTH3 3
++#define BATMON_HR 4
++#define BATMON_OK 5
++#define BAT_LOW_EN 6
++#define BAT_LOW 7
++
++#define XOSC_CTRL _SFR_MEM8(0x152)
++#define XTAL_TRIM0 0
++#define XTAL_TRIM1 1
++#define XTAL_TRIM2 2
++#define XTAL_TRIM3 3
++#define XTAL_MODE0 4
++#define XTAL_MODE1 5
++#define XTAL_MODE2 6
++#define XTAL_MODE3 7
++
++#define CC_CTRL_0 _SFR_MEM8(0x153)
++#define CC_NUMBER0 0
++#define CC_NUMBER1 1
++#define CC_NUMBER2 2
++#define CC_NUMBER3 3
++#define CC_NUMBER4 4
++#define CC_NUMBER5 5
++#define CC_NUMBER6 6
++#define CC_NUMBER7 7
++
++#define CC_CTRL_1 _SFR_MEM8(0x154)
++#define CC_BAND0 0
++#define CC_BAND1 1
++#define CC_BAND2 2
++#define CC_BAND3 3
++
++#define RX_SYN _SFR_MEM8(0x155)
++#define RX_PDT_LEVEL0 0
++#define RX_PDT_LEVEL1 1
++#define RX_PDT_LEVEL2 2
++#define RX_PDT_LEVEL3 3
++#define RX_OVERRIDE 6
++#define RX_PDT_DIS 7
++
++#define TRX_RPC _SFR_MEM8(0x156)
++#define XAH_RPC_EN 0
++#define IPAN_RPC_EN 1
++#define PLL_RPC_EN 3
++#define PDT_RPC_EN 4
++#define RX_RPC_EN 5
++#define RX_RPC_CTRL0 6
++#define RX_RPC_CTRL1 7
++
++#define XAH_CTRL_1 _SFR_MEM8(0x157)
++#define AACK_PROM_MODE 1
++#define AACK_ACK_TIME 2
++#define AACK_UPLD_RES_FT 4
++#define AACK_FLTR_RES_FT 5
++
++#define FTN_CTRL _SFR_MEM8(0x158)
++#define FTN_START 7
++
++/* Reserved [0x159] */
++
++#define PLL_CF _SFR_MEM8(0x15A)
++#define PLL_CF_START 7
++
++#define PLL_DCU _SFR_MEM8(0x15B)
++#define PLL_DCU_START 7
++
++#define PART_NUM _SFR_MEM8(0x15C)
++#define PART_NUM0 0
++#define PART_NUM1 1
++#define PART_NUM2 2
++#define PART_NUM3 3
++#define PART_NUM4 4
++#define PART_NUM5 5
++#define PART_NUM6 6
++#define PART_NUM7 7
++
++#define VERSION_NUM _SFR_MEM8(0x15D)
++#define VERSION_NUM0 0
++#define VERSION_NUM1 1
++#define VERSION_NUM2 2
++#define VERSION_NUM3 3
++#define VERSION_NUM4 4
++#define VERSION_NUM5 5
++#define VERSION_NUM6 6
++#define VERSION_NUM7 7
++
++#define MAN_ID_0 _SFR_MEM8(0x15E)
++#define MAN_ID_00 0
++#define MAN_ID_01 1
++#define MAN_ID_02 2
++#define MAN_ID_03 3
++#define MAN_ID_04 4
++#define MAN_ID_05 5
++#define MAN_ID_06 6
++#define MAN_ID_07 7
++
++#define MAN_ID_1 _SFR_MEM8(0x15F)
++#define MAN_ID_10 0
++#define MAN_ID_11 1
++#define MAN_ID_12 2
++#define MAN_ID_13 3
++#define MAN_ID_14 4
++#define MAN_ID_15 5
++#define MAN_ID_16 6
++#define MAN_ID_17 7
++
++#define SHORT_ADDR_0 _SFR_MEM8(0x160)
++#define SHORT_ADDR_00 0
++#define SHORT_ADDR_01 1
++#define SHORT_ADDR_02 2
++#define SHORT_ADDR_03 3
++#define SHORT_ADDR_04 4
++#define SHORT_ADDR_05 5
++#define SHORT_ADDR_06 6
++#define SHORT_ADDR_07 7
++
++#define SHORT_ADDR_1 _SFR_MEM8(0x161)
++#define SHORT_ADDR_10 0
++#define SHORT_ADDR_11 1
++#define SHORT_ADDR_12 2
++#define SHORT_ADDR_13 3
++#define SHORT_ADDR_14 4
++#define SHORT_ADDR_15 5
++#define SHORT_ADDR_16 6
++#define SHORT_ADDR_17 7
++
++#define PAN_ID_0 _SFR_MEM8(0x162)
++#define PAN_ID_00 0
++#define PAN_ID_01 1
++#define PAN_ID_02 2
++#define PAN_ID_03 3
++#define PAN_ID_04 4
++#define PAN_ID_05 5
++#define PAN_ID_06 6
++#define PAN_ID_07 7
++
++#define PAN_ID_1 _SFR_MEM8(0x163)
++#define PAN_ID_10 0
++#define PAN_ID_11 1
++#define PAN_ID_12 2
++#define PAN_ID_13 3
++#define PAN_ID_14 4
++#define PAN_ID_15 5
++#define PAN_ID_16 6
++#define PAN_ID_17 7
++
++#define IEEE_ADDR_0 _SFR_MEM8(0x164)
++#define IEEE_ADDR_00 0
++#define IEEE_ADDR_01 1
++#define IEEE_ADDR_02 2
++#define IEEE_ADDR_03 3
++#define IEEE_ADDR_04 4
++#define IEEE_ADDR_05 5
++#define IEEE_ADDR_06 6
++#define IEEE_ADDR_07 7
++
++#define IEEE_ADDR_1 _SFR_MEM8(0x165)
++#define IEEE_ADDR_10 0
++#define IEEE_ADDR_11 1
++#define IEEE_ADDR_12 2
++#define IEEE_ADDR_13 3
++#define IEEE_ADDR_14 4
++#define IEEE_ADDR_15 5
++#define IEEE_ADDR_16 6
++#define IEEE_ADDR_17 7
++
++#define IEEE_ADDR_2 _SFR_MEM8(0x166)
++#define IEEE_ADDR_20 0
++#define IEEE_ADDR_21 1
++#define IEEE_ADDR_22 2
++#define IEEE_ADDR_23 3
++#define IEEE_ADDR_24 4
++#define IEEE_ADDR_25 5
++#define IEEE_ADDR_26 6
++#define IEEE_ADDR_27 7
++
++#define IEEE_ADDR_3 _SFR_MEM8(0x167)
++#define IEEE_ADDR_30 0
++#define IEEE_ADDR_31 1
++#define IEEE_ADDR_32 2
++#define IEEE_ADDR_33 3
++#define IEEE_ADDR_34 4
++#define IEEE_ADDR_35 5
++#define IEEE_ADDR_36 6
++#define IEEE_ADDR_37 7
++
++#define IEEE_ADDR_4 _SFR_MEM8(0x168)
++#define IEEE_ADDR_40 0
++#define IEEE_ADDR_41 1
++#define IEEE_ADDR_42 2
++#define IEEE_ADDR_43 3
++#define IEEE_ADDR_44 4
++#define IEEE_ADDR_45 5
++#define IEEE_ADDR_46 6
++#define IEEE_ADDR_47 7
++
++#define IEEE_ADDR_5 _SFR_MEM8(0x169)
++#define IEEE_ADDR_50 0
++#define IEEE_ADDR_51 1
++#define IEEE_ADDR_52 2
++#define IEEE_ADDR_53 3
++#define IEEE_ADDR_54 4
++#define IEEE_ADDR_55 5
++#define IEEE_ADDR_56 6
++#define IEEE_ADDR_57 7
++
++#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
++#define IEEE_ADDR_60 0
++#define IEEE_ADDR_61 1
++#define IEEE_ADDR_62 2
++#define IEEE_ADDR_63 3
++#define IEEE_ADDR_64 4
++#define IEEE_ADDR_65 5
++#define IEEE_ADDR_66 6
++#define IEEE_ADDR_67 7
++
++#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
++#define IEEE_ADDR_70 0
++#define IEEE_ADDR_71 1
++#define IEEE_ADDR_72 2
++#define IEEE_ADDR_73 3
++#define IEEE_ADDR_74 4
++#define IEEE_ADDR_75 5
++#define IEEE_ADDR_76 6
++#define IEEE_ADDR_77 7
++
++#define XAH_CTRL_0 _SFR_MEM8(0x16C)
++#define SLOTTED_OPERATION 0
++#define MAX_CSMA_RETRIES0 1
++#define MAX_CSMA_RETRIES1 2
++#define MAX_CSMA_RETRIES2 3
++#define MAX_FRAME_RETRIES0 4
++#define MAX_FRAME_RETRIES1 5
++#define MAX_FRAME_RETRIES2 6
++#define MAX_FRAME_RETRIES3 7
++
++#define CSMA_SEED_0 _SFR_MEM8(0x16D)
++#define CSMA_SEED_00 0
++#define CSMA_SEED_01 1
++#define CSMA_SEED_02 2
++#define CSMA_SEED_03 3
++#define CSMA_SEED_04 4
++#define CSMA_SEED_05 5
++#define CSMA_SEED_06 6
++#define CSMA_SEED_07 7
++
++#define CSMA_SEED_1 _SFR_MEM8(0x16E)
++#define CSMA_SEED_10 0
++#define CSMA_SEED_11 1
++#define CSMA_SEED_12 2
++#define AACK_I_AM_COORD 3
++#define AACK_DIS_ACK 4
++#define AACK_SET_PD 5
++#define AACK_FVN_MODE0 6
++#define AACK_FVN_MODE1 7
++
++#define CSMA_BE _SFR_MEM8(0x16F)
++#define MIN_BE0 0
++#define MIN_BE1 1
++#define MIN_BE2 2
++#define MIN_BE3 3
++#define MAX_BE0 4
++#define MAX_BE1 5
++#define MAX_BE2 6
++#define MAX_BE3 7
++
++/* Reserved [0x170..0x175] */
++
++#define TST_CTRL_DIGI _SFR_MEM8(0x176)
++#define TST_CTRL_DIG0 0
++#define TST_CTRL_DIG1 1
++#define TST_CTRL_DIG2 2
++#define TST_CTRL_DIG3 3
++
++/* Reserved [0x177..0x17A] */
++
++#define TST_RX_LENGTH _SFR_MEM8(0x17B)
++#define RX_LENGTH0 0
++#define RX_LENGTH1 1
++#define RX_LENGTH2 2
++#define RX_LENGTH3 3
++#define RX_LENGTH4 4
++#define RX_LENGTH5 5
++#define RX_LENGTH6 6
++#define RX_LENGTH7 7
++
++/* Reserved [0x17C..0x17F] */
++
++#define TRXFBST _SFR_MEM8(0x180)
++
++/* Reserved [0x181..0x1FE] */
++
++#define TRXFBEND _SFR_MEM8(0x1FF)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* External Interrupt Request 3 */
++#define INT3_vect _VECTOR(4)
++#define INT3_vect_num 4
++
++/* External Interrupt Request 4 */
++#define INT4_vect _VECTOR(5)
++#define INT4_vect_num 5
++
++/* External Interrupt Request 5 */
++#define INT5_vect _VECTOR(6)
++#define INT5_vect_num 6
++
++/* External Interrupt Request 6 */
++#define INT6_vect _VECTOR(7)
++#define INT6_vect_num 7
++
++/* External Interrupt Request 7 */
++#define INT7_vect _VECTOR(8)
++#define INT7_vect_num 8
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(9)
++#define PCINT0_vect_num 9
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(10)
++#define PCINT1_vect_num 10
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(11)
++#define PCINT2_vect_num 11
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(12)
++#define WDT_vect_num 12
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(13)
++#define TIMER2_COMPA_vect_num 13
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(14)
++#define TIMER2_COMPB_vect_num 14
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(15)
++#define TIMER2_OVF_vect_num 15
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(16)
++#define TIMER1_CAPT_vect_num 16
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(17)
++#define TIMER1_COMPA_vect_num 17
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(18)
++#define TIMER1_COMPB_vect_num 18
++
++/* Timer/Counter1 Compare Match C */
++#define TIMER1_COMPC_vect _VECTOR(19)
++#define TIMER1_COMPC_vect_num 19
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(20)
++#define TIMER1_OVF_vect_num 20
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(21)
++#define TIMER0_COMPA_vect_num 21
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(22)
++#define TIMER0_COMPB_vect_num 22
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(23)
++#define TIMER0_OVF_vect_num 23
++
++/* SPI Serial Transfer Complete */
++#define SPI_STC_vect _VECTOR(24)
++#define SPI_STC_vect_num 24
++
++/* USART0, Rx Complete */
++#define USART0_RX_vect _VECTOR(25)
++#define USART0_RX_vect_num 25
++
++/* USART0 Data register Empty */
++#define USART0_UDRE_vect _VECTOR(26)
++#define USART0_UDRE_vect_num 26
++
++/* USART0, Tx Complete */
++#define USART0_TX_vect _VECTOR(27)
++#define USART0_TX_vect_num 27
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(28)
++#define ANALOG_COMP_vect_num 28
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(29)
++#define ADC_vect_num 29
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(30)
++#define EE_READY_vect_num 30
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(31)
++#define TIMER3_CAPT_vect_num 31
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(32)
++#define TIMER3_COMPA_vect_num 32
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(33)
++#define TIMER3_COMPB_vect_num 33
++
++/* Timer/Counter3 Compare Match C */
++#define TIMER3_COMPC_vect _VECTOR(34)
++#define TIMER3_COMPC_vect_num 34
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(35)
++#define TIMER3_OVF_vect_num 35
++
++/* USART1, Rx Complete */
++#define USART1_RX_vect _VECTOR(36)
++#define USART1_RX_vect_num 36
++
++/* USART1 Data register Empty */
++#define USART1_UDRE_vect _VECTOR(37)
++#define USART1_UDRE_vect_num 37
++
++/* USART1, Tx Complete */
++#define USART1_TX_vect _VECTOR(38)
++#define USART1_TX_vect_num 38
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(39)
++#define TWI_vect_num 39
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(40)
++#define SPM_READY_vect_num 40
++
++/* Timer/Counter4 Capture Event */
++#define TIMER4_CAPT_vect _VECTOR(41)
++#define TIMER4_CAPT_vect_num 41
++
++/* Timer/Counter4 Compare Match A */
++#define TIMER4_COMPA_vect _VECTOR(42)
++#define TIMER4_COMPA_vect_num 42
++
++/* Timer/Counter4 Compare Match B */
++#define TIMER4_COMPB_vect _VECTOR(43)
++#define TIMER4_COMPB_vect_num 43
++
++/* Timer/Counter4 Compare Match C */
++#define TIMER4_COMPC_vect _VECTOR(44)
++#define TIMER4_COMPC_vect_num 44
++
++/* Timer/Counter4 Overflow */
++#define TIMER4_OVF_vect _VECTOR(45)
++#define TIMER4_OVF_vect_num 45
++
++/* Timer/Counter5 Capture Event */
++#define TIMER5_CAPT_vect _VECTOR(46)
++#define TIMER5_CAPT_vect_num 46
++
++/* Timer/Counter5 Compare Match A */
++#define TIMER5_COMPA_vect _VECTOR(47)
++#define TIMER5_COMPA_vect_num 47
++
++/* Timer/Counter5 Compare Match B */
++#define TIMER5_COMPB_vect _VECTOR(48)
++#define TIMER5_COMPB_vect_num 48
++
++/* Timer/Counter5 Compare Match C */
++#define TIMER5_COMPC_vect _VECTOR(49)
++#define TIMER5_COMPC_vect_num 49
++
++/* Timer/Counter5 Overflow */
++#define TIMER5_OVF_vect _VECTOR(50)
++#define TIMER5_OVF_vect_num 50
++
++/* USART2, Rx Complete */
++#define USART2_RX_vect _VECTOR(51)
++#define USART2_RX_vect_num 51
++
++/* USART2 Data register Empty */
++#define USART2_UDRE_vect _VECTOR(52)
++#define USART2_UDRE_vect_num 52
++
++/* USART2, Tx Complete */
++#define USART2_TX_vect _VECTOR(53)
++#define USART2_TX_vect_num 53
++
++/* USART3, Rx Complete */
++#define USART3_RX_vect _VECTOR(54)
++#define USART3_RX_vect_num 54
++
++/* USART3 Data register Empty */
++#define USART3_UDRE_vect _VECTOR(55)
++#define USART3_UDRE_vect_num 55
++
++/* USART3, Tx Complete */
++#define USART3_TX_vect _VECTOR(56)
++#define USART3_TX_vect_num 56
++
++/* TRX24 - PLL lock interrupt */
++#define TRX24_PLL_LOCK_vect _VECTOR(57)
++#define TRX24_PLL_LOCK_vect_num 57
++
++/* TRX24 - PLL unlock interrupt */
++#define TRX24_PLL_UNLOCK_vect _VECTOR(58)
++#define TRX24_PLL_UNLOCK_vect_num 58
++
++/* TRX24 - Receive start interrupt */
++#define TRX24_RX_START_vect _VECTOR(59)
++#define TRX24_RX_START_vect_num 59
++
++/* TRX24 - RX_END interrupt */
++#define TRX24_RX_END_vect _VECTOR(60)
++#define TRX24_RX_END_vect_num 60
++
++/* TRX24 - CCA/ED done interrupt */
++#define TRX24_CCA_ED_DONE_vect _VECTOR(61)
++#define TRX24_CCA_ED_DONE_vect_num 61
++
++/* TRX24 - XAH - AMI */
++#define TRX24_XAH_AMI_vect _VECTOR(62)
++#define TRX24_XAH_AMI_vect_num 62
++
++/* TRX24 - TX_END interrupt */
++#define TRX24_TX_END_vect _VECTOR(63)
++#define TRX24_TX_END_vect_num 63
++
++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
++#define TRX24_AWAKE_vect _VECTOR(64)
++#define TRX24_AWAKE_vect_num 64
++
++/* Symbol counter - compare match 1 interrupt */
++#define SCNT_CMP1_vect _VECTOR(65)
++#define SCNT_CMP1_vect_num 65
++
++/* Symbol counter - compare match 2 interrupt */
++#define SCNT_CMP2_vect _VECTOR(66)
++#define SCNT_CMP2_vect_num 66
++
++/* Symbol counter - compare match 3 interrupt */
++#define SCNT_CMP3_vect _VECTOR(67)
++#define SCNT_CMP3_vect_num 67
++
++/* Symbol counter - overflow interrupt */
++#define SCNT_OVFL_vect _VECTOR(68)
++#define SCNT_OVFL_vect_num 68
++
++/* Symbol counter - backoff interrupt */
++#define SCNT_BACKOFF_vect _VECTOR(69)
++#define SCNT_BACKOFF_vect_num 69
++
++/* AES engine ready interrupt */
++#define AES_READY_vect _VECTOR(70)
++#define AES_READY_vect_num 70
++
++/* Battery monitor indicates supply voltage below threshold */
++#define BAT_LOW_vect _VECTOR(71)
++#define BAT_LOW_vect_num 71
++
++/* TRX24 TX start interrupt */
++#define TRX24_TX_START_vect _VECTOR(72)
++#define TRX24_TX_START_vect_num 72
++
++/* Address match interrupt of address filter 0 */
++#define TRX24_AMI0_vect _VECTOR(73)
++#define TRX24_AMI0_vect_num 73
++
++/* Address match interrupt of address filter 1 */
++#define TRX24_AMI1_vect _VECTOR(74)
++#define TRX24_AMI1_vect_num 74
++
++/* Address match interrupt of address filter 2 */
++#define TRX24_AMI2_vect _VECTOR(75)
++#define TRX24_AMI2_vect_num 75
++
++/* Address match interrupt of address filter 3 */
++#define TRX24_AMI3_vect _VECTOR(76)
++#define TRX24_AMI3_vect_num 76
++
++#define _VECTORS_SIZE 308
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHSTART 0x0000
++#define FLASHEND 0x1FFFF
++#define RAMSTART 0x0200
++#define RAMSIZE 16384
++#define RAMEND 0x41FF
++#define E2START 0
++#define E2SIZE 4096
++#define E2PAGESIZE 8
++#define E2END 0x0FFF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0)
++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1)
++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2)
++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3)
++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4)
++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0xA7
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA128RFR2_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom256rfr2.h avr-libc-1.8.0/include/avr/iom256rfr2.h
+--- avr-libc-1.8.0.orig/include/avr/iom256rfr2.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom256rfr2.h 2013-01-18 10:08:38.000000000 +0100
+@@ -0,0 +1,2572 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA256RFR2_H_INCLUDED
++#define _AVR_ATMEGA256RFR2_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom256rfr2.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++#define Res0 3
++#define Res1 4
++#define Res2 5
++#define Res3 6
++#define Res4 7
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define OCF1C 3
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++#define TIFR3 _SFR_IO8(0x18)
++#define TOV3 0
++#define OCF3A 1
++#define OCF3B 2
++#define OCF3C 3
++#define ICF3 5
++
++#define TIFR4 _SFR_IO8(0x19)
++#define TOV4 0
++#define OCF4A 1
++#define OCF4B 2
++#define OCF4C 3
++#define ICF4 5
++
++#define TIFR5 _SFR_IO8(0x1A)
++#define TOV5 0
++#define OCF5A 1
++#define OCF5B 2
++#define OCF5C 3
++#define ICF5 5
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++#define INTF3 3
++#define INTF4 4
++#define INTF5 5
++#define INTF6 6
++#define INTF7 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++#define INT3 3
++#define INT4 4
++#define INT5 5
++#define INT6 6
++#define INT7 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define PSRASY 1
++#define TSM 7
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR0 0
++#define OCDR1 1
++#define OCDR2 2
++#define OCDR3 3
++#define OCDR4 4
++#define OCDR5 5
++#define OCDR6 6
++#define OCDR7 7
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3A] */
++
++#define RAMPZ _SFR_IO8(0x3B)
++#define RAMPZ0 0
++#define RAMPZ1 1
++#define Res5 7
++
++#define EIND _SFR_IO8(0x3C)
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62] */
++
++#define PRR2 _SFR_MEM8(0x63)
++#define PRRAM0 0
++#define PRRAM1 1
++#define PRRAM2 2
++#define PRRAM3 3
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRPGA 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++#define PRR1 _SFR_MEM8(0x65)
++#define PRUSART1 0
++#define PRTIM3 3
++#define PRTIM4 4
++#define PRTIM5 5
++#define PRTRX24 6
++#define Res 7
++
++#define OSCCAL _SFR_MEM8(0x66)
++#define CAL0 0
++#define CAL1 1
++#define CAL2 2
++#define CAL3 3
++#define CAL4 4
++#define CAL5 5
++#define CAL6 6
++#define CAL7 7
++
++#define BGCR _SFR_MEM8(0x67)
++#define BGCAL0 0
++#define BGCAL1 1
++#define BGCAL2 2
++#define BGCAL_FINE0 3
++#define BGCAL_FINE1 4
++#define BGCAL_FINE2 5
++#define BGCAL_FINE3 6
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++#define ISC30 6
++#define ISC31 7
++
++#define EICRB _SFR_MEM8(0x6A)
++#define ISC40 0
++#define ISC41 1
++#define ISC50 2
++#define ISC51 3
++#define ISC60 4
++#define ISC61 5
++#define ISC70 6
++#define ISC71 7
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define OCIE1C 3
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++#define TIMSK3 _SFR_MEM8(0x71)
++#define TOIE3 0
++#define OCIE3A 1
++#define OCIE3B 2
++#define OCIE3C 3
++#define ICIE3 5
++
++#define TIMSK4 _SFR_MEM8(0x72)
++#define TOIE4 0
++#define OCIE4A 1
++#define OCIE4B 2
++#define OCIE4C 3
++#define ICIE4 5
++
++#define TIMSK5 _SFR_MEM8(0x73)
++#define TOIE5 0
++#define OCIE5A 1
++#define OCIE5B 2
++#define OCIE5C 3
++#define ICIE5 5
++
++/* Reserved [0x74] */
++
++#define NEMCR _SFR_MEM8(0x75)
++#define AEAM0 4
++#define AEAM1 5
++#define ENEAM 6
++
++/* Reserved [0x76] */
++
++#define ADCSRC _SFR_MEM8(0x77)
++#define ADSUT0 0
++#define ADSUT1 1
++#define ADSUT2 2
++#define ADSUT3 3
++#define ADSUT4 4
++#define ADTHT0 6
++#define ADTHT1 7
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define MUX5 3
++#define ACCH 4
++#define REFOK 5
++#define AVDDOK 7
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define DIDR2 _SFR_MEM8(0x7D)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++#define ADC11D 3
++#define ADC12D 4
++#define ADC13D 5
++#define ADC14D 6
++#define ADC15D 7
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1C0 2
++#define COM1C1 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1C 5
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Combine OCR1CL and OCR1CH */
++#define OCR1C _SFR_MEM16(0x8C)
++
++#define OCR1CL _SFR_MEM8(0x8C)
++#define OCR1CH _SFR_MEM8(0x8D)
++
++/* Reserved [0x8E..0x8F] */
++
++#define TCCR3A _SFR_MEM8(0x90)
++#define WGM30 0
++#define WGM31 1
++#define COM3C0 2
++#define COM3C1 3
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3B _SFR_MEM8(0x91)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3C _SFR_MEM8(0x92)
++#define FOC3C 5
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x93] */
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x94)
++
++#define TCNT3L _SFR_MEM8(0x94)
++#define TCNT3H _SFR_MEM8(0x95)
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x96)
++
++#define ICR3L _SFR_MEM8(0x96)
++#define ICR3H _SFR_MEM8(0x97)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x98)
++
++#define OCR3AL _SFR_MEM8(0x98)
++#define OCR3AH _SFR_MEM8(0x99)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x9A)
++
++#define OCR3BL _SFR_MEM8(0x9A)
++#define OCR3BH _SFR_MEM8(0x9B)
++
++/* Combine OCR3CL and OCR3CH */
++#define OCR3C _SFR_MEM16(0x9C)
++
++#define OCR3CL _SFR_MEM8(0x9C)
++#define OCR3CH _SFR_MEM8(0x9D)
++
++/* Reserved [0x9E..0x9F] */
++
++#define TCCR4A _SFR_MEM8(0xA0)
++#define WGM40 0
++#define WGM41 1
++#define COM4C0 2
++#define COM4C1 3
++#define COM4B0 4
++#define COM4B1 5
++#define COM4A0 6
++#define COM4A1 7
++
++#define TCCR4B _SFR_MEM8(0xA1)
++#define CS40 0
++#define CS41 1
++#define CS42 2
++#define WGM42 3
++#define WGM43 4
++#define ICES4 6
++#define ICNC4 7
++
++#define TCCR4C _SFR_MEM8(0xA2)
++#define FOC4C 5
++#define FOC4B 6
++#define FOC4A 7
++
++/* Reserved [0xA3] */
++
++/* Combine TCNT4L and TCNT4H */
++#define TCNT4 _SFR_MEM16(0xA4)
++
++#define TCNT4L _SFR_MEM8(0xA4)
++#define TCNT4H _SFR_MEM8(0xA5)
++
++/* Combine ICR4L and ICR4H */
++#define ICR4 _SFR_MEM16(0xA6)
++
++#define ICR4L _SFR_MEM8(0xA6)
++#define ICR4H _SFR_MEM8(0xA7)
++
++/* Combine OCR4AL and OCR4AH */
++#define OCR4A _SFR_MEM16(0xA8)
++
++#define OCR4AL _SFR_MEM8(0xA8)
++#define OCR4AH _SFR_MEM8(0xA9)
++
++/* Combine OCR4BL and OCR4BH */
++#define OCR4B _SFR_MEM16(0xAA)
++
++#define OCR4BL _SFR_MEM8(0xAA)
++#define OCR4BH _SFR_MEM8(0xAB)
++
++/* Combine OCR4CL and OCR4CH */
++#define OCR4C _SFR_MEM16(0xAC)
++
++#define OCR4CL _SFR_MEM8(0xAC)
++#define OCR4CH _SFR_MEM8(0xAD)
++
++/* Reserved [0xAE..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++#define EXCLKAMR 7
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++#define IRQ_MASK1 _SFR_MEM8(0xBE)
++#define TX_START_EN 0
++#define MAF_0_AMI_EN 1
++#define MAF_1_AMI_EN 2
++#define MAF_2_AMI_EN 3
++#define MAF_3_AMI_EN 4
++
++#define IRQ_STATUS1 _SFR_MEM8(0xBF)
++#define TX_START 0
++#define MAF_0_AMI 1
++#define MAF_1_AMI 2
++#define MAF_2_AMI 3
++#define MAF_3_AMI 4
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++#define UCPHA0 1
++#define UDORD0 2
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++#define UCPHA1 1
++#define UDORD1 2
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++/* Reserved [0xCF..0xD6] */
++
++#define SCRSTRLL _SFR_MEM8(0xD7)
++#define SCRSTRLL0 0
++#define SCRSTRLL1 1
++#define SCRSTRLL2 2
++#define SCRSTRLL3 3
++#define SCRSTRLL4 4
++#define SCRSTRLL5 5
++#define SCRSTRLL6 6
++#define SCRSTRLL7 7
++
++#define SCRSTRLH _SFR_MEM8(0xD8)
++#define SCRSTRLH0 0
++#define SCRSTRLH1 1
++#define SCRSTRLH2 2
++#define SCRSTRLH3 3
++#define SCRSTRLH4 4
++#define SCRSTRLH5 5
++#define SCRSTRLH6 6
++#define SCRSTRLH7 7
++
++#define SCRSTRHL _SFR_MEM8(0xD9)
++#define SCRSTRHL0 0
++#define SCRSTRHL1 1
++#define SCRSTRHL2 2
++#define SCRSTRHL3 3
++#define SCRSTRHL4 4
++#define SCRSTRHL5 5
++#define SCRSTRHL6 6
++#define SCRSTRHL7 7
++
++#define SCRSTRHH _SFR_MEM8(0xDA)
++#define SCRSTRHH0 0
++#define SCRSTRHH1 1
++#define SCRSTRHH2 2
++#define SCRSTRHH3 3
++#define SCRSTRHH4 4
++#define SCRSTRHH5 5
++#define SCRSTRHH6 6
++#define SCRSTRHH7 7
++
++#define SCCSR _SFR_MEM8(0xDB)
++#define SCCS10 0
++#define SCCS11 1
++#define SCCS20 2
++#define SCCS21 3
++#define SCCS30 4
++#define SCCS31 5
++
++#define SCCR0 _SFR_MEM8(0xDC)
++#define SCCMP1 0
++#define SCCMP2 1
++#define SCCMP3 2
++#define SCTSE 3
++#define SCCKSEL 4
++#define SCEN 5
++#define SCMBTS 6
++#define SCRES 7
++
++#define SCCR1 _SFR_MEM8(0xDD)
++#define SCENBO 0
++#define SCEECLK 1
++#define SCCKDIV0 2
++#define SCCKDIV1 3
++#define SCCKDIV2 4
++#define SCBTSM 5
++#define Res6 7
++
++#define SCSR _SFR_MEM8(0xDE)
++#define SCBSY 0
++
++#define SCIRQM _SFR_MEM8(0xDF)
++#define IRQMCP1 0
++#define IRQMCP2 1
++#define IRQMCP3 2
++#define IRQMOF 3
++#define IRQMBO 4
++
++#define SCIRQS _SFR_MEM8(0xE0)
++#define IRQSCP1 0
++#define IRQSCP2 1
++#define IRQSCP3 2
++#define IRQSOF 3
++#define IRQSBO 4
++
++#define SCCNTLL _SFR_MEM8(0xE1)
++#define SCCNTLL0 0
++#define SCCNTLL1 1
++#define SCCNTLL2 2
++#define SCCNTLL3 3
++#define SCCNTLL4 4
++#define SCCNTLL5 5
++#define SCCNTLL6 6
++#define SCCNTLL7 7
++
++#define SCCNTLH _SFR_MEM8(0xE2)
++#define SCCNTLH0 0
++#define SCCNTLH1 1
++#define SCCNTLH2 2
++#define SCCNTLH3 3
++#define SCCNTLH4 4
++#define SCCNTLH5 5
++#define SCCNTLH6 6
++#define SCCNTLH7 7
++
++#define SCCNTHL _SFR_MEM8(0xE3)
++#define SCCNTHL0 0
++#define SCCNTHL1 1
++#define SCCNTHL2 2
++#define SCCNTHL3 3
++#define SCCNTHL4 4
++#define SCCNTHL5 5
++#define SCCNTHL6 6
++#define SCCNTHL7 7
++
++#define SCCNTHH _SFR_MEM8(0xE4)
++#define SCCNTHH0 0
++#define SCCNTHH1 1
++#define SCCNTHH2 2
++#define SCCNTHH3 3
++#define SCCNTHH4 4
++#define SCCNTHH5 5
++#define SCCNTHH6 6
++#define SCCNTHH7 7
++
++#define SCBTSRLL _SFR_MEM8(0xE5)
++#define SCBTSRLL0 0
++#define SCBTSRLL1 1
++#define SCBTSRLL2 2
++#define SCBTSRLL3 3
++#define SCBTSRLL4 4
++#define SCBTSRLL5 5
++#define SCBTSRLL6 6
++#define SCBTSRLL7 7
++
++#define SCBTSRLH _SFR_MEM8(0xE6)
++#define SCBTSRLH0 0
++#define SCBTSRLH1 1
++#define SCBTSRLH2 2
++#define SCBTSRLH3 3
++#define SCBTSRLH4 4
++#define SCBTSRLH5 5
++#define SCBTSRLH6 6
++#define SCBTSRLH7 7
++
++#define SCBTSRHL _SFR_MEM8(0xE7)
++#define SCBTSRHL0 0
++#define SCBTSRHL1 1
++#define SCBTSRHL2 2
++#define SCBTSRHL3 3
++#define SCBTSRHL4 4
++#define SCBTSRHL5 5
++#define SCBTSRHL6 6
++#define SCBTSRHL7 7
++
++#define SCBTSRHH _SFR_MEM8(0xE8)
++#define SCBTSRHH0 0
++#define SCBTSRHH1 1
++#define SCBTSRHH2 2
++#define SCBTSRHH3 3
++#define SCBTSRHH4 4
++#define SCBTSRHH5 5
++#define SCBTSRHH6 6
++#define SCBTSRHH7 7
++
++#define SCTSRLL _SFR_MEM8(0xE9)
++#define SCTSRLL0 0
++#define SCTSRLL1 1
++#define SCTSRLL2 2
++#define SCTSRLL3 3
++#define SCTSRLL4 4
++#define SCTSRLL5 5
++#define SCTSRLL6 6
++#define SCTSRLL7 7
++
++#define SCTSRLH _SFR_MEM8(0xEA)
++#define SCTSRLH0 0
++#define SCTSRLH1 1
++#define SCTSRLH2 2
++#define SCTSRLH3 3
++#define SCTSRLH4 4
++#define SCTSRLH5 5
++#define SCTSRLH6 6
++#define SCTSRLH7 7
++
++#define SCTSRHL _SFR_MEM8(0xEB)
++#define SCTSRHL0 0
++#define SCTSRHL1 1
++#define SCTSRHL2 2
++#define SCTSRHL3 3
++#define SCTSRHL4 4
++#define SCTSRHL5 5
++#define SCTSRHL6 6
++#define SCTSRHL7 7
++
++#define SCTSRHH _SFR_MEM8(0xEC)
++#define SCTSRHH0 0
++#define SCTSRHH1 1
++#define SCTSRHH2 2
++#define SCTSRHH3 3
++#define SCTSRHH4 4
++#define SCTSRHH5 5
++#define SCTSRHH6 6
++#define SCTSRHH7 7
++
++#define SCOCR3LL _SFR_MEM8(0xED)
++#define SCOCR3LL0 0
++#define SCOCR3LL1 1
++#define SCOCR3LL2 2
++#define SCOCR3LL3 3
++#define SCOCR3LL4 4
++#define SCOCR3LL5 5
++#define SCOCR3LL6 6
++#define SCOCR3LL7 7
++
++#define SCOCR3LH _SFR_MEM8(0xEE)
++#define SCOCR3LH0 0
++#define SCOCR3LH1 1
++#define SCOCR3LH2 2
++#define SCOCR3LH3 3
++#define SCOCR3LH4 4
++#define SCOCR3LH5 5
++#define SCOCR3LH6 6
++#define SCOCR3LH7 7
++
++#define SCOCR3HL _SFR_MEM8(0xEF)
++#define SCOCR3HL0 0
++#define SCOCR3HL1 1
++#define SCOCR3HL2 2
++#define SCOCR3HL3 3
++#define SCOCR3HL4 4
++#define SCOCR3HL5 5
++#define SCOCR3HL6 6
++#define SCOCR3HL7 7
++
++#define SCOCR3HH _SFR_MEM8(0xF0)
++#define SCOCR3HH0 0
++#define SCOCR3HH1 1
++#define SCOCR3HH2 2
++#define SCOCR3HH3 3
++#define SCOCR3HH4 4
++#define SCOCR3HH5 5
++#define SCOCR3HH6 6
++#define SCOCR3HH7 7
++
++#define SCOCR2LL _SFR_MEM8(0xF1)
++#define SCOCR2LL0 0
++#define SCOCR2LL1 1
++#define SCOCR2LL2 2
++#define SCOCR2LL3 3
++#define SCOCR2LL4 4
++#define SCOCR2LL5 5
++#define SCOCR2LL6 6
++#define SCOCR2LL7 7
++
++#define SCOCR2LH _SFR_MEM8(0xF2)
++#define SCOCR2LH0 0
++#define SCOCR2LH1 1
++#define SCOCR2LH2 2
++#define SCOCR2LH3 3
++#define SCOCR2LH4 4
++#define SCOCR2LH5 5
++#define SCOCR2LH6 6
++#define SCOCR2LH7 7
++
++#define SCOCR2HL _SFR_MEM8(0xF3)
++#define SCOCR2HL0 0
++#define SCOCR2HL1 1
++#define SCOCR2HL2 2
++#define SCOCR2HL3 3
++#define SCOCR2HL4 4
++#define SCOCR2HL5 5
++#define SCOCR2HL6 6
++#define SCOCR2HL7 7
++
++#define SCOCR2HH _SFR_MEM8(0xF4)
++#define SCOCR2HH0 0
++#define SCOCR2HH1 1
++#define SCOCR2HH2 2
++#define SCOCR2HH3 3
++#define SCOCR2HH4 4
++#define SCOCR2HH5 5
++#define SCOCR2HH6 6
++#define SCOCR2HH7 7
++
++#define SCOCR1LL _SFR_MEM8(0xF5)
++#define SCOCR1LL0 0
++#define SCOCR1LL1 1
++#define SCOCR1LL2 2
++#define SCOCR1LL3 3
++#define SCOCR1LL4 4
++#define SCOCR1LL5 5
++#define SCOCR1LL6 6
++#define SCOCR1LL7 7
++
++#define SCOCR1LH _SFR_MEM8(0xF6)
++#define SCOCR1LH0 0
++#define SCOCR1LH1 1
++#define SCOCR1LH2 2
++#define SCOCR1LH3 3
++#define SCOCR1LH4 4
++#define SCOCR1LH5 5
++#define SCOCR1LH6 6
++#define SCOCR1LH7 7
++
++#define SCOCR1HL _SFR_MEM8(0xF7)
++#define SCOCR1HL0 0
++#define SCOCR1HL1 1
++#define SCOCR1HL2 2
++#define SCOCR1HL3 3
++#define SCOCR1HL4 4
++#define SCOCR1HL5 5
++#define SCOCR1HL6 6
++#define SCOCR1HL7 7
++
++#define SCOCR1HH _SFR_MEM8(0xF8)
++#define SCOCR1HH0 0
++#define SCOCR1HH1 1
++#define SCOCR1HH2 2
++#define SCOCR1HH3 3
++#define SCOCR1HH4 4
++#define SCOCR1HH5 5
++#define SCOCR1HH6 6
++#define SCOCR1HH7 7
++
++#define SCTSTRLL _SFR_MEM8(0xF9)
++#define SCTSTRLL0 0
++#define SCTSTRLL1 1
++#define SCTSTRLL2 2
++#define SCTSTRLL3 3
++#define SCTSTRLL4 4
++#define SCTSTRLL5 5
++#define SCTSTRLL6 6
++#define SCTSTRLL7 7
++
++#define SCTSTRLH _SFR_MEM8(0xFA)
++#define SCTSTRLH0 0
++#define SCTSTRLH1 1
++#define SCTSTRLH2 2
++#define SCTSTRLH3 3
++#define SCTSTRLH4 4
++#define SCTSTRLH5 5
++#define SCTSTRLH6 6
++#define SCTSTRLH7 7
++
++#define SCTSTRHL _SFR_MEM8(0xFB)
++#define SCTSTRHL0 0
++#define SCTSTRHL1 1
++#define SCTSTRHL2 2
++#define SCTSTRHL3 3
++#define SCTSTRHL4 4
++#define SCTSTRHL5 5
++#define SCTSTRHL6 6
++#define SCTSTRHL7 7
++
++#define SCTSTRHH _SFR_MEM8(0xFC)
++#define SCTSTRHH0 0
++#define SCTSTRHH1 1
++#define SCTSTRHH2 2
++#define SCTSTRHH3 3
++#define SCTSTRHH4 4
++#define SCTSTRHH5 5
++#define SCTSTRHH6 6
++#define SCTSTRHH7 7
++
++/* Reserved [0xFD..0x10B] */
++
++#define MAFCR0 _SFR_MEM8(0x10C)
++#define MAF0EN 0
++#define MAF1EN 1
++#define MAF2EN 2
++#define MAF3EN 3
++
++#define MAFCR1 _SFR_MEM8(0x10D)
++#define AACK_0_I_AM_COORD 0
++#define AACK_0_SET_PD 1
++#define AACK_1_I_AM_COORD 2
++#define AACK_1_SET_PD 3
++#define AACK_2_I_AM_COORD 4
++#define AACK_2_SET_PD 5
++#define AACK_3_I_AM_COORD 6
++#define AACK_3_SET_PD 7
++
++#define MAFSA0L _SFR_MEM8(0x10E)
++#define MAFSA0L0 0
++#define MAFSA0L1 1
++#define MAFSA0L2 2
++#define MAFSA0L3 3
++#define MAFSA0L4 4
++#define MAFSA0L5 5
++#define MAFSA0L6 6
++#define MAFSA0L7 7
++
++#define MAFSA0H _SFR_MEM8(0x10F)
++#define MAFSA0H0 0
++#define MAFSA0H1 1
++#define MAFSA0H2 2
++#define MAFSA0H3 3
++#define MAFSA0H4 4
++#define MAFSA0H5 5
++#define MAFSA0H6 6
++#define MAFSA0H7 7
++
++#define MAFPA0L _SFR_MEM8(0x110)
++#define MAFPA0L0 0
++#define MAFPA0L1 1
++#define MAFPA0L2 2
++#define MAFPA0L3 3
++#define MAFPA0L4 4
++#define MAFPA0L5 5
++#define MAFPA0L6 6
++#define MAFPA0L7 7
++
++#define MAFPA0H _SFR_MEM8(0x111)
++#define MAFPA0H0 0
++#define MAFPA0H1 1
++#define MAFPA0H2 2
++#define MAFPA0H3 3
++#define MAFPA0H4 4
++#define MAFPA0H5 5
++#define MAFPA0H6 6
++#define MAFPA0H7 7
++
++#define MAFSA1L _SFR_MEM8(0x112)
++#define MAFSA1L0 0
++#define MAFSA1L1 1
++#define MAFSA1L2 2
++#define MAFSA1L3 3
++#define MAFSA1L4 4
++#define MAFSA1L5 5
++#define MAFSA1L6 6
++#define MAFSA1L7 7
++
++#define MAFSA1H _SFR_MEM8(0x113)
++#define MAFSA1H0 0
++#define MAFSA1H1 1
++#define MAFSA1H2 2
++#define MAFSA1H3 3
++#define MAFSA1H4 4
++#define MAFSA1H5 5
++#define MAFSA1H6 6
++#define MAFSA1H7 7
++
++#define MAFPA1L _SFR_MEM8(0x114)
++#define MAFPA1L0 0
++#define MAFPA1L1 1
++#define MAFPA1L2 2
++#define MAFPA1L3 3
++#define MAFPA1L4 4
++#define MAFPA1L5 5
++#define MAFPA1L6 6
++#define MAFPA1L7 7
++
++#define MAFPA1H _SFR_MEM8(0x115)
++#define MAFPA1H0 0
++#define MAFPA1H1 1
++#define MAFPA1H2 2
++#define MAFPA1H3 3
++#define MAFPA1H4 4
++#define MAFPA1H5 5
++#define MAFPA1H6 6
++#define MAFPA1H7 7
++
++#define MAFSA2L _SFR_MEM8(0x116)
++#define MAFSA2L0 0
++#define MAFSA2L1 1
++#define MAFSA2L2 2
++#define MAFSA2L3 3
++#define MAFSA2L4 4
++#define MAFSA2L5 5
++#define MAFSA2L6 6
++#define MAFSA2L7 7
++
++#define MAFSA2H _SFR_MEM8(0x117)
++#define MAFSA2H0 0
++#define MAFSA2H1 1
++#define MAFSA2H2 2
++#define MAFSA2H3 3
++#define MAFSA2H4 4
++#define MAFSA2H5 5
++#define MAFSA2H6 6
++#define MAFSA2H7 7
++
++#define MAFPA2L _SFR_MEM8(0x118)
++#define MAFPA2L0 0
++#define MAFPA2L1 1
++#define MAFPA2L2 2
++#define MAFPA2L3 3
++#define MAFPA2L4 4
++#define MAFPA2L5 5
++#define MAFPA2L6 6
++#define MAFPA2L7 7
++
++#define MAFPA2H _SFR_MEM8(0x119)
++#define MAFPA2H0 0
++#define MAFPA2H1 1
++#define MAFPA2H2 2
++#define MAFPA2H3 3
++#define MAFPA2H4 4
++#define MAFPA2H5 5
++#define MAFPA2H6 6
++#define MAFPA2H7 7
++
++#define MAFSA3L _SFR_MEM8(0x11A)
++#define MAFSA3L0 0
++#define MAFSA3L1 1
++#define MAFSA3L2 2
++#define MAFSA3L3 3
++#define MAFSA3L4 4
++#define MAFSA3L5 5
++#define MAFSA3L6 6
++#define MAFSA3L7 7
++
++#define MAFSA3H _SFR_MEM8(0x11B)
++#define MAFSA3H0 0
++#define MAFSA3H1 1
++#define MAFSA3H2 2
++#define MAFSA3H3 3
++#define MAFSA3H4 4
++#define MAFSA3H5 5
++#define MAFSA3H6 6
++#define MAFSA3H7 7
++
++#define MAFPA3L _SFR_MEM8(0x11C)
++#define MAFPA3L0 0
++#define MAFPA3L1 1
++#define MAFPA3L2 2
++#define MAFPA3L3 3
++#define MAFPA3L4 4
++#define MAFPA3L5 5
++#define MAFPA3L6 6
++#define MAFPA3L7 7
++
++#define MAFPA3H _SFR_MEM8(0x11D)
++#define MAFPA3H0 0
++#define MAFPA3H1 1
++#define MAFPA3H2 2
++#define MAFPA3H3 3
++#define MAFPA3H4 4
++#define MAFPA3H5 5
++#define MAFPA3H6 6
++#define MAFPA3H7 7
++
++/* Reserved [0x11E..0x11F] */
++
++#define TCCR5A _SFR_MEM8(0x120)
++#define WGM50 0
++#define WGM51 1
++#define COM5C0 2
++#define COM5C1 3
++#define COM5B0 4
++#define COM5B1 5
++#define COM5A0 6
++#define COM5A1 7
++
++#define TCCR5B _SFR_MEM8(0x121)
++#define CS50 0
++#define CS51 1
++#define CS52 2
++#define WGM52 3
++#define WGM53 4
++#define ICES5 6
++#define ICNC5 7
++
++#define TCCR5C _SFR_MEM8(0x122)
++#define FOC5C 5
++#define FOC5B 6
++#define FOC5A 7
++
++/* Reserved [0x123] */
++
++/* Combine TCNT5L and TCNT5H */
++#define TCNT5 _SFR_MEM16(0x124)
++
++#define TCNT5L _SFR_MEM8(0x124)
++#define TCNT5H _SFR_MEM8(0x125)
++
++/* Combine ICR5L and ICR5H */
++#define ICR5 _SFR_MEM16(0x126)
++
++#define ICR5L _SFR_MEM8(0x126)
++#define ICR5H _SFR_MEM8(0x127)
++
++/* Combine OCR5AL and OCR5AH */
++#define OCR5A _SFR_MEM16(0x128)
++
++#define OCR5AL _SFR_MEM8(0x128)
++#define OCR5AH _SFR_MEM8(0x129)
++
++/* Combine OCR5BL and OCR5BH */
++#define OCR5B _SFR_MEM16(0x12A)
++
++#define OCR5BL _SFR_MEM8(0x12A)
++#define OCR5BH _SFR_MEM8(0x12B)
++
++/* Combine OCR5CL and OCR5CH */
++#define OCR5C _SFR_MEM16(0x12C)
++
++#define OCR5CL _SFR_MEM8(0x12C)
++#define OCR5CH _SFR_MEM8(0x12D)
++
++/* Reserved [0x12E] */
++
++#define LLCR _SFR_MEM8(0x12F)
++#define LLENCAL 0
++#define LLSHORT 1
++#define LLTCO 2
++#define LLCAL 3
++#define LLCOMP 4
++#define LLDONE 5
++
++#define LLDRL _SFR_MEM8(0x130)
++#define LLDRL0 0
++#define LLDRL1 1
++#define LLDRL2 2
++#define LLDRL3 3
++
++#define LLDRH _SFR_MEM8(0x131)
++#define LLDRH0 0
++#define LLDRH1 1
++#define LLDRH2 2
++#define LLDRH3 3
++#define LLDRH4 4
++
++#define DRTRAM3 _SFR_MEM8(0x132)
++#define ENDRT 4
++#define DRTSWOK 5
++
++#define DRTRAM2 _SFR_MEM8(0x133)
++
++#define DRTRAM1 _SFR_MEM8(0x134)
++
++#define DRTRAM0 _SFR_MEM8(0x135)
++
++#define DPDS0 _SFR_MEM8(0x136)
++#define PBDRV0 0
++#define PBDRV1 1
++#define PDDRV0 2
++#define PDDRV1 3
++#define PEDRV0 4
++#define PEDRV1 5
++#define PFDRV0 6
++#define PFDRV1 7
++
++#define DPDS1 _SFR_MEM8(0x137)
++#define PGDRV0 0
++#define PGDRV1 1
++
++#define PARCR _SFR_MEM8(0x138)
++#define PARUFI 0
++#define PARDFI 1
++#define PALTU0 2
++#define PALTU1 3
++#define PALTU2 4
++#define PALTD0 5
++#define PALTD1 6
++#define PALTD2 7
++
++#define TRXPR _SFR_MEM8(0x139)
++#define TRXRST 0
++#define SLPTR 1
++
++/* Reserved [0x13A..0x13B] */
++
++#define AES_CTRL _SFR_MEM8(0x13C)
++#define AES_IM 2
++#define AES_DIR 3
++#define AES_MODE 5
++#define AES_REQUEST 7
++
++#define AES_STATUS _SFR_MEM8(0x13D)
++#define AES_DONE 0
++#define AES_ER 7
++
++#define AES_STATE _SFR_MEM8(0x13E)
++#define AES_STATE0 0
++#define AES_STATE1 1
++#define AES_STATE2 2
++#define AES_STATE3 3
++#define AES_STATE4 4
++#define AES_STATE5 5
++#define AES_STATE6 6
++#define AES_STATE7 7
++
++#define AES_KEY _SFR_MEM8(0x13F)
++#define AES_KEY0 0
++#define AES_KEY1 1
++#define AES_KEY2 2
++#define AES_KEY3 3
++#define AES_KEY4 4
++#define AES_KEY5 5
++#define AES_KEY6 6
++#define AES_KEY7 7
++
++/* Reserved [0x140] */
++
++#define TRX_STATUS _SFR_MEM8(0x141)
++#define TRX_STATUS0 0
++#define TRX_STATUS1 1
++#define TRX_STATUS2 2
++#define TRX_STATUS3 3
++#define TRX_STATUS4 4
++#define TST_STATUS 5
++#define CCA_STATUS 6
++#define CCA_DONE 7
++
++#define TRX_STATE _SFR_MEM8(0x142)
++#define TRX_CMD0 0
++#define TRX_CMD1 1
++#define TRX_CMD2 2
++#define TRX_CMD3 3
++#define TRX_CMD4 4
++#define TRAC_STATUS0 5
++#define TRAC_STATUS1 6
++#define TRAC_STATUS2 7
++
++#define TRX_CTRL_0 _SFR_MEM8(0x143)
++#define PMU_IF_INV 4
++#define PMU_START 5
++#define PMU_EN 6
++#define Res7 7
++
++#define TRX_CTRL_1 _SFR_MEM8(0x144)
++#define PLL_TX_FLT 4
++#define TX_AUTO_CRC_ON 5
++#define IRQ_2_EXT_EN 6
++#define PA_EXT_EN 7
++
++#define PHY_TX_PWR _SFR_MEM8(0x145)
++#define TX_PWR0 0
++#define TX_PWR1 1
++#define TX_PWR2 2
++#define TX_PWR3 3
++
++#define PHY_RSSI _SFR_MEM8(0x146)
++#define RSSI0 0
++#define RSSI1 1
++#define RSSI2 2
++#define RSSI3 3
++#define RSSI4 4
++#define RND_VALUE0 5
++#define RND_VALUE1 6
++#define RX_CRC_VALID 7
++
++#define PHY_ED_LEVEL _SFR_MEM8(0x147)
++#define ED_LEVEL0 0
++#define ED_LEVEL1 1
++#define ED_LEVEL2 2
++#define ED_LEVEL3 3
++#define ED_LEVEL4 4
++#define ED_LEVEL5 5
++#define ED_LEVEL6 6
++#define ED_LEVEL7 7
++
++#define PHY_CC_CCA _SFR_MEM8(0x148)
++#define CHANNEL0 0
++#define CHANNEL1 1
++#define CHANNEL2 2
++#define CHANNEL3 3
++#define CHANNEL4 4
++#define CCA_MODE0 5
++#define CCA_MODE1 6
++#define CCA_REQUEST 7
++
++#define CCA_THRES _SFR_MEM8(0x149)
++#define CCA_ED_THRES0 0
++#define CCA_ED_THRES1 1
++#define CCA_ED_THRES2 2
++#define CCA_ED_THRES3 3
++#define CCA_CS_THRES0 4
++#define CCA_CS_THRES1 5
++#define CCA_CS_THRES2 6
++#define CCA_CS_THRES3 7
++
++#define RX_CTRL _SFR_MEM8(0x14A)
++#define PDT_THRES0 0
++#define PDT_THRES1 1
++#define PDT_THRES2 2
++#define PDT_THRES3 3
++
++#define SFD_VALUE _SFR_MEM8(0x14B)
++#define SFD_VALUE0 0
++#define SFD_VALUE1 1
++#define SFD_VALUE2 2
++#define SFD_VALUE3 3
++#define SFD_VALUE4 4
++#define SFD_VALUE5 5
++#define SFD_VALUE6 6
++#define SFD_VALUE7 7
++
++#define TRX_CTRL_2 _SFR_MEM8(0x14C)
++#define OQPSK_DATA_RATE0 0
++#define OQPSK_DATA_RATE1 1
++#define RX_SAFE_MODE 7
++
++#define ANT_DIV _SFR_MEM8(0x14D)
++#define ANT_CTRL0 0
++#define ANT_CTRL1 1
++#define ANT_EXT_SW_EN 2
++#define ANT_DIV_EN 3
++#define ANT_SEL 7
++
++#define IRQ_MASK _SFR_MEM8(0x14E)
++#define PLL_LOCK_EN 0
++#define PLL_UNLOCK_EN 1
++#define RX_START_EN 2
++#define RX_END_EN 3
++#define CCA_ED_DONE_EN 4
++#define AMI_EN 5
++#define TX_END_EN 6
++#define AWAKE_EN 7
++
++#define IRQ_STATUS _SFR_MEM8(0x14F)
++#define PLL_LOCK 0
++#define PLL_UNLOCK 1
++#define RX_START 2
++#define RX_END 3
++#define CCA_ED_DONE 4
++#define AMI 5
++#define TX_END 6
++#define AWAKE 7
++
++#define VREG_CTRL _SFR_MEM8(0x150)
++#define DVDD_OK 2
++#define DVREG_EXT 3
++#define AVDD_OK 6
++#define AVREG_EXT 7
++
++#define BATMON _SFR_MEM8(0x151)
++#define BATMON_VTH0 0
++#define BATMON_VTH1 1
++#define BATMON_VTH2 2
++#define BATMON_VTH3 3
++#define BATMON_HR 4
++#define BATMON_OK 5
++#define BAT_LOW_EN 6
++#define BAT_LOW 7
++
++#define XOSC_CTRL _SFR_MEM8(0x152)
++#define XTAL_TRIM0 0
++#define XTAL_TRIM1 1
++#define XTAL_TRIM2 2
++#define XTAL_TRIM3 3
++#define XTAL_MODE0 4
++#define XTAL_MODE1 5
++#define XTAL_MODE2 6
++#define XTAL_MODE3 7
++
++#define CC_CTRL_0 _SFR_MEM8(0x153)
++#define CC_NUMBER0 0
++#define CC_NUMBER1 1
++#define CC_NUMBER2 2
++#define CC_NUMBER3 3
++#define CC_NUMBER4 4
++#define CC_NUMBER5 5
++#define CC_NUMBER6 6
++#define CC_NUMBER7 7
++
++#define CC_CTRL_1 _SFR_MEM8(0x154)
++#define CC_BAND0 0
++#define CC_BAND1 1
++#define CC_BAND2 2
++#define CC_BAND3 3
++
++#define RX_SYN _SFR_MEM8(0x155)
++#define RX_PDT_LEVEL0 0
++#define RX_PDT_LEVEL1 1
++#define RX_PDT_LEVEL2 2
++#define RX_PDT_LEVEL3 3
++#define RX_OVERRIDE 6
++#define RX_PDT_DIS 7
++
++#define TRX_RPC _SFR_MEM8(0x156)
++#define XAH_RPC_EN 0
++#define IPAN_RPC_EN 1
++#define PLL_RPC_EN 3
++#define PDT_RPC_EN 4
++#define RX_RPC_EN 5
++#define RX_RPC_CTRL0 6
++#define RX_RPC_CTRL1 7
++
++#define XAH_CTRL_1 _SFR_MEM8(0x157)
++#define AACK_PROM_MODE 1
++#define AACK_ACK_TIME 2
++#define AACK_UPLD_RES_FT 4
++#define AACK_FLTR_RES_FT 5
++
++#define FTN_CTRL _SFR_MEM8(0x158)
++#define FTN_START 7
++
++/* Reserved [0x159] */
++
++#define PLL_CF _SFR_MEM8(0x15A)
++#define PLL_CF_START 7
++
++#define PLL_DCU _SFR_MEM8(0x15B)
++#define PLL_DCU_START 7
++
++#define PART_NUM _SFR_MEM8(0x15C)
++#define PART_NUM0 0
++#define PART_NUM1 1
++#define PART_NUM2 2
++#define PART_NUM3 3
++#define PART_NUM4 4
++#define PART_NUM5 5
++#define PART_NUM6 6
++#define PART_NUM7 7
++
++#define VERSION_NUM _SFR_MEM8(0x15D)
++#define VERSION_NUM0 0
++#define VERSION_NUM1 1
++#define VERSION_NUM2 2
++#define VERSION_NUM3 3
++#define VERSION_NUM4 4
++#define VERSION_NUM5 5
++#define VERSION_NUM6 6
++#define VERSION_NUM7 7
++
++#define MAN_ID_0 _SFR_MEM8(0x15E)
++#define MAN_ID_00 0
++#define MAN_ID_01 1
++#define MAN_ID_02 2
++#define MAN_ID_03 3
++#define MAN_ID_04 4
++#define MAN_ID_05 5
++#define MAN_ID_06 6
++#define MAN_ID_07 7
++
++#define MAN_ID_1 _SFR_MEM8(0x15F)
++#define MAN_ID_10 0
++#define MAN_ID_11 1
++#define MAN_ID_12 2
++#define MAN_ID_13 3
++#define MAN_ID_14 4
++#define MAN_ID_15 5
++#define MAN_ID_16 6
++#define MAN_ID_17 7
++
++#define SHORT_ADDR_0 _SFR_MEM8(0x160)
++#define SHORT_ADDR_00 0
++#define SHORT_ADDR_01 1
++#define SHORT_ADDR_02 2
++#define SHORT_ADDR_03 3
++#define SHORT_ADDR_04 4
++#define SHORT_ADDR_05 5
++#define SHORT_ADDR_06 6
++#define SHORT_ADDR_07 7
++
++#define SHORT_ADDR_1 _SFR_MEM8(0x161)
++#define SHORT_ADDR_10 0
++#define SHORT_ADDR_11 1
++#define SHORT_ADDR_12 2
++#define SHORT_ADDR_13 3
++#define SHORT_ADDR_14 4
++#define SHORT_ADDR_15 5
++#define SHORT_ADDR_16 6
++#define SHORT_ADDR_17 7
++
++#define PAN_ID_0 _SFR_MEM8(0x162)
++#define PAN_ID_00 0
++#define PAN_ID_01 1
++#define PAN_ID_02 2
++#define PAN_ID_03 3
++#define PAN_ID_04 4
++#define PAN_ID_05 5
++#define PAN_ID_06 6
++#define PAN_ID_07 7
++
++#define PAN_ID_1 _SFR_MEM8(0x163)
++#define PAN_ID_10 0
++#define PAN_ID_11 1
++#define PAN_ID_12 2
++#define PAN_ID_13 3
++#define PAN_ID_14 4
++#define PAN_ID_15 5
++#define PAN_ID_16 6
++#define PAN_ID_17 7
++
++#define IEEE_ADDR_0 _SFR_MEM8(0x164)
++#define IEEE_ADDR_00 0
++#define IEEE_ADDR_01 1
++#define IEEE_ADDR_02 2
++#define IEEE_ADDR_03 3
++#define IEEE_ADDR_04 4
++#define IEEE_ADDR_05 5
++#define IEEE_ADDR_06 6
++#define IEEE_ADDR_07 7
++
++#define IEEE_ADDR_1 _SFR_MEM8(0x165)
++#define IEEE_ADDR_10 0
++#define IEEE_ADDR_11 1
++#define IEEE_ADDR_12 2
++#define IEEE_ADDR_13 3
++#define IEEE_ADDR_14 4
++#define IEEE_ADDR_15 5
++#define IEEE_ADDR_16 6
++#define IEEE_ADDR_17 7
++
++#define IEEE_ADDR_2 _SFR_MEM8(0x166)
++#define IEEE_ADDR_20 0
++#define IEEE_ADDR_21 1
++#define IEEE_ADDR_22 2
++#define IEEE_ADDR_23 3
++#define IEEE_ADDR_24 4
++#define IEEE_ADDR_25 5
++#define IEEE_ADDR_26 6
++#define IEEE_ADDR_27 7
++
++#define IEEE_ADDR_3 _SFR_MEM8(0x167)
++#define IEEE_ADDR_30 0
++#define IEEE_ADDR_31 1
++#define IEEE_ADDR_32 2
++#define IEEE_ADDR_33 3
++#define IEEE_ADDR_34 4
++#define IEEE_ADDR_35 5
++#define IEEE_ADDR_36 6
++#define IEEE_ADDR_37 7
++
++#define IEEE_ADDR_4 _SFR_MEM8(0x168)
++#define IEEE_ADDR_40 0
++#define IEEE_ADDR_41 1
++#define IEEE_ADDR_42 2
++#define IEEE_ADDR_43 3
++#define IEEE_ADDR_44 4
++#define IEEE_ADDR_45 5
++#define IEEE_ADDR_46 6
++#define IEEE_ADDR_47 7
++
++#define IEEE_ADDR_5 _SFR_MEM8(0x169)
++#define IEEE_ADDR_50 0
++#define IEEE_ADDR_51 1
++#define IEEE_ADDR_52 2
++#define IEEE_ADDR_53 3
++#define IEEE_ADDR_54 4
++#define IEEE_ADDR_55 5
++#define IEEE_ADDR_56 6
++#define IEEE_ADDR_57 7
++
++#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
++#define IEEE_ADDR_60 0
++#define IEEE_ADDR_61 1
++#define IEEE_ADDR_62 2
++#define IEEE_ADDR_63 3
++#define IEEE_ADDR_64 4
++#define IEEE_ADDR_65 5
++#define IEEE_ADDR_66 6
++#define IEEE_ADDR_67 7
++
++#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
++#define IEEE_ADDR_70 0
++#define IEEE_ADDR_71 1
++#define IEEE_ADDR_72 2
++#define IEEE_ADDR_73 3
++#define IEEE_ADDR_74 4
++#define IEEE_ADDR_75 5
++#define IEEE_ADDR_76 6
++#define IEEE_ADDR_77 7
++
++#define XAH_CTRL_0 _SFR_MEM8(0x16C)
++#define SLOTTED_OPERATION 0
++#define MAX_CSMA_RETRIES0 1
++#define MAX_CSMA_RETRIES1 2
++#define MAX_CSMA_RETRIES2 3
++#define MAX_FRAME_RETRIES0 4
++#define MAX_FRAME_RETRIES1 5
++#define MAX_FRAME_RETRIES2 6
++#define MAX_FRAME_RETRIES3 7
++
++#define CSMA_SEED_0 _SFR_MEM8(0x16D)
++#define CSMA_SEED_00 0
++#define CSMA_SEED_01 1
++#define CSMA_SEED_02 2
++#define CSMA_SEED_03 3
++#define CSMA_SEED_04 4
++#define CSMA_SEED_05 5
++#define CSMA_SEED_06 6
++#define CSMA_SEED_07 7
++
++#define CSMA_SEED_1 _SFR_MEM8(0x16E)
++#define CSMA_SEED_10 0
++#define CSMA_SEED_11 1
++#define CSMA_SEED_12 2
++#define AACK_I_AM_COORD 3
++#define AACK_DIS_ACK 4
++#define AACK_SET_PD 5
++#define AACK_FVN_MODE0 6
++#define AACK_FVN_MODE1 7
++
++#define CSMA_BE _SFR_MEM8(0x16F)
++#define MIN_BE0 0
++#define MIN_BE1 1
++#define MIN_BE2 2
++#define MIN_BE3 3
++#define MAX_BE0 4
++#define MAX_BE1 5
++#define MAX_BE2 6
++#define MAX_BE3 7
++
++/* Reserved [0x170..0x175] */
++
++#define TST_CTRL_DIGI _SFR_MEM8(0x176)
++#define TST_CTRL_DIG0 0
++#define TST_CTRL_DIG1 1
++#define TST_CTRL_DIG2 2
++#define TST_CTRL_DIG3 3
++
++/* Reserved [0x177..0x17A] */
++
++#define TST_RX_LENGTH _SFR_MEM8(0x17B)
++#define RX_LENGTH0 0
++#define RX_LENGTH1 1
++#define RX_LENGTH2 2
++#define RX_LENGTH3 3
++#define RX_LENGTH4 4
++#define RX_LENGTH5 5
++#define RX_LENGTH6 6
++#define RX_LENGTH7 7
++
++/* Reserved [0x17C..0x17F] */
++
++#define TRXFBST _SFR_MEM8(0x180)
++
++/* Reserved [0x181..0x1FE] */
++
++#define TRXFBEND _SFR_MEM8(0x1FF)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* External Interrupt Request 3 */
++#define INT3_vect _VECTOR(4)
++#define INT3_vect_num 4
++
++/* External Interrupt Request 4 */
++#define INT4_vect _VECTOR(5)
++#define INT4_vect_num 5
++
++/* External Interrupt Request 5 */
++#define INT5_vect _VECTOR(6)
++#define INT5_vect_num 6
++
++/* External Interrupt Request 6 */
++#define INT6_vect _VECTOR(7)
++#define INT6_vect_num 7
++
++/* External Interrupt Request 7 */
++#define INT7_vect _VECTOR(8)
++#define INT7_vect_num 8
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(9)
++#define PCINT0_vect_num 9
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(10)
++#define PCINT1_vect_num 10
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(11)
++#define PCINT2_vect_num 11
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(12)
++#define WDT_vect_num 12
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(13)
++#define TIMER2_COMPA_vect_num 13
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(14)
++#define TIMER2_COMPB_vect_num 14
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(15)
++#define TIMER2_OVF_vect_num 15
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(16)
++#define TIMER1_CAPT_vect_num 16
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(17)
++#define TIMER1_COMPA_vect_num 17
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(18)
++#define TIMER1_COMPB_vect_num 18
++
++/* Timer/Counter1 Compare Match C */
++#define TIMER1_COMPC_vect _VECTOR(19)
++#define TIMER1_COMPC_vect_num 19
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(20)
++#define TIMER1_OVF_vect_num 20
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(21)
++#define TIMER0_COMPA_vect_num 21
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(22)
++#define TIMER0_COMPB_vect_num 22
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(23)
++#define TIMER0_OVF_vect_num 23
++
++/* SPI Serial Transfer Complete */
++#define SPI_STC_vect _VECTOR(24)
++#define SPI_STC_vect_num 24
++
++/* USART0, Rx Complete */
++#define USART0_RX_vect _VECTOR(25)
++#define USART0_RX_vect_num 25
++
++/* USART0 Data register Empty */
++#define USART0_UDRE_vect _VECTOR(26)
++#define USART0_UDRE_vect_num 26
++
++/* USART0, Tx Complete */
++#define USART0_TX_vect _VECTOR(27)
++#define USART0_TX_vect_num 27
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(28)
++#define ANALOG_COMP_vect_num 28
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(29)
++#define ADC_vect_num 29
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(30)
++#define EE_READY_vect_num 30
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(31)
++#define TIMER3_CAPT_vect_num 31
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(32)
++#define TIMER3_COMPA_vect_num 32
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(33)
++#define TIMER3_COMPB_vect_num 33
++
++/* Timer/Counter3 Compare Match C */
++#define TIMER3_COMPC_vect _VECTOR(34)
++#define TIMER3_COMPC_vect_num 34
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(35)
++#define TIMER3_OVF_vect_num 35
++
++/* USART1, Rx Complete */
++#define USART1_RX_vect _VECTOR(36)
++#define USART1_RX_vect_num 36
++
++/* USART1 Data register Empty */
++#define USART1_UDRE_vect _VECTOR(37)
++#define USART1_UDRE_vect_num 37
++
++/* USART1, Tx Complete */
++#define USART1_TX_vect _VECTOR(38)
++#define USART1_TX_vect_num 38
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(39)
++#define TWI_vect_num 39
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(40)
++#define SPM_READY_vect_num 40
++
++/* Timer/Counter4 Capture Event */
++#define TIMER4_CAPT_vect _VECTOR(41)
++#define TIMER4_CAPT_vect_num 41
++
++/* Timer/Counter4 Compare Match A */
++#define TIMER4_COMPA_vect _VECTOR(42)
++#define TIMER4_COMPA_vect_num 42
++
++/* Timer/Counter4 Compare Match B */
++#define TIMER4_COMPB_vect _VECTOR(43)
++#define TIMER4_COMPB_vect_num 43
++
++/* Timer/Counter4 Compare Match C */
++#define TIMER4_COMPC_vect _VECTOR(44)
++#define TIMER4_COMPC_vect_num 44
++
++/* Timer/Counter4 Overflow */
++#define TIMER4_OVF_vect _VECTOR(45)
++#define TIMER4_OVF_vect_num 45
++
++/* Timer/Counter5 Capture Event */
++#define TIMER5_CAPT_vect _VECTOR(46)
++#define TIMER5_CAPT_vect_num 46
++
++/* Timer/Counter5 Compare Match A */
++#define TIMER5_COMPA_vect _VECTOR(47)
++#define TIMER5_COMPA_vect_num 47
++
++/* Timer/Counter5 Compare Match B */
++#define TIMER5_COMPB_vect _VECTOR(48)
++#define TIMER5_COMPB_vect_num 48
++
++/* Timer/Counter5 Compare Match C */
++#define TIMER5_COMPC_vect _VECTOR(49)
++#define TIMER5_COMPC_vect_num 49
++
++/* Timer/Counter5 Overflow */
++#define TIMER5_OVF_vect _VECTOR(50)
++#define TIMER5_OVF_vect_num 50
++
++/* USART2, Rx Complete */
++#define USART2_RX_vect _VECTOR(51)
++#define USART2_RX_vect_num 51
++
++/* USART2 Data register Empty */
++#define USART2_UDRE_vect _VECTOR(52)
++#define USART2_UDRE_vect_num 52
++
++/* USART2, Tx Complete */
++#define USART2_TX_vect _VECTOR(53)
++#define USART2_TX_vect_num 53
++
++/* USART3, Rx Complete */
++#define USART3_RX_vect _VECTOR(54)
++#define USART3_RX_vect_num 54
++
++/* USART3 Data register Empty */
++#define USART3_UDRE_vect _VECTOR(55)
++#define USART3_UDRE_vect_num 55
++
++/* USART3, Tx Complete */
++#define USART3_TX_vect _VECTOR(56)
++#define USART3_TX_vect_num 56
++
++/* TRX24 - PLL lock interrupt */
++#define TRX24_PLL_LOCK_vect _VECTOR(57)
++#define TRX24_PLL_LOCK_vect_num 57
++
++/* TRX24 - PLL unlock interrupt */
++#define TRX24_PLL_UNLOCK_vect _VECTOR(58)
++#define TRX24_PLL_UNLOCK_vect_num 58
++
++/* TRX24 - Receive start interrupt */
++#define TRX24_RX_START_vect _VECTOR(59)
++#define TRX24_RX_START_vect_num 59
++
++/* TRX24 - RX_END interrupt */
++#define TRX24_RX_END_vect _VECTOR(60)
++#define TRX24_RX_END_vect_num 60
++
++/* TRX24 - CCA/ED done interrupt */
++#define TRX24_CCA_ED_DONE_vect _VECTOR(61)
++#define TRX24_CCA_ED_DONE_vect_num 61
++
++/* TRX24 - XAH - AMI */
++#define TRX24_XAH_AMI_vect _VECTOR(62)
++#define TRX24_XAH_AMI_vect_num 62
++
++/* TRX24 - TX_END interrupt */
++#define TRX24_TX_END_vect _VECTOR(63)
++#define TRX24_TX_END_vect_num 63
++
++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
++#define TRX24_AWAKE_vect _VECTOR(64)
++#define TRX24_AWAKE_vect_num 64
++
++/* Symbol counter - compare match 1 interrupt */
++#define SCNT_CMP1_vect _VECTOR(65)
++#define SCNT_CMP1_vect_num 65
++
++/* Symbol counter - compare match 2 interrupt */
++#define SCNT_CMP2_vect _VECTOR(66)
++#define SCNT_CMP2_vect_num 66
++
++/* Symbol counter - compare match 3 interrupt */
++#define SCNT_CMP3_vect _VECTOR(67)
++#define SCNT_CMP3_vect_num 67
++
++/* Symbol counter - overflow interrupt */
++#define SCNT_OVFL_vect _VECTOR(68)
++#define SCNT_OVFL_vect_num 68
++
++/* Symbol counter - backoff interrupt */
++#define SCNT_BACKOFF_vect _VECTOR(69)
++#define SCNT_BACKOFF_vect_num 69
++
++/* AES engine ready interrupt */
++#define AES_READY_vect _VECTOR(70)
++#define AES_READY_vect_num 70
++
++/* Battery monitor indicates supply voltage below threshold */
++#define BAT_LOW_vect _VECTOR(71)
++#define BAT_LOW_vect_num 71
++
++/* TRX24 TX start interrupt */
++#define TRX24_TX_START_vect _VECTOR(72)
++#define TRX24_TX_START_vect_num 72
++
++/* Address match interrupt of address filter 0 */
++#define TRX24_AMI0_vect _VECTOR(73)
++#define TRX24_AMI0_vect_num 73
++
++/* Address match interrupt of address filter 1 */
++#define TRX24_AMI1_vect _VECTOR(74)
++#define TRX24_AMI1_vect_num 74
++
++/* Address match interrupt of address filter 2 */
++#define TRX24_AMI2_vect _VECTOR(75)
++#define TRX24_AMI2_vect_num 75
++
++/* Address match interrupt of address filter 3 */
++#define TRX24_AMI3_vect _VECTOR(76)
++#define TRX24_AMI3_vect_num 76
++
++#define _VECTORS_SIZE 308
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHSTART 0x0000
++#define FLASHEND 0x3FFFF
++#define RAMSTART 0x0200
++#define RAMSIZE 32768
++#define RAMEND 0x81FF
++#define E2START 0
++#define E2SIZE 8192
++#define E2PAGESIZE 8
++#define E2END 0x1FFF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0)
++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1)
++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2)
++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3)
++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4)
++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0xA8
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA256RFR2_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iom3290p.h avr-libc-1.8.0/include/avr/iom3290p.h
+--- avr-libc-1.8.0.orig/include/avr/iom3290p.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom3290p.h 2013-01-18 10:08:39.000000000 +0100
+@@ -0,0 +1,34 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2011 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++#include "iom3290.h"
+diff -urN avr-libc-1.8.0.orig/include/avr/iom64rfr2.h avr-libc-1.8.0/include/avr/iom64rfr2.h
+--- avr-libc-1.8.0.orig/include/avr/iom64rfr2.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iom64rfr2.h 2013-01-18 10:08:39.000000000 +0100
+@@ -0,0 +1,2566 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_ATMEGA64RFR2_H_INCLUDED
++#define _AVR_ATMEGA64RFR2_H_INCLUDED
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iom64rfr2.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++/* Registers and associated bit numbers */
++
++#define PINA _SFR_IO8(0x00)
++#define PINA7 7
++#define PINA6 6
++#define PINA5 5
++#define PINA4 4
++#define PINA3 3
++#define PINA2 2
++#define PINA1 1
++#define PINA0 0
++
++#define DDRA _SFR_IO8(0x01)
++#define DDRA7 7
++#define DDRA6 6
++#define DDRA5 5
++#define DDRA4 4
++#define DDRA3 3
++#define DDRA2 2
++#define DDRA1 1
++#define DDRA0 0
++
++#define PORTA _SFR_IO8(0x02)
++#define PORTA7 7
++#define PORTA6 6
++#define PORTA5 5
++#define PORTA4 4
++#define PORTA3 3
++#define PORTA2 2
++#define PORTA1 1
++#define PORTA0 0
++
++#define PINB _SFR_IO8(0x03)
++#define PINB7 7
++#define PINB6 6
++#define PINB5 5
++#define PINB4 4
++#define PINB3 3
++#define PINB2 2
++#define PINB1 1
++#define PINB0 0
++
++#define DDRB _SFR_IO8(0x04)
++#define DDRB7 7
++#define DDRB6 6
++#define DDRB5 5
++#define DDRB4 4
++#define DDRB3 3
++#define DDRB2 2
++#define DDRB1 1
++#define DDRB0 0
++
++#define PORTB _SFR_IO8(0x05)
++#define PORTB7 7
++#define PORTB6 6
++#define PORTB5 5
++#define PORTB4 4
++#define PORTB3 3
++#define PORTB2 2
++#define PORTB1 1
++#define PORTB0 0
++
++#define PINC _SFR_IO8(0x06)
++#define PINC7 7
++#define PINC6 6
++#define PINC5 5
++#define PINC4 4
++#define PINC3 3
++#define PINC2 2
++#define PINC1 1
++#define PINC0 0
++
++#define DDRC _SFR_IO8(0x07)
++#define DDRC7 7
++#define DDRC6 6
++#define DDRC5 5
++#define DDRC4 4
++#define DDRC3 3
++#define DDRC2 2
++#define DDRC1 1
++#define DDRC0 0
++
++#define PORTC _SFR_IO8(0x08)
++#define PORTC7 7
++#define PORTC6 6
++#define PORTC5 5
++#define PORTC4 4
++#define PORTC3 3
++#define PORTC2 2
++#define PORTC1 1
++#define PORTC0 0
++
++#define PIND _SFR_IO8(0x09)
++#define PIND7 7
++#define PIND6 6
++#define PIND5 5
++#define PIND4 4
++#define PIND3 3
++#define PIND2 2
++#define PIND1 1
++#define PIND0 0
++
++#define DDRD _SFR_IO8(0x0A)
++#define DDRD7 7
++#define DDRD6 6
++#define DDRD5 5
++#define DDRD4 4
++#define DDRD3 3
++#define DDRD2 2
++#define DDRD1 1
++#define DDRD0 0
++
++#define PORTD _SFR_IO8(0x0B)
++#define PORTD7 7
++#define PORTD6 6
++#define PORTD5 5
++#define PORTD4 4
++#define PORTD3 3
++#define PORTD2 2
++#define PORTD1 1
++#define PORTD0 0
++
++#define PINE _SFR_IO8(0x0C)
++#define PINE7 7
++#define PINE6 6
++#define PINE5 5
++#define PINE4 4
++#define PINE3 3
++#define PINE2 2
++#define PINE1 1
++#define PINE0 0
++
++#define DDRE _SFR_IO8(0x0D)
++#define DDRE7 7
++#define DDRE6 6
++#define DDRE5 5
++#define DDRE4 4
++#define DDRE3 3
++#define DDRE2 2
++#define DDRE1 1
++#define DDRE0 0
++
++#define PORTE _SFR_IO8(0x0E)
++#define PORTE7 7
++#define PORTE6 6
++#define PORTE5 5
++#define PORTE4 4
++#define PORTE3 3
++#define PORTE2 2
++#define PORTE1 1
++#define PORTE0 0
++
++#define PINF _SFR_IO8(0x0F)
++#define PINF7 7
++#define PINF6 6
++#define PINF5 5
++#define PINF4 4
++#define PINF3 3
++#define PINF2 2
++#define PINF1 1
++#define PINF0 0
++
++#define DDRF _SFR_IO8(0x10)
++#define DDRF7 7
++#define DDRF6 6
++#define DDRF5 5
++#define DDRF4 4
++#define DDRF3 3
++#define DDRF2 2
++#define DDRF1 1
++#define DDRF0 0
++
++#define PORTF _SFR_IO8(0x11)
++#define PORTF7 7
++#define PORTF6 6
++#define PORTF5 5
++#define PORTF4 4
++#define PORTF3 3
++#define PORTF2 2
++#define PORTF1 1
++#define PORTF0 0
++
++#define PING _SFR_IO8(0x12)
++#define PING7 7
++#define PING6 6
++#define PING5 5
++#define PING4 4
++#define PING3 3
++#define PING2 2
++#define PING1 1
++#define PING0 0
++
++#define DDRG _SFR_IO8(0x13)
++#define DDRG7 7
++#define DDRG6 6
++#define DDRG5 5
++#define DDRG4 4
++#define DDRG3 3
++#define DDRG2 2
++#define DDRG1 1
++#define DDRG0 0
++
++#define PORTG _SFR_IO8(0x14)
++#define PORTG7 7
++#define PORTG6 6
++#define PORTG5 5
++#define PORTG4 4
++#define PORTG3 3
++#define PORTG2 2
++#define PORTG1 1
++#define PORTG0 0
++
++#define TIFR0 _SFR_IO8(0x15)
++#define TOV0 0
++#define OCF0A 1
++#define OCF0B 2
++#define Res0 3
++#define Res1 4
++#define Res2 5
++#define Res3 6
++#define Res4 7
++
++#define TIFR1 _SFR_IO8(0x16)
++#define TOV1 0
++#define OCF1A 1
++#define OCF1B 2
++#define OCF1C 3
++#define ICF1 5
++
++#define TIFR2 _SFR_IO8(0x17)
++#define TOV2 0
++#define OCF2A 1
++#define OCF2B 2
++
++#define TIFR3 _SFR_IO8(0x18)
++#define TOV3 0
++#define OCF3A 1
++#define OCF3B 2
++#define OCF3C 3
++#define ICF3 5
++
++#define TIFR4 _SFR_IO8(0x19)
++#define TOV4 0
++#define OCF4A 1
++#define OCF4B 2
++#define OCF4C 3
++#define ICF4 5
++
++#define TIFR5 _SFR_IO8(0x1A)
++#define TOV5 0
++#define OCF5A 1
++#define OCF5B 2
++#define OCF5C 3
++#define ICF5 5
++
++#define PCIFR _SFR_IO8(0x1B)
++#define PCIF0 0
++#define PCIF1 1
++#define PCIF2 2
++
++#define EIFR _SFR_IO8(0x1C)
++#define INTF0 0
++#define INTF1 1
++#define INTF2 2
++#define INTF3 3
++#define INTF4 4
++#define INTF5 5
++#define INTF6 6
++#define INTF7 7
++
++#define EIMSK _SFR_IO8(0x1D)
++#define INT0 0
++#define INT1 1
++#define INT2 2
++#define INT3 3
++#define INT4 4
++#define INT5 5
++#define INT6 6
++#define INT7 7
++
++#define GPIOR0 _SFR_IO8(0x1E)
++#define GPIOR00 0
++#define GPIOR01 1
++#define GPIOR02 2
++#define GPIOR03 3
++#define GPIOR04 4
++#define GPIOR05 5
++#define GPIOR06 6
++#define GPIOR07 7
++
++#define EECR _SFR_IO8(0x1F)
++#define EERE 0
++#define EEPE 1
++#define EEMPE 2
++#define EERIE 3
++#define EEPM0 4
++#define EEPM1 5
++
++#define EEDR _SFR_IO8(0x20)
++
++/* Combine EEARL and EEARH */
++#define EEAR _SFR_IO16(0x21)
++
++#define EEARL _SFR_IO8(0x21)
++#define EEARH _SFR_IO8(0x22)
++
++#define GTCCR _SFR_IO8(0x23)
++#define PSRSYNC 0
++#define PSRASY 1
++#define TSM 7
++
++#define TCCR0A _SFR_IO8(0x24)
++#define WGM00 0
++#define WGM01 1
++#define COM0B0 4
++#define COM0B1 5
++#define COM0A0 6
++#define COM0A1 7
++
++#define TCCR0B _SFR_IO8(0x25)
++#define CS00 0
++#define CS01 1
++#define CS02 2
++#define WGM02 3
++#define FOC0B 6
++#define FOC0A 7
++
++#define TCNT0 _SFR_IO8(0x26)
++
++#define OCR0A _SFR_IO8(0x27)
++
++#define OCR0B _SFR_IO8(0x28)
++
++/* Reserved [0x29] */
++
++#define GPIOR1 _SFR_IO8(0x2A)
++#define GPIOR10 0
++#define GPIOR11 1
++#define GPIOR12 2
++#define GPIOR13 3
++#define GPIOR14 4
++#define GPIOR15 5
++#define GPIOR16 6
++#define GPIOR17 7
++
++#define GPIOR2 _SFR_IO8(0x2B)
++#define GPIOR20 0
++#define GPIOR21 1
++#define GPIOR22 2
++#define GPIOR23 3
++#define GPIOR24 4
++#define GPIOR25 5
++#define GPIOR26 6
++#define GPIOR27 7
++
++#define SPCR _SFR_IO8(0x2C)
++#define SPR0 0
++#define SPR1 1
++#define CPHA 2
++#define CPOL 3
++#define MSTR 4
++#define DORD 5
++#define SPE 6
++#define SPIE 7
++
++#define SPSR _SFR_IO8(0x2D)
++#define SPI2X 0
++#define WCOL 6
++#define SPIF 7
++
++#define SPDR _SFR_IO8(0x2E)
++
++/* Reserved [0x2F] */
++
++#define ACSR _SFR_IO8(0x30)
++#define ACIS0 0
++#define ACIS1 1
++#define ACIC 2
++#define ACIE 3
++#define ACI 4
++#define ACO 5
++#define ACBG 6
++#define ACD 7
++
++#define OCDR _SFR_IO8(0x31)
++#define OCDR0 0
++#define OCDR1 1
++#define OCDR2 2
++#define OCDR3 3
++#define OCDR4 4
++#define OCDR5 5
++#define OCDR6 6
++#define OCDR7 7
++#define OCDR7 7
++#define OCDR6 6
++#define OCDR5 5
++#define OCDR4 4
++#define OCDR3 3
++#define OCDR2 2
++#define OCDR1 1
++#define OCDR0 0
++
++/* Reserved [0x32] */
++
++#define SMCR _SFR_IO8(0x33)
++#define SE 0
++#define SM0 1
++#define SM1 2
++#define SM2 3
++
++#define MCUSR _SFR_IO8(0x34)
++#define JTRF 4
++#define PORF 0
++#define EXTRF 1
++#define BORF 2
++#define WDRF 3
++
++#define MCUCR _SFR_IO8(0x35)
++#define JTD 7
++#define IVCE 0
++#define IVSEL 1
++#define PUD 4
++
++/* Reserved [0x36] */
++
++#define SPMCSR _SFR_IO8(0x37)
++#define SPMEN 0
++#define PGERS 1
++#define PGWRT 2
++#define BLBSET 3
++#define RWWSRE 4
++#define SIGRD 5
++#define RWWSB 6
++#define SPMIE 7
++
++/* Reserved [0x38..0x3C] */
++
++/* SP [0x3D..0x3E] */
++
++/* SREG [0x3F] */
++
++#define WDTCSR _SFR_MEM8(0x60)
++#define WDE 3
++#define WDCE 4
++#define WDP0 0
++#define WDP1 1
++#define WDP2 2
++#define WDP3 5
++#define WDIE 6
++#define WDIF 7
++
++#define CLKPR _SFR_MEM8(0x61)
++#define CLKPS0 0
++#define CLKPS1 1
++#define CLKPS2 2
++#define CLKPS3 3
++#define CLKPCE 7
++
++/* Reserved [0x62] */
++
++#define PRR2 _SFR_MEM8(0x63)
++#define PRRAM0 0
++#define PRRAM1 1
++#define PRRAM2 2
++#define PRRAM3 3
++
++#define PRR0 _SFR_MEM8(0x64)
++#define PRADC 0
++#define PRUSART0 1
++#define PRSPI 2
++#define PRTIM1 3
++#define PRPGA 4
++#define PRTIM0 5
++#define PRTIM2 6
++#define PRTWI 7
++
++#define PRR1 _SFR_MEM8(0x65)
++#define PRUSART1 0
++#define PRTIM3 3
++#define PRTIM4 4
++#define PRTIM5 5
++#define PRTRX24 6
++#define Res 7
++
++#define OSCCAL _SFR_MEM8(0x66)
++#define CAL0 0
++#define CAL1 1
++#define CAL2 2
++#define CAL3 3
++#define CAL4 4
++#define CAL5 5
++#define CAL6 6
++#define CAL7 7
++
++#define BGCR _SFR_MEM8(0x67)
++#define BGCAL0 0
++#define BGCAL1 1
++#define BGCAL2 2
++#define BGCAL_FINE0 3
++#define BGCAL_FINE1 4
++#define BGCAL_FINE2 5
++#define BGCAL_FINE3 6
++
++#define PCICR _SFR_MEM8(0x68)
++#define PCIE0 0
++#define PCIE1 1
++#define PCIE2 2
++
++#define EICRA _SFR_MEM8(0x69)
++#define ISC00 0
++#define ISC01 1
++#define ISC10 2
++#define ISC11 3
++#define ISC20 4
++#define ISC21 5
++#define ISC30 6
++#define ISC31 7
++
++#define EICRB _SFR_MEM8(0x6A)
++#define ISC40 0
++#define ISC41 1
++#define ISC50 2
++#define ISC51 3
++#define ISC60 4
++#define ISC61 5
++#define ISC70 6
++#define ISC71 7
++
++#define PCMSK0 _SFR_MEM8(0x6B)
++
++#define PCMSK1 _SFR_MEM8(0x6C)
++#define PCINT8 0
++#define PCINT9 1
++#define PCINT10 2
++#define PCINT11 3
++#define PCINT12 4
++#define PCINT13 5
++#define PCINT14 6
++#define PCINT15 7
++
++#define PCMSK2 _SFR_MEM8(0x6D)
++#define PCINT16 0
++#define PCINT17 1
++#define PCINT18 2
++#define PCINT19 3
++#define PCINT20 4
++#define PCINT21 5
++#define PCINT22 6
++#define PCINT23 7
++
++#define TIMSK0 _SFR_MEM8(0x6E)
++#define TOIE0 0
++#define OCIE0A 1
++#define OCIE0B 2
++
++#define TIMSK1 _SFR_MEM8(0x6F)
++#define TOIE1 0
++#define OCIE1A 1
++#define OCIE1B 2
++#define OCIE1C 3
++#define ICIE1 5
++
++#define TIMSK2 _SFR_MEM8(0x70)
++#define TOIE2 0
++#define OCIE2A 1
++#define OCIE2B 2
++
++#define TIMSK3 _SFR_MEM8(0x71)
++#define TOIE3 0
++#define OCIE3A 1
++#define OCIE3B 2
++#define OCIE3C 3
++#define ICIE3 5
++
++#define TIMSK4 _SFR_MEM8(0x72)
++#define TOIE4 0
++#define OCIE4A 1
++#define OCIE4B 2
++#define OCIE4C 3
++#define ICIE4 5
++
++#define TIMSK5 _SFR_MEM8(0x73)
++#define TOIE5 0
++#define OCIE5A 1
++#define OCIE5B 2
++#define OCIE5C 3
++#define ICIE5 5
++
++/* Reserved [0x74] */
++
++#define NEMCR _SFR_MEM8(0x75)
++#define AEAM0 4
++#define AEAM1 5
++#define ENEAM 6
++
++/* Reserved [0x76] */
++
++#define ADCSRC _SFR_MEM8(0x77)
++#define ADSUT0 0
++#define ADSUT1 1
++#define ADSUT2 2
++#define ADSUT3 3
++#define ADSUT4 4
++#define ADTHT0 6
++#define ADTHT1 7
++
++/* Combine ADCL and ADCH */
++#ifndef __ASSEMBLER__
++#define ADC _SFR_MEM16(0x78)
++#endif
++#define ADCW _SFR_MEM16(0x78)
++
++#define ADCL _SFR_MEM8(0x78)
++#define ADCH _SFR_MEM8(0x79)
++
++#define ADCSRA _SFR_MEM8(0x7A)
++#define ADPS0 0
++#define ADPS1 1
++#define ADPS2 2
++#define ADIE 3
++#define ADIF 4
++#define ADATE 5
++#define ADSC 6
++#define ADEN 7
++
++#define ADCSRB _SFR_MEM8(0x7B)
++#define ACME 6
++#define ADTS0 0
++#define ADTS1 1
++#define ADTS2 2
++#define MUX5 3
++#define ACCH 4
++#define REFOK 5
++#define AVDDOK 7
++
++#define ADMUX _SFR_MEM8(0x7C)
++#define MUX0 0
++#define MUX1 1
++#define MUX2 2
++#define MUX3 3
++#define MUX4 4
++#define ADLAR 5
++#define REFS0 6
++#define REFS1 7
++
++#define DIDR2 _SFR_MEM8(0x7D)
++#define ADC8D 0
++#define ADC9D 1
++#define ADC10D 2
++#define ADC11D 3
++#define ADC12D 4
++#define ADC13D 5
++#define ADC14D 6
++#define ADC15D 7
++
++#define DIDR0 _SFR_MEM8(0x7E)
++#define ADC0D 0
++#define ADC1D 1
++#define ADC2D 2
++#define ADC3D 3
++#define ADC4D 4
++#define ADC5D 5
++#define ADC6D 6
++#define ADC7D 7
++
++#define DIDR1 _SFR_MEM8(0x7F)
++#define AIN0D 0
++#define AIN1D 1
++
++#define TCCR1A _SFR_MEM8(0x80)
++#define WGM10 0
++#define WGM11 1
++#define COM1C0 2
++#define COM1C1 3
++#define COM1B0 4
++#define COM1B1 5
++#define COM1A0 6
++#define COM1A1 7
++
++#define TCCR1B _SFR_MEM8(0x81)
++#define CS10 0
++#define CS11 1
++#define CS12 2
++#define WGM12 3
++#define WGM13 4
++#define ICES1 6
++#define ICNC1 7
++
++#define TCCR1C _SFR_MEM8(0x82)
++#define FOC1C 5
++#define FOC1B 6
++#define FOC1A 7
++
++/* Reserved [0x83] */
++
++/* Combine TCNT1L and TCNT1H */
++#define TCNT1 _SFR_MEM16(0x84)
++
++#define TCNT1L _SFR_MEM8(0x84)
++#define TCNT1H _SFR_MEM8(0x85)
++
++/* Combine ICR1L and ICR1H */
++#define ICR1 _SFR_MEM16(0x86)
++
++#define ICR1L _SFR_MEM8(0x86)
++#define ICR1H _SFR_MEM8(0x87)
++
++/* Combine OCR1AL and OCR1AH */
++#define OCR1A _SFR_MEM16(0x88)
++
++#define OCR1AL _SFR_MEM8(0x88)
++#define OCR1AH _SFR_MEM8(0x89)
++
++/* Combine OCR1BL and OCR1BH */
++#define OCR1B _SFR_MEM16(0x8A)
++
++#define OCR1BL _SFR_MEM8(0x8A)
++#define OCR1BH _SFR_MEM8(0x8B)
++
++/* Combine OCR1CL and OCR1CH */
++#define OCR1C _SFR_MEM16(0x8C)
++
++#define OCR1CL _SFR_MEM8(0x8C)
++#define OCR1CH _SFR_MEM8(0x8D)
++
++/* Reserved [0x8E..0x8F] */
++
++#define TCCR3A _SFR_MEM8(0x90)
++#define WGM30 0
++#define WGM31 1
++#define COM3C0 2
++#define COM3C1 3
++#define COM3B0 4
++#define COM3B1 5
++#define COM3A0 6
++#define COM3A1 7
++
++#define TCCR3B _SFR_MEM8(0x91)
++#define CS30 0
++#define CS31 1
++#define CS32 2
++#define WGM32 3
++#define WGM33 4
++#define ICES3 6
++#define ICNC3 7
++
++#define TCCR3C _SFR_MEM8(0x92)
++#define FOC3C 5
++#define FOC3B 6
++#define FOC3A 7
++
++/* Reserved [0x93] */
++
++/* Combine TCNT3L and TCNT3H */
++#define TCNT3 _SFR_MEM16(0x94)
++
++#define TCNT3L _SFR_MEM8(0x94)
++#define TCNT3H _SFR_MEM8(0x95)
++
++/* Combine ICR3L and ICR3H */
++#define ICR3 _SFR_MEM16(0x96)
++
++#define ICR3L _SFR_MEM8(0x96)
++#define ICR3H _SFR_MEM8(0x97)
++
++/* Combine OCR3AL and OCR3AH */
++#define OCR3A _SFR_MEM16(0x98)
++
++#define OCR3AL _SFR_MEM8(0x98)
++#define OCR3AH _SFR_MEM8(0x99)
++
++/* Combine OCR3BL and OCR3BH */
++#define OCR3B _SFR_MEM16(0x9A)
++
++#define OCR3BL _SFR_MEM8(0x9A)
++#define OCR3BH _SFR_MEM8(0x9B)
++
++/* Combine OCR3CL and OCR3CH */
++#define OCR3C _SFR_MEM16(0x9C)
++
++#define OCR3CL _SFR_MEM8(0x9C)
++#define OCR3CH _SFR_MEM8(0x9D)
++
++/* Reserved [0x9E..0x9F] */
++
++#define TCCR4A _SFR_MEM8(0xA0)
++#define WGM40 0
++#define WGM41 1
++#define COM4C0 2
++#define COM4C1 3
++#define COM4B0 4
++#define COM4B1 5
++#define COM4A0 6
++#define COM4A1 7
++
++#define TCCR4B _SFR_MEM8(0xA1)
++#define CS40 0
++#define CS41 1
++#define CS42 2
++#define WGM42 3
++#define WGM43 4
++#define ICES4 6
++#define ICNC4 7
++
++#define TCCR4C _SFR_MEM8(0xA2)
++#define FOC4C 5
++#define FOC4B 6
++#define FOC4A 7
++
++/* Reserved [0xA3] */
++
++/* Combine TCNT4L and TCNT4H */
++#define TCNT4 _SFR_MEM16(0xA4)
++
++#define TCNT4L _SFR_MEM8(0xA4)
++#define TCNT4H _SFR_MEM8(0xA5)
++
++/* Combine ICR4L and ICR4H */
++#define ICR4 _SFR_MEM16(0xA6)
++
++#define ICR4L _SFR_MEM8(0xA6)
++#define ICR4H _SFR_MEM8(0xA7)
++
++/* Combine OCR4AL and OCR4AH */
++#define OCR4A _SFR_MEM16(0xA8)
++
++#define OCR4AL _SFR_MEM8(0xA8)
++#define OCR4AH _SFR_MEM8(0xA9)
++
++/* Combine OCR4BL and OCR4BH */
++#define OCR4B _SFR_MEM16(0xAA)
++
++#define OCR4BL _SFR_MEM8(0xAA)
++#define OCR4BH _SFR_MEM8(0xAB)
++
++/* Combine OCR4CL and OCR4CH */
++#define OCR4C _SFR_MEM16(0xAC)
++
++#define OCR4CL _SFR_MEM8(0xAC)
++#define OCR4CH _SFR_MEM8(0xAD)
++
++/* Reserved [0xAE..0xAF] */
++
++#define TCCR2A _SFR_MEM8(0xB0)
++#define WGM20 0
++#define WGM21 1
++#define COM2B0 4
++#define COM2B1 5
++#define COM2A0 6
++#define COM2A1 7
++
++#define TCCR2B _SFR_MEM8(0xB1)
++#define CS20 0
++#define CS21 1
++#define CS22 2
++#define WGM22 3
++#define FOC2B 6
++#define FOC2A 7
++
++#define TCNT2 _SFR_MEM8(0xB2)
++
++#define OCR2A _SFR_MEM8(0xB3)
++
++#define OCR2B _SFR_MEM8(0xB4)
++
++/* Reserved [0xB5] */
++
++#define ASSR _SFR_MEM8(0xB6)
++#define TCR2BUB 0
++#define TCR2AUB 1
++#define OCR2BUB 2
++#define OCR2AUB 3
++#define TCN2UB 4
++#define AS2 5
++#define EXCLK 6
++#define EXCLKAMR 7
++
++/* Reserved [0xB7] */
++
++#define TWBR _SFR_MEM8(0xB8)
++
++#define TWSR _SFR_MEM8(0xB9)
++#define TWPS0 0
++#define TWPS1 1
++#define TWS3 3
++#define TWS4 4
++#define TWS5 5
++#define TWS6 6
++#define TWS7 7
++
++#define TWAR _SFR_MEM8(0xBA)
++#define TWGCE 0
++#define TWA0 1
++#define TWA1 2
++#define TWA2 3
++#define TWA3 4
++#define TWA4 5
++#define TWA5 6
++#define TWA6 7
++
++#define TWDR _SFR_MEM8(0xBB)
++
++#define TWCR _SFR_MEM8(0xBC)
++#define TWIE 0
++#define TWEN 2
++#define TWWC 3
++#define TWSTO 4
++#define TWSTA 5
++#define TWEA 6
++#define TWINT 7
++
++#define TWAMR _SFR_MEM8(0xBD)
++#define TWAM0 1
++#define TWAM1 2
++#define TWAM2 3
++#define TWAM3 4
++#define TWAM4 5
++#define TWAM5 6
++#define TWAM6 7
++
++#define IRQ_MASK1 _SFR_MEM8(0xBE)
++#define TX_START_EN 0
++#define MAF_0_AMI_EN 1
++#define MAF_1_AMI_EN 2
++#define MAF_2_AMI_EN 3
++#define MAF_3_AMI_EN 4
++
++#define IRQ_STATUS1 _SFR_MEM8(0xBF)
++#define TX_START 0
++#define MAF_0_AMI 1
++#define MAF_1_AMI 2
++#define MAF_2_AMI 3
++#define MAF_3_AMI 4
++
++#define UCSR0A _SFR_MEM8(0xC0)
++#define MPCM0 0
++#define U2X0 1
++#define UPE0 2
++#define DOR0 3
++#define FE0 4
++#define UDRE0 5
++#define TXC0 6
++#define RXC0 7
++
++#define UCSR0B _SFR_MEM8(0xC1)
++#define TXB80 0
++#define RXB80 1
++#define UCSZ02 2
++#define TXEN0 3
++#define RXEN0 4
++#define UDRIE0 5
++#define TXCIE0 6
++#define RXCIE0 7
++
++#define UCSR0C _SFR_MEM8(0xC2)
++#define UCPOL0 0
++#define UCSZ00 1
++#define UCSZ01 2
++#define USBS0 3
++#define UPM00 4
++#define UPM01 5
++#define UMSEL00 6
++#define UMSEL01 7
++#define UCPHA0 1
++#define UDORD0 2
++
++/* Reserved [0xC3] */
++
++/* Combine UBRR0L and UBRR0H */
++#define UBRR0 _SFR_MEM16(0xC4)
++
++#define UBRR0L _SFR_MEM8(0xC4)
++#define UBRR0H _SFR_MEM8(0xC5)
++
++#define UDR0 _SFR_MEM8(0xC6)
++
++/* Reserved [0xC7] */
++
++#define UCSR1A _SFR_MEM8(0xC8)
++#define MPCM1 0
++#define U2X1 1
++#define UPE1 2
++#define DOR1 3
++#define FE1 4
++#define UDRE1 5
++#define TXC1 6
++#define RXC1 7
++
++#define UCSR1B _SFR_MEM8(0xC9)
++#define TXB81 0
++#define RXB81 1
++#define UCSZ12 2
++#define TXEN1 3
++#define RXEN1 4
++#define UDRIE1 5
++#define TXCIE1 6
++#define RXCIE1 7
++
++#define UCSR1C _SFR_MEM8(0xCA)
++#define UCPOL1 0
++#define UCSZ10 1
++#define UCSZ11 2
++#define USBS1 3
++#define UPM10 4
++#define UPM11 5
++#define UMSEL10 6
++#define UMSEL11 7
++#define UCPHA1 1
++#define UDORD1 2
++
++/* Reserved [0xCB] */
++
++/* Combine UBRR1L and UBRR1H */
++#define UBRR1 _SFR_MEM16(0xCC)
++
++#define UBRR1L _SFR_MEM8(0xCC)
++#define UBRR1H _SFR_MEM8(0xCD)
++
++#define UDR1 _SFR_MEM8(0xCE)
++
++/* Reserved [0xCF..0xD6] */
++
++#define SCRSTRLL _SFR_MEM8(0xD7)
++#define SCRSTRLL0 0
++#define SCRSTRLL1 1
++#define SCRSTRLL2 2
++#define SCRSTRLL3 3
++#define SCRSTRLL4 4
++#define SCRSTRLL5 5
++#define SCRSTRLL6 6
++#define SCRSTRLL7 7
++
++#define SCRSTRLH _SFR_MEM8(0xD8)
++#define SCRSTRLH0 0
++#define SCRSTRLH1 1
++#define SCRSTRLH2 2
++#define SCRSTRLH3 3
++#define SCRSTRLH4 4
++#define SCRSTRLH5 5
++#define SCRSTRLH6 6
++#define SCRSTRLH7 7
++
++#define SCRSTRHL _SFR_MEM8(0xD9)
++#define SCRSTRHL0 0
++#define SCRSTRHL1 1
++#define SCRSTRHL2 2
++#define SCRSTRHL3 3
++#define SCRSTRHL4 4
++#define SCRSTRHL5 5
++#define SCRSTRHL6 6
++#define SCRSTRHL7 7
++
++#define SCRSTRHH _SFR_MEM8(0xDA)
++#define SCRSTRHH0 0
++#define SCRSTRHH1 1
++#define SCRSTRHH2 2
++#define SCRSTRHH3 3
++#define SCRSTRHH4 4
++#define SCRSTRHH5 5
++#define SCRSTRHH6 6
++#define SCRSTRHH7 7
++
++#define SCCSR _SFR_MEM8(0xDB)
++#define SCCS10 0
++#define SCCS11 1
++#define SCCS20 2
++#define SCCS21 3
++#define SCCS30 4
++#define SCCS31 5
++
++#define SCCR0 _SFR_MEM8(0xDC)
++#define SCCMP1 0
++#define SCCMP2 1
++#define SCCMP3 2
++#define SCTSE 3
++#define SCCKSEL 4
++#define SCEN 5
++#define SCMBTS 6
++#define SCRES 7
++
++#define SCCR1 _SFR_MEM8(0xDD)
++#define SCENBO 0
++#define SCEECLK 1
++#define SCCKDIV0 2
++#define SCCKDIV1 3
++#define SCCKDIV2 4
++#define SCBTSM 5
++#define Res5 6
++#define Res6 7
++
++#define SCSR _SFR_MEM8(0xDE)
++#define SCBSY 0
++
++#define SCIRQM _SFR_MEM8(0xDF)
++#define IRQMCP1 0
++#define IRQMCP2 1
++#define IRQMCP3 2
++#define IRQMOF 3
++#define IRQMBO 4
++
++#define SCIRQS _SFR_MEM8(0xE0)
++#define IRQSCP1 0
++#define IRQSCP2 1
++#define IRQSCP3 2
++#define IRQSOF 3
++#define IRQSBO 4
++
++#define SCCNTLL _SFR_MEM8(0xE1)
++#define SCCNTLL0 0
++#define SCCNTLL1 1
++#define SCCNTLL2 2
++#define SCCNTLL3 3
++#define SCCNTLL4 4
++#define SCCNTLL5 5
++#define SCCNTLL6 6
++#define SCCNTLL7 7
++
++#define SCCNTLH _SFR_MEM8(0xE2)
++#define SCCNTLH0 0
++#define SCCNTLH1 1
++#define SCCNTLH2 2
++#define SCCNTLH3 3
++#define SCCNTLH4 4
++#define SCCNTLH5 5
++#define SCCNTLH6 6
++#define SCCNTLH7 7
++
++#define SCCNTHL _SFR_MEM8(0xE3)
++#define SCCNTHL0 0
++#define SCCNTHL1 1
++#define SCCNTHL2 2
++#define SCCNTHL3 3
++#define SCCNTHL4 4
++#define SCCNTHL5 5
++#define SCCNTHL6 6
++#define SCCNTHL7 7
++
++#define SCCNTHH _SFR_MEM8(0xE4)
++#define SCCNTHH0 0
++#define SCCNTHH1 1
++#define SCCNTHH2 2
++#define SCCNTHH3 3
++#define SCCNTHH4 4
++#define SCCNTHH5 5
++#define SCCNTHH6 6
++#define SCCNTHH7 7
++
++#define SCBTSRLL _SFR_MEM8(0xE5)
++#define SCBTSRLL0 0
++#define SCBTSRLL1 1
++#define SCBTSRLL2 2
++#define SCBTSRLL3 3
++#define SCBTSRLL4 4
++#define SCBTSRLL5 5
++#define SCBTSRLL6 6
++#define SCBTSRLL7 7
++
++#define SCBTSRLH _SFR_MEM8(0xE6)
++#define SCBTSRLH0 0
++#define SCBTSRLH1 1
++#define SCBTSRLH2 2
++#define SCBTSRLH3 3
++#define SCBTSRLH4 4
++#define SCBTSRLH5 5
++#define SCBTSRLH6 6
++#define SCBTSRLH7 7
++
++#define SCBTSRHL _SFR_MEM8(0xE7)
++#define SCBTSRHL0 0
++#define SCBTSRHL1 1
++#define SCBTSRHL2 2
++#define SCBTSRHL3 3
++#define SCBTSRHL4 4
++#define SCBTSRHL5 5
++#define SCBTSRHL6 6
++#define SCBTSRHL7 7
++
++#define SCBTSRHH _SFR_MEM8(0xE8)
++#define SCBTSRHH0 0
++#define SCBTSRHH1 1
++#define SCBTSRHH2 2
++#define SCBTSRHH3 3
++#define SCBTSRHH4 4
++#define SCBTSRHH5 5
++#define SCBTSRHH6 6
++#define SCBTSRHH7 7
++
++#define SCTSRLL _SFR_MEM8(0xE9)
++#define SCTSRLL0 0
++#define SCTSRLL1 1
++#define SCTSRLL2 2
++#define SCTSRLL3 3
++#define SCTSRLL4 4
++#define SCTSRLL5 5
++#define SCTSRLL6 6
++#define SCTSRLL7 7
++
++#define SCTSRLH _SFR_MEM8(0xEA)
++#define SCTSRLH0 0
++#define SCTSRLH1 1
++#define SCTSRLH2 2
++#define SCTSRLH3 3
++#define SCTSRLH4 4
++#define SCTSRLH5 5
++#define SCTSRLH6 6
++#define SCTSRLH7 7
++
++#define SCTSRHL _SFR_MEM8(0xEB)
++#define SCTSRHL0 0
++#define SCTSRHL1 1
++#define SCTSRHL2 2
++#define SCTSRHL3 3
++#define SCTSRHL4 4
++#define SCTSRHL5 5
++#define SCTSRHL6 6
++#define SCTSRHL7 7
++
++#define SCTSRHH _SFR_MEM8(0xEC)
++#define SCTSRHH0 0
++#define SCTSRHH1 1
++#define SCTSRHH2 2
++#define SCTSRHH3 3
++#define SCTSRHH4 4
++#define SCTSRHH5 5
++#define SCTSRHH6 6
++#define SCTSRHH7 7
++
++#define SCOCR3LL _SFR_MEM8(0xED)
++#define SCOCR3LL0 0
++#define SCOCR3LL1 1
++#define SCOCR3LL2 2
++#define SCOCR3LL3 3
++#define SCOCR3LL4 4
++#define SCOCR3LL5 5
++#define SCOCR3LL6 6
++#define SCOCR3LL7 7
++
++#define SCOCR3LH _SFR_MEM8(0xEE)
++#define SCOCR3LH0 0
++#define SCOCR3LH1 1
++#define SCOCR3LH2 2
++#define SCOCR3LH3 3
++#define SCOCR3LH4 4
++#define SCOCR3LH5 5
++#define SCOCR3LH6 6
++#define SCOCR3LH7 7
++
++#define SCOCR3HL _SFR_MEM8(0xEF)
++#define SCOCR3HL0 0
++#define SCOCR3HL1 1
++#define SCOCR3HL2 2
++#define SCOCR3HL3 3
++#define SCOCR3HL4 4
++#define SCOCR3HL5 5
++#define SCOCR3HL6 6
++#define SCOCR3HL7 7
++
++#define SCOCR3HH _SFR_MEM8(0xF0)
++#define SCOCR3HH0 0
++#define SCOCR3HH1 1
++#define SCOCR3HH2 2
++#define SCOCR3HH3 3
++#define SCOCR3HH4 4
++#define SCOCR3HH5 5
++#define SCOCR3HH6 6
++#define SCOCR3HH7 7
++
++#define SCOCR2LL _SFR_MEM8(0xF1)
++#define SCOCR2LL0 0
++#define SCOCR2LL1 1
++#define SCOCR2LL2 2
++#define SCOCR2LL3 3
++#define SCOCR2LL4 4
++#define SCOCR2LL5 5
++#define SCOCR2LL6 6
++#define SCOCR2LL7 7
++
++#define SCOCR2LH _SFR_MEM8(0xF2)
++#define SCOCR2LH0 0
++#define SCOCR2LH1 1
++#define SCOCR2LH2 2
++#define SCOCR2LH3 3
++#define SCOCR2LH4 4
++#define SCOCR2LH5 5
++#define SCOCR2LH6 6
++#define SCOCR2LH7 7
++
++#define SCOCR2HL _SFR_MEM8(0xF3)
++#define SCOCR2HL0 0
++#define SCOCR2HL1 1
++#define SCOCR2HL2 2
++#define SCOCR2HL3 3
++#define SCOCR2HL4 4
++#define SCOCR2HL5 5
++#define SCOCR2HL6 6
++#define SCOCR2HL7 7
++
++#define SCOCR2HH _SFR_MEM8(0xF4)
++#define SCOCR2HH0 0
++#define SCOCR2HH1 1
++#define SCOCR2HH2 2
++#define SCOCR2HH3 3
++#define SCOCR2HH4 4
++#define SCOCR2HH5 5
++#define SCOCR2HH6 6
++#define SCOCR2HH7 7
++
++#define SCOCR1LL _SFR_MEM8(0xF5)
++#define SCOCR1LL0 0
++#define SCOCR1LL1 1
++#define SCOCR1LL2 2
++#define SCOCR1LL3 3
++#define SCOCR1LL4 4
++#define SCOCR1LL5 5
++#define SCOCR1LL6 6
++#define SCOCR1LL7 7
++
++#define SCOCR1LH _SFR_MEM8(0xF6)
++#define SCOCR1LH0 0
++#define SCOCR1LH1 1
++#define SCOCR1LH2 2
++#define SCOCR1LH3 3
++#define SCOCR1LH4 4
++#define SCOCR1LH5 5
++#define SCOCR1LH6 6
++#define SCOCR1LH7 7
++
++#define SCOCR1HL _SFR_MEM8(0xF7)
++#define SCOCR1HL0 0
++#define SCOCR1HL1 1
++#define SCOCR1HL2 2
++#define SCOCR1HL3 3
++#define SCOCR1HL4 4
++#define SCOCR1HL5 5
++#define SCOCR1HL6 6
++#define SCOCR1HL7 7
++
++#define SCOCR1HH _SFR_MEM8(0xF8)
++#define SCOCR1HH0 0
++#define SCOCR1HH1 1
++#define SCOCR1HH2 2
++#define SCOCR1HH3 3
++#define SCOCR1HH4 4
++#define SCOCR1HH5 5
++#define SCOCR1HH6 6
++#define SCOCR1HH7 7
++
++#define SCTSTRLL _SFR_MEM8(0xF9)
++#define SCTSTRLL0 0
++#define SCTSTRLL1 1
++#define SCTSTRLL2 2
++#define SCTSTRLL3 3
++#define SCTSTRLL4 4
++#define SCTSTRLL5 5
++#define SCTSTRLL6 6
++#define SCTSTRLL7 7
++
++#define SCTSTRLH _SFR_MEM8(0xFA)
++#define SCTSTRLH0 0
++#define SCTSTRLH1 1
++#define SCTSTRLH2 2
++#define SCTSTRLH3 3
++#define SCTSTRLH4 4
++#define SCTSTRLH5 5
++#define SCTSTRLH6 6
++#define SCTSTRLH7 7
++
++#define SCTSTRHL _SFR_MEM8(0xFB)
++#define SCTSTRHL0 0
++#define SCTSTRHL1 1
++#define SCTSTRHL2 2
++#define SCTSTRHL3 3
++#define SCTSTRHL4 4
++#define SCTSTRHL5 5
++#define SCTSTRHL6 6
++#define SCTSTRHL7 7
++
++#define SCTSTRHH _SFR_MEM8(0xFC)
++#define SCTSTRHH0 0
++#define SCTSTRHH1 1
++#define SCTSTRHH2 2
++#define SCTSTRHH3 3
++#define SCTSTRHH4 4
++#define SCTSTRHH5 5
++#define SCTSTRHH6 6
++#define SCTSTRHH7 7
++
++/* Reserved [0xFD..0x10B] */
++
++#define MAFCR0 _SFR_MEM8(0x10C)
++#define MAF0EN 0
++#define MAF1EN 1
++#define MAF2EN 2
++#define MAF3EN 3
++
++#define MAFCR1 _SFR_MEM8(0x10D)
++#define AACK_0_I_AM_COORD 0
++#define AACK_0_SET_PD 1
++#define AACK_1_I_AM_COORD 2
++#define AACK_1_SET_PD 3
++#define AACK_2_I_AM_COORD 4
++#define AACK_2_SET_PD 5
++#define AACK_3_I_AM_COORD 6
++#define AACK_3_SET_PD 7
++
++#define MAFSA0L _SFR_MEM8(0x10E)
++#define MAFSA0L0 0
++#define MAFSA0L1 1
++#define MAFSA0L2 2
++#define MAFSA0L3 3
++#define MAFSA0L4 4
++#define MAFSA0L5 5
++#define MAFSA0L6 6
++#define MAFSA0L7 7
++
++#define MAFSA0H _SFR_MEM8(0x10F)
++#define MAFSA0H0 0
++#define MAFSA0H1 1
++#define MAFSA0H2 2
++#define MAFSA0H3 3
++#define MAFSA0H4 4
++#define MAFSA0H5 5
++#define MAFSA0H6 6
++#define MAFSA0H7 7
++
++#define MAFPA0L _SFR_MEM8(0x110)
++#define MAFPA0L0 0
++#define MAFPA0L1 1
++#define MAFPA0L2 2
++#define MAFPA0L3 3
++#define MAFPA0L4 4
++#define MAFPA0L5 5
++#define MAFPA0L6 6
++#define MAFPA0L7 7
++
++#define MAFPA0H _SFR_MEM8(0x111)
++#define MAFPA0H0 0
++#define MAFPA0H1 1
++#define MAFPA0H2 2
++#define MAFPA0H3 3
++#define MAFPA0H4 4
++#define MAFPA0H5 5
++#define MAFPA0H6 6
++#define MAFPA0H7 7
++
++#define MAFSA1L _SFR_MEM8(0x112)
++#define MAFSA1L0 0
++#define MAFSA1L1 1
++#define MAFSA1L2 2
++#define MAFSA1L3 3
++#define MAFSA1L4 4
++#define MAFSA1L5 5
++#define MAFSA1L6 6
++#define MAFSA1L7 7
++
++#define MAFSA1H _SFR_MEM8(0x113)
++#define MAFSA1H0 0
++#define MAFSA1H1 1
++#define MAFSA1H2 2
++#define MAFSA1H3 3
++#define MAFSA1H4 4
++#define MAFSA1H5 5
++#define MAFSA1H6 6
++#define MAFSA1H7 7
++
++#define MAFPA1L _SFR_MEM8(0x114)
++#define MAFPA1L0 0
++#define MAFPA1L1 1
++#define MAFPA1L2 2
++#define MAFPA1L3 3
++#define MAFPA1L4 4
++#define MAFPA1L5 5
++#define MAFPA1L6 6
++#define MAFPA1L7 7
++
++#define MAFPA1H _SFR_MEM8(0x115)
++#define MAFPA1H0 0
++#define MAFPA1H1 1
++#define MAFPA1H2 2
++#define MAFPA1H3 3
++#define MAFPA1H4 4
++#define MAFPA1H5 5
++#define MAFPA1H6 6
++#define MAFPA1H7 7
++
++#define MAFSA2L _SFR_MEM8(0x116)
++#define MAFSA2L0 0
++#define MAFSA2L1 1
++#define MAFSA2L2 2
++#define MAFSA2L3 3
++#define MAFSA2L4 4
++#define MAFSA2L5 5
++#define MAFSA2L6 6
++#define MAFSA2L7 7
++
++#define MAFSA2H _SFR_MEM8(0x117)
++#define MAFSA2H0 0
++#define MAFSA2H1 1
++#define MAFSA2H2 2
++#define MAFSA2H3 3
++#define MAFSA2H4 4
++#define MAFSA2H5 5
++#define MAFSA2H6 6
++#define MAFSA2H7 7
++
++#define MAFPA2L _SFR_MEM8(0x118)
++#define MAFPA2L0 0
++#define MAFPA2L1 1
++#define MAFPA2L2 2
++#define MAFPA2L3 3
++#define MAFPA2L4 4
++#define MAFPA2L5 5
++#define MAFPA2L6 6
++#define MAFPA2L7 7
++
++#define MAFPA2H _SFR_MEM8(0x119)
++#define MAFPA2H0 0
++#define MAFPA2H1 1
++#define MAFPA2H2 2
++#define MAFPA2H3 3
++#define MAFPA2H4 4
++#define MAFPA2H5 5
++#define MAFPA2H6 6
++#define MAFPA2H7 7
++
++#define MAFSA3L _SFR_MEM8(0x11A)
++#define MAFSA3L0 0
++#define MAFSA3L1 1
++#define MAFSA3L2 2
++#define MAFSA3L3 3
++#define MAFSA3L4 4
++#define MAFSA3L5 5
++#define MAFSA3L6 6
++#define MAFSA3L7 7
++
++#define MAFSA3H _SFR_MEM8(0x11B)
++#define MAFSA3H0 0
++#define MAFSA3H1 1
++#define MAFSA3H2 2
++#define MAFSA3H3 3
++#define MAFSA3H4 4
++#define MAFSA3H5 5
++#define MAFSA3H6 6
++#define MAFSA3H7 7
++
++#define MAFPA3L _SFR_MEM8(0x11C)
++#define MAFPA3L0 0
++#define MAFPA3L1 1
++#define MAFPA3L2 2
++#define MAFPA3L3 3
++#define MAFPA3L4 4
++#define MAFPA3L5 5
++#define MAFPA3L6 6
++#define MAFPA3L7 7
++
++#define MAFPA3H _SFR_MEM8(0x11D)
++#define MAFPA3H0 0
++#define MAFPA3H1 1
++#define MAFPA3H2 2
++#define MAFPA3H3 3
++#define MAFPA3H4 4
++#define MAFPA3H5 5
++#define MAFPA3H6 6
++#define MAFPA3H7 7
++
++/* Reserved [0x11E..0x11F] */
++
++#define TCCR5A _SFR_MEM8(0x120)
++#define WGM50 0
++#define WGM51 1
++#define COM5C0 2
++#define COM5C1 3
++#define COM5B0 4
++#define COM5B1 5
++#define COM5A0 6
++#define COM5A1 7
++
++#define TCCR5B _SFR_MEM8(0x121)
++#define CS50 0
++#define CS51 1
++#define CS52 2
++#define WGM52 3
++#define WGM53 4
++#define ICES5 6
++#define ICNC5 7
++
++#define TCCR5C _SFR_MEM8(0x122)
++#define FOC5C 5
++#define FOC5B 6
++#define FOC5A 7
++
++/* Reserved [0x123] */
++
++/* Combine TCNT5L and TCNT5H */
++#define TCNT5 _SFR_MEM16(0x124)
++
++#define TCNT5L _SFR_MEM8(0x124)
++#define TCNT5H _SFR_MEM8(0x125)
++
++/* Combine ICR5L and ICR5H */
++#define ICR5 _SFR_MEM16(0x126)
++
++#define ICR5L _SFR_MEM8(0x126)
++#define ICR5H _SFR_MEM8(0x127)
++
++/* Combine OCR5AL and OCR5AH */
++#define OCR5A _SFR_MEM16(0x128)
++
++#define OCR5AL _SFR_MEM8(0x128)
++#define OCR5AH _SFR_MEM8(0x129)
++
++/* Combine OCR5BL and OCR5BH */
++#define OCR5B _SFR_MEM16(0x12A)
++
++#define OCR5BL _SFR_MEM8(0x12A)
++#define OCR5BH _SFR_MEM8(0x12B)
++
++/* Combine OCR5CL and OCR5CH */
++#define OCR5C _SFR_MEM16(0x12C)
++
++#define OCR5CL _SFR_MEM8(0x12C)
++#define OCR5CH _SFR_MEM8(0x12D)
++
++/* Reserved [0x12E] */
++
++#define LLCR _SFR_MEM8(0x12F)
++#define LLENCAL 0
++#define LLSHORT 1
++#define LLTCO 2
++#define LLCAL 3
++#define LLCOMP 4
++#define LLDONE 5
++
++#define LLDRL _SFR_MEM8(0x130)
++#define LLDRL0 0
++#define LLDRL1 1
++#define LLDRL2 2
++#define LLDRL3 3
++
++#define LLDRH _SFR_MEM8(0x131)
++#define LLDRH0 0
++#define LLDRH1 1
++#define LLDRH2 2
++#define LLDRH3 3
++#define LLDRH4 4
++
++#define DRTRAM3 _SFR_MEM8(0x132)
++#define ENDRT 4
++#define DRTSWOK 5
++
++#define DRTRAM2 _SFR_MEM8(0x133)
++
++#define DRTRAM1 _SFR_MEM8(0x134)
++
++#define DRTRAM0 _SFR_MEM8(0x135)
++
++#define DPDS0 _SFR_MEM8(0x136)
++#define PBDRV0 0
++#define PBDRV1 1
++#define PDDRV0 2
++#define PDDRV1 3
++#define PEDRV0 4
++#define PEDRV1 5
++#define PFDRV0 6
++#define PFDRV1 7
++
++#define DPDS1 _SFR_MEM8(0x137)
++#define PGDRV0 0
++#define PGDRV1 1
++
++#define PARCR _SFR_MEM8(0x138)
++#define PARUFI 0
++#define PARDFI 1
++#define PALTU0 2
++#define PALTU1 3
++#define PALTU2 4
++#define PALTD0 5
++#define PALTD1 6
++#define PALTD2 7
++
++#define TRXPR _SFR_MEM8(0x139)
++#define TRXRST 0
++#define SLPTR 1
++
++/* Reserved [0x13A..0x13B] */
++
++#define AES_CTRL _SFR_MEM8(0x13C)
++#define AES_IM 2
++#define AES_DIR 3
++#define AES_MODE 5
++#define AES_REQUEST 7
++
++#define AES_STATUS _SFR_MEM8(0x13D)
++#define AES_DONE 0
++#define AES_ER 7
++
++#define AES_STATE _SFR_MEM8(0x13E)
++#define AES_STATE0 0
++#define AES_STATE1 1
++#define AES_STATE2 2
++#define AES_STATE3 3
++#define AES_STATE4 4
++#define AES_STATE5 5
++#define AES_STATE6 6
++#define AES_STATE7 7
++
++#define AES_KEY _SFR_MEM8(0x13F)
++#define AES_KEY0 0
++#define AES_KEY1 1
++#define AES_KEY2 2
++#define AES_KEY3 3
++#define AES_KEY4 4
++#define AES_KEY5 5
++#define AES_KEY6 6
++#define AES_KEY7 7
++
++/* Reserved [0x140] */
++
++#define TRX_STATUS _SFR_MEM8(0x141)
++#define TRX_STATUS0 0
++#define TRX_STATUS1 1
++#define TRX_STATUS2 2
++#define TRX_STATUS3 3
++#define TRX_STATUS4 4
++#define TST_STATUS 5
++#define CCA_STATUS 6
++#define CCA_DONE 7
++
++#define TRX_STATE _SFR_MEM8(0x142)
++#define TRX_CMD0 0
++#define TRX_CMD1 1
++#define TRX_CMD2 2
++#define TRX_CMD3 3
++#define TRX_CMD4 4
++#define TRAC_STATUS0 5
++#define TRAC_STATUS1 6
++#define TRAC_STATUS2 7
++
++#define TRX_CTRL_0 _SFR_MEM8(0x143)
++#define PMU_IF_INV 4
++#define PMU_START 5
++#define PMU_EN 6
++#define Res7 7
++
++#define TRX_CTRL_1 _SFR_MEM8(0x144)
++#define PLL_TX_FLT 4
++#define TX_AUTO_CRC_ON 5
++#define IRQ_2_EXT_EN 6
++#define PA_EXT_EN 7
++
++#define PHY_TX_PWR _SFR_MEM8(0x145)
++#define TX_PWR0 0
++#define TX_PWR1 1
++#define TX_PWR2 2
++#define TX_PWR3 3
++
++#define PHY_RSSI _SFR_MEM8(0x146)
++#define RSSI0 0
++#define RSSI1 1
++#define RSSI2 2
++#define RSSI3 3
++#define RSSI4 4
++#define RND_VALUE0 5
++#define RND_VALUE1 6
++#define RX_CRC_VALID 7
++
++#define PHY_ED_LEVEL _SFR_MEM8(0x147)
++#define ED_LEVEL0 0
++#define ED_LEVEL1 1
++#define ED_LEVEL2 2
++#define ED_LEVEL3 3
++#define ED_LEVEL4 4
++#define ED_LEVEL5 5
++#define ED_LEVEL6 6
++#define ED_LEVEL7 7
++
++#define PHY_CC_CCA _SFR_MEM8(0x148)
++#define CHANNEL0 0
++#define CHANNEL1 1
++#define CHANNEL2 2
++#define CHANNEL3 3
++#define CHANNEL4 4
++#define CCA_MODE0 5
++#define CCA_MODE1 6
++#define CCA_REQUEST 7
++
++#define CCA_THRES _SFR_MEM8(0x149)
++#define CCA_ED_THRES0 0
++#define CCA_ED_THRES1 1
++#define CCA_ED_THRES2 2
++#define CCA_ED_THRES3 3
++#define CCA_CS_THRES0 4
++#define CCA_CS_THRES1 5
++#define CCA_CS_THRES2 6
++#define CCA_CS_THRES3 7
++
++#define RX_CTRL _SFR_MEM8(0x14A)
++#define PDT_THRES0 0
++#define PDT_THRES1 1
++#define PDT_THRES2 2
++#define PDT_THRES3 3
++
++#define SFD_VALUE _SFR_MEM8(0x14B)
++#define SFD_VALUE0 0
++#define SFD_VALUE1 1
++#define SFD_VALUE2 2
++#define SFD_VALUE3 3
++#define SFD_VALUE4 4
++#define SFD_VALUE5 5
++#define SFD_VALUE6 6
++#define SFD_VALUE7 7
++
++#define TRX_CTRL_2 _SFR_MEM8(0x14C)
++#define OQPSK_DATA_RATE0 0
++#define OQPSK_DATA_RATE1 1
++#define RX_SAFE_MODE 7
++
++#define ANT_DIV _SFR_MEM8(0x14D)
++#define ANT_CTRL0 0
++#define ANT_CTRL1 1
++#define ANT_EXT_SW_EN 2
++#define ANT_DIV_EN 3
++#define ANT_SEL 7
++
++#define IRQ_MASK _SFR_MEM8(0x14E)
++#define PLL_LOCK_EN 0
++#define PLL_UNLOCK_EN 1
++#define RX_START_EN 2
++#define RX_END_EN 3
++#define CCA_ED_DONE_EN 4
++#define AMI_EN 5
++#define TX_END_EN 6
++#define AWAKE_EN 7
++
++#define IRQ_STATUS _SFR_MEM8(0x14F)
++#define PLL_LOCK 0
++#define PLL_UNLOCK 1
++#define RX_START 2
++#define RX_END 3
++#define CCA_ED_DONE 4
++#define AMI 5
++#define TX_END 6
++#define AWAKE 7
++
++#define VREG_CTRL _SFR_MEM8(0x150)
++#define DVDD_OK 2
++#define DVREG_EXT 3
++#define AVDD_OK 6
++#define AVREG_EXT 7
++
++#define BATMON _SFR_MEM8(0x151)
++#define BATMON_VTH0 0
++#define BATMON_VTH1 1
++#define BATMON_VTH2 2
++#define BATMON_VTH3 3
++#define BATMON_HR 4
++#define BATMON_OK 5
++#define BAT_LOW_EN 6
++#define BAT_LOW 7
++
++#define XOSC_CTRL _SFR_MEM8(0x152)
++#define XTAL_TRIM0 0
++#define XTAL_TRIM1 1
++#define XTAL_TRIM2 2
++#define XTAL_TRIM3 3
++#define XTAL_MODE0 4
++#define XTAL_MODE1 5
++#define XTAL_MODE2 6
++#define XTAL_MODE3 7
++
++#define CC_CTRL_0 _SFR_MEM8(0x153)
++#define CC_NUMBER0 0
++#define CC_NUMBER1 1
++#define CC_NUMBER2 2
++#define CC_NUMBER3 3
++#define CC_NUMBER4 4
++#define CC_NUMBER5 5
++#define CC_NUMBER6 6
++#define CC_NUMBER7 7
++
++#define CC_CTRL_1 _SFR_MEM8(0x154)
++#define CC_BAND0 0
++#define CC_BAND1 1
++#define CC_BAND2 2
++#define CC_BAND3 3
++
++#define RX_SYN _SFR_MEM8(0x155)
++#define RX_PDT_LEVEL0 0
++#define RX_PDT_LEVEL1 1
++#define RX_PDT_LEVEL2 2
++#define RX_PDT_LEVEL3 3
++#define RX_OVERRIDE 6
++#define RX_PDT_DIS 7
++
++#define TRX_RPC _SFR_MEM8(0x156)
++#define XAH_RPC_EN 0
++#define IPAN_RPC_EN 1
++#define PLL_RPC_EN 3
++#define PDT_RPC_EN 4
++#define RX_RPC_EN 5
++#define RX_RPC_CTRL0 6
++#define RX_RPC_CTRL1 7
++
++#define XAH_CTRL_1 _SFR_MEM8(0x157)
++#define AACK_PROM_MODE 1
++#define AACK_ACK_TIME 2
++#define AACK_UPLD_RES_FT 4
++#define AACK_FLTR_RES_FT 5
++
++#define FTN_CTRL _SFR_MEM8(0x158)
++#define FTN_START 7
++
++/* Reserved [0x159] */
++
++#define PLL_CF _SFR_MEM8(0x15A)
++#define PLL_CF_START 7
++
++#define PLL_DCU _SFR_MEM8(0x15B)
++#define PLL_DCU_START 7
++
++#define PART_NUM _SFR_MEM8(0x15C)
++#define PART_NUM0 0
++#define PART_NUM1 1
++#define PART_NUM2 2
++#define PART_NUM3 3
++#define PART_NUM4 4
++#define PART_NUM5 5
++#define PART_NUM6 6
++#define PART_NUM7 7
++
++#define VERSION_NUM _SFR_MEM8(0x15D)
++#define VERSION_NUM0 0
++#define VERSION_NUM1 1
++#define VERSION_NUM2 2
++#define VERSION_NUM3 3
++#define VERSION_NUM4 4
++#define VERSION_NUM5 5
++#define VERSION_NUM6 6
++#define VERSION_NUM7 7
++
++#define MAN_ID_0 _SFR_MEM8(0x15E)
++#define MAN_ID_00 0
++#define MAN_ID_01 1
++#define MAN_ID_02 2
++#define MAN_ID_03 3
++#define MAN_ID_04 4
++#define MAN_ID_05 5
++#define MAN_ID_06 6
++#define MAN_ID_07 7
++
++#define MAN_ID_1 _SFR_MEM8(0x15F)
++#define MAN_ID_10 0
++#define MAN_ID_11 1
++#define MAN_ID_12 2
++#define MAN_ID_13 3
++#define MAN_ID_14 4
++#define MAN_ID_15 5
++#define MAN_ID_16 6
++#define MAN_ID_17 7
++
++#define SHORT_ADDR_0 _SFR_MEM8(0x160)
++#define SHORT_ADDR_00 0
++#define SHORT_ADDR_01 1
++#define SHORT_ADDR_02 2
++#define SHORT_ADDR_03 3
++#define SHORT_ADDR_04 4
++#define SHORT_ADDR_05 5
++#define SHORT_ADDR_06 6
++#define SHORT_ADDR_07 7
++
++#define SHORT_ADDR_1 _SFR_MEM8(0x161)
++#define SHORT_ADDR_10 0
++#define SHORT_ADDR_11 1
++#define SHORT_ADDR_12 2
++#define SHORT_ADDR_13 3
++#define SHORT_ADDR_14 4
++#define SHORT_ADDR_15 5
++#define SHORT_ADDR_16 6
++#define SHORT_ADDR_17 7
++
++#define PAN_ID_0 _SFR_MEM8(0x162)
++#define PAN_ID_00 0
++#define PAN_ID_01 1
++#define PAN_ID_02 2
++#define PAN_ID_03 3
++#define PAN_ID_04 4
++#define PAN_ID_05 5
++#define PAN_ID_06 6
++#define PAN_ID_07 7
++
++#define PAN_ID_1 _SFR_MEM8(0x163)
++#define PAN_ID_10 0
++#define PAN_ID_11 1
++#define PAN_ID_12 2
++#define PAN_ID_13 3
++#define PAN_ID_14 4
++#define PAN_ID_15 5
++#define PAN_ID_16 6
++#define PAN_ID_17 7
++
++#define IEEE_ADDR_0 _SFR_MEM8(0x164)
++#define IEEE_ADDR_00 0
++#define IEEE_ADDR_01 1
++#define IEEE_ADDR_02 2
++#define IEEE_ADDR_03 3
++#define IEEE_ADDR_04 4
++#define IEEE_ADDR_05 5
++#define IEEE_ADDR_06 6
++#define IEEE_ADDR_07 7
++
++#define IEEE_ADDR_1 _SFR_MEM8(0x165)
++#define IEEE_ADDR_10 0
++#define IEEE_ADDR_11 1
++#define IEEE_ADDR_12 2
++#define IEEE_ADDR_13 3
++#define IEEE_ADDR_14 4
++#define IEEE_ADDR_15 5
++#define IEEE_ADDR_16 6
++#define IEEE_ADDR_17 7
++
++#define IEEE_ADDR_2 _SFR_MEM8(0x166)
++#define IEEE_ADDR_20 0
++#define IEEE_ADDR_21 1
++#define IEEE_ADDR_22 2
++#define IEEE_ADDR_23 3
++#define IEEE_ADDR_24 4
++#define IEEE_ADDR_25 5
++#define IEEE_ADDR_26 6
++#define IEEE_ADDR_27 7
++
++#define IEEE_ADDR_3 _SFR_MEM8(0x167)
++#define IEEE_ADDR_30 0
++#define IEEE_ADDR_31 1
++#define IEEE_ADDR_32 2
++#define IEEE_ADDR_33 3
++#define IEEE_ADDR_34 4
++#define IEEE_ADDR_35 5
++#define IEEE_ADDR_36 6
++#define IEEE_ADDR_37 7
++
++#define IEEE_ADDR_4 _SFR_MEM8(0x168)
++#define IEEE_ADDR_40 0
++#define IEEE_ADDR_41 1
++#define IEEE_ADDR_42 2
++#define IEEE_ADDR_43 3
++#define IEEE_ADDR_44 4
++#define IEEE_ADDR_45 5
++#define IEEE_ADDR_46 6
++#define IEEE_ADDR_47 7
++
++#define IEEE_ADDR_5 _SFR_MEM8(0x169)
++#define IEEE_ADDR_50 0
++#define IEEE_ADDR_51 1
++#define IEEE_ADDR_52 2
++#define IEEE_ADDR_53 3
++#define IEEE_ADDR_54 4
++#define IEEE_ADDR_55 5
++#define IEEE_ADDR_56 6
++#define IEEE_ADDR_57 7
++
++#define IEEE_ADDR_6 _SFR_MEM8(0x16A)
++#define IEEE_ADDR_60 0
++#define IEEE_ADDR_61 1
++#define IEEE_ADDR_62 2
++#define IEEE_ADDR_63 3
++#define IEEE_ADDR_64 4
++#define IEEE_ADDR_65 5
++#define IEEE_ADDR_66 6
++#define IEEE_ADDR_67 7
++
++#define IEEE_ADDR_7 _SFR_MEM8(0x16B)
++#define IEEE_ADDR_70 0
++#define IEEE_ADDR_71 1
++#define IEEE_ADDR_72 2
++#define IEEE_ADDR_73 3
++#define IEEE_ADDR_74 4
++#define IEEE_ADDR_75 5
++#define IEEE_ADDR_76 6
++#define IEEE_ADDR_77 7
++
++#define XAH_CTRL_0 _SFR_MEM8(0x16C)
++#define SLOTTED_OPERATION 0
++#define MAX_CSMA_RETRIES0 1
++#define MAX_CSMA_RETRIES1 2
++#define MAX_CSMA_RETRIES2 3
++#define MAX_FRAME_RETRIES0 4
++#define MAX_FRAME_RETRIES1 5
++#define MAX_FRAME_RETRIES2 6
++#define MAX_FRAME_RETRIES3 7
++
++#define CSMA_SEED_0 _SFR_MEM8(0x16D)
++#define CSMA_SEED_00 0
++#define CSMA_SEED_01 1
++#define CSMA_SEED_02 2
++#define CSMA_SEED_03 3
++#define CSMA_SEED_04 4
++#define CSMA_SEED_05 5
++#define CSMA_SEED_06 6
++#define CSMA_SEED_07 7
++
++#define CSMA_SEED_1 _SFR_MEM8(0x16E)
++#define CSMA_SEED_10 0
++#define CSMA_SEED_11 1
++#define CSMA_SEED_12 2
++#define AACK_I_AM_COORD 3
++#define AACK_DIS_ACK 4
++#define AACK_SET_PD 5
++#define AACK_FVN_MODE0 6
++#define AACK_FVN_MODE1 7
++
++#define CSMA_BE _SFR_MEM8(0x16F)
++#define MIN_BE0 0
++#define MIN_BE1 1
++#define MIN_BE2 2
++#define MIN_BE3 3
++#define MAX_BE0 4
++#define MAX_BE1 5
++#define MAX_BE2 6
++#define MAX_BE3 7
++
++/* Reserved [0x170..0x175] */
++
++#define TST_CTRL_DIGI _SFR_MEM8(0x176)
++#define TST_CTRL_DIG0 0
++#define TST_CTRL_DIG1 1
++#define TST_CTRL_DIG2 2
++#define TST_CTRL_DIG3 3
++
++/* Reserved [0x177..0x17A] */
++
++#define TST_RX_LENGTH _SFR_MEM8(0x17B)
++#define RX_LENGTH0 0
++#define RX_LENGTH1 1
++#define RX_LENGTH2 2
++#define RX_LENGTH3 3
++#define RX_LENGTH4 4
++#define RX_LENGTH5 5
++#define RX_LENGTH6 6
++#define RX_LENGTH7 7
++
++/* Reserved [0x17C..0x17F] */
++
++#define TRXFBST _SFR_MEM8(0x180)
++
++/* Reserved [0x181..0x1FE] */
++
++#define TRXFBEND _SFR_MEM8(0x1FF)
++
++
++
++/* Interrupt vectors */
++/* Vector 0 is the reset vector */
++/* External Interrupt Request 0 */
++#define INT0_vect _VECTOR(1)
++#define INT0_vect_num 1
++
++/* External Interrupt Request 1 */
++#define INT1_vect _VECTOR(2)
++#define INT1_vect_num 2
++
++/* External Interrupt Request 2 */
++#define INT2_vect _VECTOR(3)
++#define INT2_vect_num 3
++
++/* External Interrupt Request 3 */
++#define INT3_vect _VECTOR(4)
++#define INT3_vect_num 4
++
++/* External Interrupt Request 4 */
++#define INT4_vect _VECTOR(5)
++#define INT4_vect_num 5
++
++/* External Interrupt Request 5 */
++#define INT5_vect _VECTOR(6)
++#define INT5_vect_num 6
++
++/* External Interrupt Request 6 */
++#define INT6_vect _VECTOR(7)
++#define INT6_vect_num 7
++
++/* External Interrupt Request 7 */
++#define INT7_vect _VECTOR(8)
++#define INT7_vect_num 8
++
++/* Pin Change Interrupt Request 0 */
++#define PCINT0_vect _VECTOR(9)
++#define PCINT0_vect_num 9
++
++/* Pin Change Interrupt Request 1 */
++#define PCINT1_vect _VECTOR(10)
++#define PCINT1_vect_num 10
++
++/* Pin Change Interrupt Request 2 */
++#define PCINT2_vect _VECTOR(11)
++#define PCINT2_vect_num 11
++
++/* Watchdog Time-out Interrupt */
++#define WDT_vect _VECTOR(12)
++#define WDT_vect_num 12
++
++/* Timer/Counter2 Compare Match A */
++#define TIMER2_COMPA_vect _VECTOR(13)
++#define TIMER2_COMPA_vect_num 13
++
++/* Timer/Counter2 Compare Match B */
++#define TIMER2_COMPB_vect _VECTOR(14)
++#define TIMER2_COMPB_vect_num 14
++
++/* Timer/Counter2 Overflow */
++#define TIMER2_OVF_vect _VECTOR(15)
++#define TIMER2_OVF_vect_num 15
++
++/* Timer/Counter1 Capture Event */
++#define TIMER1_CAPT_vect _VECTOR(16)
++#define TIMER1_CAPT_vect_num 16
++
++/* Timer/Counter1 Compare Match A */
++#define TIMER1_COMPA_vect _VECTOR(17)
++#define TIMER1_COMPA_vect_num 17
++
++/* Timer/Counter1 Compare Match B */
++#define TIMER1_COMPB_vect _VECTOR(18)
++#define TIMER1_COMPB_vect_num 18
++
++/* Timer/Counter1 Compare Match C */
++#define TIMER1_COMPC_vect _VECTOR(19)
++#define TIMER1_COMPC_vect_num 19
++
++/* Timer/Counter1 Overflow */
++#define TIMER1_OVF_vect _VECTOR(20)
++#define TIMER1_OVF_vect_num 20
++
++/* Timer/Counter0 Compare Match A */
++#define TIMER0_COMPA_vect _VECTOR(21)
++#define TIMER0_COMPA_vect_num 21
++
++/* Timer/Counter0 Compare Match B */
++#define TIMER0_COMPB_vect _VECTOR(22)
++#define TIMER0_COMPB_vect_num 22
++
++/* Timer/Counter0 Overflow */
++#define TIMER0_OVF_vect _VECTOR(23)
++#define TIMER0_OVF_vect_num 23
++
++/* SPI Serial Transfer Complete */
++#define SPI_STC_vect _VECTOR(24)
++#define SPI_STC_vect_num 24
++
++/* USART0, Rx Complete */
++#define USART0_RX_vect _VECTOR(25)
++#define USART0_RX_vect_num 25
++
++/* USART0 Data register Empty */
++#define USART0_UDRE_vect _VECTOR(26)
++#define USART0_UDRE_vect_num 26
++
++/* USART0, Tx Complete */
++#define USART0_TX_vect _VECTOR(27)
++#define USART0_TX_vect_num 27
++
++/* Analog Comparator */
++#define ANALOG_COMP_vect _VECTOR(28)
++#define ANALOG_COMP_vect_num 28
++
++/* ADC Conversion Complete */
++#define ADC_vect _VECTOR(29)
++#define ADC_vect_num 29
++
++/* EEPROM Ready */
++#define EE_READY_vect _VECTOR(30)
++#define EE_READY_vect_num 30
++
++/* Timer/Counter3 Capture Event */
++#define TIMER3_CAPT_vect _VECTOR(31)
++#define TIMER3_CAPT_vect_num 31
++
++/* Timer/Counter3 Compare Match A */
++#define TIMER3_COMPA_vect _VECTOR(32)
++#define TIMER3_COMPA_vect_num 32
++
++/* Timer/Counter3 Compare Match B */
++#define TIMER3_COMPB_vect _VECTOR(33)
++#define TIMER3_COMPB_vect_num 33
++
++/* Timer/Counter3 Compare Match C */
++#define TIMER3_COMPC_vect _VECTOR(34)
++#define TIMER3_COMPC_vect_num 34
++
++/* Timer/Counter3 Overflow */
++#define TIMER3_OVF_vect _VECTOR(35)
++#define TIMER3_OVF_vect_num 35
++
++/* USART1, Rx Complete */
++#define USART1_RX_vect _VECTOR(36)
++#define USART1_RX_vect_num 36
++
++/* USART1 Data register Empty */
++#define USART1_UDRE_vect _VECTOR(37)
++#define USART1_UDRE_vect_num 37
++
++/* USART1, Tx Complete */
++#define USART1_TX_vect _VECTOR(38)
++#define USART1_TX_vect_num 38
++
++/* 2-wire Serial Interface */
++#define TWI_vect _VECTOR(39)
++#define TWI_vect_num 39
++
++/* Store Program Memory Read */
++#define SPM_READY_vect _VECTOR(40)
++#define SPM_READY_vect_num 40
++
++/* Timer/Counter4 Capture Event */
++#define TIMER4_CAPT_vect _VECTOR(41)
++#define TIMER4_CAPT_vect_num 41
++
++/* Timer/Counter4 Compare Match A */
++#define TIMER4_COMPA_vect _VECTOR(42)
++#define TIMER4_COMPA_vect_num 42
++
++/* Timer/Counter4 Compare Match B */
++#define TIMER4_COMPB_vect _VECTOR(43)
++#define TIMER4_COMPB_vect_num 43
++
++/* Timer/Counter4 Compare Match C */
++#define TIMER4_COMPC_vect _VECTOR(44)
++#define TIMER4_COMPC_vect_num 44
++
++/* Timer/Counter4 Overflow */
++#define TIMER4_OVF_vect _VECTOR(45)
++#define TIMER4_OVF_vect_num 45
++
++/* Timer/Counter5 Capture Event */
++#define TIMER5_CAPT_vect _VECTOR(46)
++#define TIMER5_CAPT_vect_num 46
++
++/* Timer/Counter5 Compare Match A */
++#define TIMER5_COMPA_vect _VECTOR(47)
++#define TIMER5_COMPA_vect_num 47
++
++/* Timer/Counter5 Compare Match B */
++#define TIMER5_COMPB_vect _VECTOR(48)
++#define TIMER5_COMPB_vect_num 48
++
++/* Timer/Counter5 Compare Match C */
++#define TIMER5_COMPC_vect _VECTOR(49)
++#define TIMER5_COMPC_vect_num 49
++
++/* Timer/Counter5 Overflow */
++#define TIMER5_OVF_vect _VECTOR(50)
++#define TIMER5_OVF_vect_num 50
++
++/* USART2, Rx Complete */
++#define USART2_RX_vect _VECTOR(51)
++#define USART2_RX_vect_num 51
++
++/* USART2 Data register Empty */
++#define USART2_UDRE_vect _VECTOR(52)
++#define USART2_UDRE_vect_num 52
++
++/* USART2, Tx Complete */
++#define USART2_TX_vect _VECTOR(53)
++#define USART2_TX_vect_num 53
++
++/* USART3, Rx Complete */
++#define USART3_RX_vect _VECTOR(54)
++#define USART3_RX_vect_num 54
++
++/* USART3 Data register Empty */
++#define USART3_UDRE_vect _VECTOR(55)
++#define USART3_UDRE_vect_num 55
++
++/* USART3, Tx Complete */
++#define USART3_TX_vect _VECTOR(56)
++#define USART3_TX_vect_num 56
++
++/* TRX24 - PLL lock interrupt */
++#define TRX24_PLL_LOCK_vect _VECTOR(57)
++#define TRX24_PLL_LOCK_vect_num 57
++
++/* TRX24 - PLL unlock interrupt */
++#define TRX24_PLL_UNLOCK_vect _VECTOR(58)
++#define TRX24_PLL_UNLOCK_vect_num 58
++
++/* TRX24 - Receive start interrupt */
++#define TRX24_RX_START_vect _VECTOR(59)
++#define TRX24_RX_START_vect_num 59
++
++/* TRX24 - RX_END interrupt */
++#define TRX24_RX_END_vect _VECTOR(60)
++#define TRX24_RX_END_vect_num 60
++
++/* TRX24 - CCA/ED done interrupt */
++#define TRX24_CCA_ED_DONE_vect _VECTOR(61)
++#define TRX24_CCA_ED_DONE_vect_num 61
++
++/* TRX24 - XAH - AMI */
++#define TRX24_XAH_AMI_vect _VECTOR(62)
++#define TRX24_XAH_AMI_vect_num 62
++
++/* TRX24 - TX_END interrupt */
++#define TRX24_TX_END_vect _VECTOR(63)
++#define TRX24_TX_END_vect_num 63
++
++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
++#define TRX24_AWAKE_vect _VECTOR(64)
++#define TRX24_AWAKE_vect_num 64
++
++/* Symbol counter - compare match 1 interrupt */
++#define SCNT_CMP1_vect _VECTOR(65)
++#define SCNT_CMP1_vect_num 65
++
++/* Symbol counter - compare match 2 interrupt */
++#define SCNT_CMP2_vect _VECTOR(66)
++#define SCNT_CMP2_vect_num 66
++
++/* Symbol counter - compare match 3 interrupt */
++#define SCNT_CMP3_vect _VECTOR(67)
++#define SCNT_CMP3_vect_num 67
++
++/* Symbol counter - overflow interrupt */
++#define SCNT_OVFL_vect _VECTOR(68)
++#define SCNT_OVFL_vect_num 68
++
++/* Symbol counter - backoff interrupt */
++#define SCNT_BACKOFF_vect _VECTOR(69)
++#define SCNT_BACKOFF_vect_num 69
++
++/* AES engine ready interrupt */
++#define AES_READY_vect _VECTOR(70)
++#define AES_READY_vect_num 70
++
++/* Battery monitor indicates supply voltage below threshold */
++#define BAT_LOW_vect _VECTOR(71)
++#define BAT_LOW_vect_num 71
++
++/* TRX24 TX start interrupt */
++#define TRX24_TX_START_vect _VECTOR(72)
++#define TRX24_TX_START_vect_num 72
++
++/* Address match interrupt of address filter 0 */
++#define TRX24_AMI0_vect _VECTOR(73)
++#define TRX24_AMI0_vect_num 73
++
++/* Address match interrupt of address filter 1 */
++#define TRX24_AMI1_vect _VECTOR(74)
++#define TRX24_AMI1_vect_num 74
++
++/* Address match interrupt of address filter 2 */
++#define TRX24_AMI2_vect _VECTOR(75)
++#define TRX24_AMI2_vect_num 75
++
++/* Address match interrupt of address filter 3 */
++#define TRX24_AMI3_vect _VECTOR(76)
++#define TRX24_AMI3_vect_num 76
++
++#define _VECTORS_SIZE 308
++
++
++/* Constants */
++
++#define SPM_PAGESIZE 256
++#define FLASHSTART 0x0000
++#define FLASHEND 0xFFFF
++#define RAMSTART 0x0200
++#define RAMSIZE 8192
++#define RAMEND 0x21FF
++#define E2START 0
++#define E2SIZE 2048
++#define E2PAGESIZE 8
++#define E2END 0x07FF
++#define XRAMEND RAMEND
++
++
++/* Fuses */
++
++#define FUSE_MEMORY_SIZE 3
++
++/* Low Fuse Byte */
++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0)
++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1)
++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2)
++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3)
++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4)
++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5)
++#define FUSE_CKOUT (unsigned char)~_BV(6)
++#define FUSE_CKDIV8 (unsigned char)~_BV(7)
++
++/* High Fuse Byte */
++#define FUSE_BOOTRST (unsigned char)~_BV(0)
++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
++#define FUSE_EESAVE (unsigned char)~_BV(3)
++#define FUSE_WDTON (unsigned char)~_BV(4)
++#define FUSE_SPIEN (unsigned char)~_BV(5)
++#define FUSE_JTAGEN (unsigned char)~_BV(6)
++#define FUSE_OCDEN (unsigned char)~_BV(7)
++
++/* Extended Fuse Byte */
++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
++
++
++/* Lock Bits */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_BITS_0_EXIST
++#define __BOOT_LOCK_BITS_1_EXIST
++
++
++/* Signature */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0xA6
++#define SIGNATURE_2 0x02
++
++
++#endif /* #ifdef _AVR_ATMEGA64RFR2_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox16e5.h avr-libc-1.8.0/include/avr/iox16e5.h
+--- avr-libc-1.8.0.orig/include/avr/iox16e5.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox16e5.h 2013-01-18 10:08:39.000000000 +0100
+@@ -0,0 +1,7559 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox16e5.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA16E5_H_INCLUDED
++#define _AVR_ATXMEGA16E5_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */
++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */
++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */
++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */
++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t WEXLOCK; /* WEX Lock */
++ register8_t FAULTLOCK; /* FAULT Lock */
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t reserved_0x03;
++ register8_t CLKOUT; /* Clock Out Register */
++ register8_t reserved_0x05;
++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */
++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */
++} PORTCFG_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* RTC Clock Output Port */
++typedef enum PORTCFG_RTCCLKOUT_enum
++{
++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */
++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */
++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */
++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */
++} PORTCFG_RTCCLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */
++} PORTCFG_CLKOUT_t;
++
++/* Analog Comparator Output Port */
++typedef enum PORTCFG_ACOUT_enum
++{
++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */
++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */
++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */
++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */
++} PORTCFG_ACOUT_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */
++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EDMA - Enhanced DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* EDMA Channel */
++typedef struct EDMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control A */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */
++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ register8_t reserved_0x05;
++ register8_t TRFCNTL; /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */
++ register8_t TRFCNTH; /* Channel Block Transfer Count High for Standard Channels Only */
++ register8_t ADDRL; /* Channel Memory Address Low for Peripheral Ch., or Channel Source Address Low for Standard Ch. */
++ register8_t ADDRH; /* Channel Memory Address High for Peripheral Ch., or Channel Source Address High for Standard Ch. */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDRL; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t DESTADDRH; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} EDMA_CH_t;
++
++
++/* Enhanced DMA Controller */
++typedef struct EDMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ EDMA_CH_t CH0; /* EDMA Channel 0 */
++ EDMA_CH_t CH1; /* EDMA Channel 1 */
++ EDMA_CH_t CH2; /* EDMA Channel 2 */
++ EDMA_CH_t CH3; /* EDMA Channel 3 */
++} EDMA_t;
++
++/* Channel mode */
++typedef enum EDMA_CHMODE_enum
++{
++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */
++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */
++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */
++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */
++} EDMA_CHMODE_t;
++
++/* Double buffer mode */
++typedef enum EDMA_DBUFMODE_enum
++{
++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */
++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */
++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */
++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */
++} EDMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum EDMA_PRIMODE_enum
++{
++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */
++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */
++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */
++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */
++} EDMA_PRIMODE_t;
++
++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */
++typedef enum EDMA_CH_RELOAD_enum
++{
++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */
++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */
++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */
++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */
++} EDMA_CH_RELOAD_t;
++
++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */
++typedef enum EDMA_CH_DIR_enum
++{
++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */
++} EDMA_CH_DIR_t;
++
++/* Destination addressing mode */
++typedef enum EDMA_CH_DESTDIR_enum
++{
++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */
++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */
++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */
++} EDMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum EDMA_CH_TRIGSRC_enum
++{
++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */
++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */
++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */
++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */
++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */
++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */
++} EDMA_CH_TRIGSRC_t;
++
++/* Interrupt level */
++typedef enum EDMA_CH_INTLVL_enum
++{
++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */
++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */
++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */
++} EDMA_CH_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++ register8_t DFCTRL; /* Digital Filter Control Register */
++} EVSYS_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */
++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */
++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */
++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */
++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */
++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */
++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */
++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */
++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */
++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */
++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */
++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */
++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */
++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */
++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */
++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */
++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */
++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */
++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */
++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<0), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<0), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<0), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<0), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Prescaler Filter */
++typedef enum EVSYS_PRESCFILT_enum
++{
++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */
++ EVSYS_PRESCFILT_CH15_gc = (0x08<<4), /* Enable prescaler filter for either channel 1 or 5 */
++ EVSYS_PRESCFILT_CH26_gc = (0x40<<4), /* Enable prescaler filter for either channel 2 or 6 */
++ EVSYS_PRESCFILT_CH37_gc = (0x3E8<<4), /* Enable prescaler filter for either channel 3 or 7 */
++} EVSYS_PRESCFILT_t;
++
++/* Prescaler */
++typedef enum EVSYS_PRESCALER_enum
++{
++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */
++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */
++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */
++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */
++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */
++} EVSYS_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t CORRCTRL; /* Correction Control Register */
++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */
++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */
++ register8_t GAINCORR0; /* Gain Correction Register 0 */
++ register8_t GAINCORR1; /* Gain Correction Register 1 */
++ register8_t AVGCTRL; /* Average Control Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Current Limitation */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */
++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */
++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */
++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */
++} ADC_CURRLIMIT_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */
++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */
++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */
++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */
++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */
++} ADC_CH_INPUTMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection when gain on 4 LSB pins */
++typedef enum ADC_CH_MUXNEGL_enum
++{
++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */
++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */
++} ADC_CH_MUXNEGL_t;
++
++/* Negative input multiplexer selection when gain on 4 MSB pins */
++typedef enum ADC_CH_MUXNEGH_enum
++{
++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */
++ ADC_CH_MUXNEGH_INTGND_gc = (0x04<<0), /* Internal ground */
++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */
++} ADC_CH_MUXNEGH_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++} ADC_CH_MUXNEG_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Averaged Number of Samples */
++typedef enum ADC_SAMPNUM_enum
++{
++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */
++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */
++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */
++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */
++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */
++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */
++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */
++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */
++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */
++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */
++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */
++} ADC_SAMPNUM_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Clounter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t CALIB; /* Calibration Register */
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++XCL - XMEGA Custom Logic
++--------------------------------------------------------------------------
++*/
++
++/* XMEGA Custom Logic */
++typedef struct XCL_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t PLC; /* Peripheral Lenght Control Register */
++ register8_t CNTL; /* Counter Register Low */
++ register8_t CNTH; /* Counter Register High */
++ register8_t CMPL; /* Compare Register Low */
++ register8_t CMPH; /* Compare Register High */
++ register8_t PERCAPTL; /* Period or Capture Register Low */
++ register8_t PERCAPTH; /* Period or Capture Register High */
++} XCL_t;
++
++/* LUT0 Output Enable */
++typedef enum XCL_LUTOUTEN_enum
++{
++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */
++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */
++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */
++} XCL_LUTOUTEN_t;
++
++/* Port Selection */
++typedef enum XCL_PORTSEL_enum
++{
++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */
++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */
++} XCL_PORTSEL_t;
++
++/* LUT Configuration */
++typedef enum XCL_LUTCONF_enum
++{
++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */
++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */
++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */
++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */
++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */
++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */
++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */
++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */
++} XCL_LUTCONF_t;
++
++/* Input Selection */
++typedef enum XCL_INSEL_enum
++{
++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */
++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */
++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */
++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */
++} XCL_INSEL_t;
++
++/* Delay Configuration on LUT */
++typedef enum XCL_DLYCONF_enum
++{
++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */
++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */
++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */
++} XCL_DLYCONF_t;
++
++/* Delay Selection */
++typedef enum XCL_DLYSEL_enum
++{
++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */
++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */
++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */
++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */
++} XCL_DLYSEL_t;
++
++/* Clock Selection */
++typedef enum XCL_CLKSEL_enum
++{
++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */
++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */
++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */
++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */
++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */
++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */
++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */
++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */
++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */
++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */
++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */
++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */
++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */
++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */
++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */
++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */
++} XCL_CLKSEL_t;
++
++/* Timer/Counter Command Selection */
++typedef enum XCL_CMDSEL_enum
++{
++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */
++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */
++} XCL_CMDSEL_t;
++
++/* Timer/Counter Selection */
++typedef enum XCL_TCSEL_enum
++{
++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */
++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */
++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */
++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */
++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */
++} XCL_TCSEL_t;
++
++/* Timer/Counter Mode */
++typedef enum XCL_TCMODE_enum
++{
++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */
++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */
++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */
++} XCL_TCMODE_t;
++
++/* Compare Output Value Timer */
++typedef enum XCL_CMPEN_enum
++{
++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */
++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */
++} XCL_CMPEN_t;
++
++/* Command Enable */
++typedef enum XCL_CMDEN_enum
++{
++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */
++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */
++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */
++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */
++} XCL_CMDEN_t;
++
++/* Timer/Counter Event Source Selection */
++typedef enum XCL_EVSRC_enum
++{
++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */
++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */
++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */
++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */
++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */
++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */
++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */
++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */
++} XCL_EVSRC_t;
++
++/* Timer/Counter Event Action Selection */
++typedef enum XCL_EVACT_enum
++{
++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */
++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */
++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */
++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */
++} XCL_EVACT_t;
++
++/* Underflow Interrupt level */
++typedef enum XCL_UNF_INTLVL_enum
++{
++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */
++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */
++} XCL_UNF_INTLVL_t;
++
++/* Compare/Capture Interrupt level */
++typedef enum XCL_CC_INTLVL_enum
++{
++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} XCL_CC_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTMASK; /* Port Interrupt Mask */
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt Level */
++typedef enum PORT_INTLVL_enum
++{
++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INTLVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 4 */
++typedef struct TC4_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC4_t;
++
++
++/* 16-bit Timer/Counter 5 */
++typedef struct TC5_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} TC5_t;
++
++/* Clock Selection */
++typedef enum TC45_CLKSEL_enum
++{
++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC45_BYTEM_enum
++{
++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */
++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */
++} TC45_BYTEM_t;
++
++/* Circular Enable Mode */
++typedef enum TC45_CIRCEN_enum
++{
++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */
++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */
++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */
++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */
++} TC45_CIRCEN_t;
++
++/* Waveform Generation Mode */
++typedef enum TC45_WGMODE_enum
++{
++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */
++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC45_WGMODE_t;
++
++/* Event Action */
++typedef enum TC45_EVACT_enum
++{
++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */
++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */
++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */
++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */
++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */
++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */
++} TC45_EVACT_t;
++
++/* Event Selection */
++typedef enum TC45_EVSEL_enum
++{
++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_EVSEL_t;
++
++/* Compare or Capture Channel A Mode */
++typedef enum TC45_CCAMODE_enum
++{
++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_CCAMODE_t;
++
++/* Compare or Capture Channel B Mode */
++typedef enum TC45_CCBMODE_enum
++{
++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_CCBMODE_t;
++
++/* Compare or Capture Channel C Mode */
++typedef enum TC45_CCCMODE_enum
++{
++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_CCCMODE_t;
++
++/* Compare or Capture Channel D Mode */
++typedef enum TC45_CCDMODE_enum
++{
++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_CCDMODE_t;
++
++/* Compare or Capture Low Channel A Mode */
++typedef enum TC45_LCCAMODE_enum
++{
++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_LCCAMODE_t;
++
++/* Compare or Capture Low Channel B Mode */
++typedef enum TC45_LCCBMODE_enum
++{
++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_LCCBMODE_t;
++
++/* Compare or Capture Low Channel C Mode */
++typedef enum TC45_LCCCMODE_enum
++{
++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_LCCCMODE_t;
++
++/* Compare or Capture Low Channel D Mode */
++typedef enum TC45_LCCDMODE_enum
++{
++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_LCCDMODE_t;
++
++/* Compare or Capture High Channel A Mode */
++typedef enum TC45_HCCAMODE_enum
++{
++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_HCCAMODE_t;
++
++/* Compare or Capture High Channel B Mode */
++typedef enum TC45_HCCBMODE_enum
++{
++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_HCCBMODE_t;
++
++/* Compare or Capture High Channel C Mode */
++typedef enum TC45_HCCCMODE_enum
++{
++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_HCCCMODE_t;
++
++/* Compare or Capture High Channel D Mode */
++typedef enum TC45_HCCDMODE_enum
++{
++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_HCCDMODE_t;
++
++/* Timer Trigger Restart Interrupt Level */
++typedef enum TC45_TRGINTLVL_enum
++{
++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_TRGINTLVL_t;
++
++/* Error Interrupt Level */
++typedef enum TC45_ERRINTLVL_enum
++{
++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC45_OVFINTLVL_enum
++{
++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_OVFINTLVL_t;
++
++/* Compare or Capture Channel A Interrupt Level */
++typedef enum TC45_CCAINTLVL_enum
++{
++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_CCAINTLVL_t;
++
++/* Compare or Capture Channel B Interrupt Level */
++typedef enum TC45_CCBINTLVL_enum
++{
++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_CCBINTLVL_t;
++
++/* Compare or Capture Channel C Interrupt Level */
++typedef enum TC45_CCCINTLVL_enum
++{
++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_CCCINTLVL_t;
++
++/* Compare or Capture Channel D Interrupt Level */
++typedef enum TC45_CCDINTLVL_enum
++{
++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_CCDINTLVL_t;
++
++/* Compare or Capture Low Channel A Interrupt Level */
++typedef enum TC45_LCCAINTLVL_enum
++{
++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_LCCAINTLVL_t;
++
++/* Compare or Capture Low Channel B Interrupt Level */
++typedef enum TC45_LCCBINTLVL_enum
++{
++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_LCCBINTLVL_t;
++
++/* Compare or Capture Low Channel C Interrupt Level */
++typedef enum TC45_LCCCINTLVL_enum
++{
++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_LCCCINTLVL_t;
++
++/* Compare or Capture Low Channel D Interrupt Level */
++typedef enum TC45_LCCDINTLVL_enum
++{
++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_LCCDINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC45_CMD_enum
++{
++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC45_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++FAULT - Fault Extension
++--------------------------------------------------------------------------
++*/
++
++/* Fault Extension */
++typedef struct FAULT_struct
++{
++ register8_t CTRLA; /* Control A Register */
++ register8_t CTRLB; /* Control B Register */
++ register8_t CTRLC; /* Control C Register */
++ register8_t CTRLD; /* Control D Register */
++ register8_t CTRLE; /* Control E Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G set */
++} FAULT_t;
++
++/* Ramp Mode Selection */
++typedef enum FAULT_RAMP_enum
++{
++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */
++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */
++} FAULT_RAMP_t;
++
++/* Fault E Input Source Selection */
++typedef enum FAULT_SRCE_enum
++{
++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */
++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */
++} FAULT_SRCE_t;
++
++/* Fault A Halt Action Selection */
++typedef enum FAULT_HALTA_enum
++{
++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTA_t;
++
++/* Fault A Source Selection */
++typedef enum FAULT_SRCA_enum
++{
++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */
++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */
++} FAULT_SRCA_t;
++
++/* Fault B Halt Action Selection */
++typedef enum FAULT_HALTB_enum
++{
++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTB_t;
++
++/* Fault B Source Selection */
++typedef enum FAULT_SRCB_enum
++{
++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */
++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */
++} FAULT_SRCB_t;
++
++/* Channel index Command */
++typedef enum FAULT_IDXCMD_enum
++{
++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */
++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */
++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */
++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */
++} FAULT_IDXCMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++WEX - Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Waveform Extension */
++typedef struct WEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */
++ register8_t DTLS; /* Dead-time Low Side Register */
++ register8_t DTHS; /* Dead-time High Side Register */
++ register8_t STATUSCLR; /* Status Clear Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t SWAP; /* Swap Register */
++ register8_t PGO; /* Pattern Generation Override Register */
++ register8_t PGV; /* Pattern Generation Value Register */
++ register8_t reserved_0x09;
++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */
++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */
++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t OUTOVDIS; /* Output Override Disable Register */
++} WEX_t;
++
++/* Output Matrix Mode */
++typedef enum WEX_OTMX_enum
++{
++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */
++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */
++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */
++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */
++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */
++} WEX_OTMX_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register A */
++} HIRES_t;
++
++/* High Resolution Plus Mode */
++typedef enum HIRES_HRPLUS_enum
++{
++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */
++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */
++ HIRES_HRPLUS_HRP5_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 5 */
++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */
++} HIRES_HRPLUS_t;
++
++/* High Resolution Mode */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */
++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */
++ HIRES_HREN_HRP5_gc = (0x03<<0), /* Hi-Res enabled on Timer 5 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Start Interrupt level */
++typedef enum USART_RXSINTLVL_enum
++{
++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_RXSINTLVL_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++/* Encoding and Decoding Type */
++typedef enum USART_DECTYPE_enum
++{
++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */
++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */
++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */
++} USART_DECTYPE_t;
++
++/* XCL LUT Action */
++typedef enum USART_LUTACT_enum
++{
++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */
++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */
++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */
++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */
++} USART_LUTACT_t;
++
++/* XCL Peripheral Counter Action */
++typedef enum USART_PECACT_enum
++{
++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */
++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */
++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */
++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */
++} USART_PECACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface with Buffer Modes */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++ register8_t CTRLB; /* Control Register B */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++/* Buffer Modes */
++typedef enum SPI_BUFMODE_enum
++{
++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */
++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */
++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */
++} SPI_BUFMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++ register8_t FUSEBYTE6; /* Fault State */
++} NVM_FUSES_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BOD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */
++ register8_t reserved_0x01;
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */
++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */
++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */
++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */
++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */
++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++#define OSC_RC8MCAL _SFR_MEM8(0x0057)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_WEXLOCK _SFR_MEM8(0x0099)
++#define MCU_FAULTLOCK _SFR_MEM8(0x009A)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6)
++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EDMA - Enhanced DMA Controller */
++#define EDMA_CTRL _SFR_MEM8(0x0100)
++#define EDMA_INTFLAGS _SFR_MEM8(0x0103)
++#define EDMA_STATUS _SFR_MEM8(0x0104)
++#define EDMA_TEMP _SFR_MEM8(0x0106)
++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113)
++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114)
++#define EDMA_CH0_TRFCNTL _SFR_MEM8(0x0116)
++#define EDMA_CH0_TRFCNTH _SFR_MEM8(0x0117)
++#define EDMA_CH0_ADDRL _SFR_MEM8(0x0118)
++#define EDMA_CH0_ADDRH _SFR_MEM8(0x0119)
++#define EDMA_CH0_DESTADDRL _SFR_MEM8(0x011C)
++#define EDMA_CH0_DESTADDRH _SFR_MEM8(0x011D)
++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123)
++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124)
++#define EDMA_CH1_TRFCNTL _SFR_MEM8(0x0126)
++#define EDMA_CH1_TRFCNTH _SFR_MEM8(0x0127)
++#define EDMA_CH1_ADDRL _SFR_MEM8(0x0128)
++#define EDMA_CH1_ADDRH _SFR_MEM8(0x0129)
++#define EDMA_CH1_DESTADDRL _SFR_MEM8(0x012C)
++#define EDMA_CH1_DESTADDRH _SFR_MEM8(0x012D)
++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133)
++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134)
++#define EDMA_CH2_TRFCNTL _SFR_MEM8(0x0136)
++#define EDMA_CH2_TRFCNTH _SFR_MEM8(0x0137)
++#define EDMA_CH2_ADDRL _SFR_MEM8(0x0138)
++#define EDMA_CH2_ADDRH _SFR_MEM8(0x0139)
++#define EDMA_CH2_DESTADDRL _SFR_MEM8(0x013C)
++#define EDMA_CH2_DESTADDRH _SFR_MEM8(0x013D)
++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143)
++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144)
++#define EDMA_CH3_TRFCNTL _SFR_MEM8(0x0146)
++#define EDMA_CH3_TRFCNTH _SFR_MEM8(0x0147)
++#define EDMA_CH3_ADDRL _SFR_MEM8(0x0148)
++#define EDMA_CH3_ADDRH _SFR_MEM8(0x0149)
++#define EDMA_CH3_DESTADDRL _SFR_MEM8(0x014C)
++#define EDMA_CH3_DESTADDRH _SFR_MEM8(0x014D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++#define EVSYS_DFCTRL _SFR_MEM8(0x0192)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227)
++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228)
++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229)
++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A)
++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B)
++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACA_CTRLA _SFR_MEM8(0x0300)
++#define DACA_CTRLB _SFR_MEM8(0x0301)
++#define DACA_CTRLC _SFR_MEM8(0x0302)
++#define DACA_EVCTRL _SFR_MEM8(0x0303)
++#define DACA_TIMCTRL _SFR_MEM8(0x0304)
++#define DACA_STATUS _SFR_MEM8(0x0305)
++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308)
++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309)
++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A)
++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B)
++#define DACA_CH0DATA _SFR_MEM16(0x0318)
++#define DACA_CH1DATA _SFR_MEM16(0x031A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++#define ACA_CURRCTRL _SFR_MEM8(0x0388)
++#define ACA_CURRCALIB _SFR_MEM8(0x0389)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CALIB _SFR_MEM8(0x0406)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* XCL - XMEGA Custom Logic */
++#define XCL_CTRLA _SFR_MEM8(0x0460)
++#define XCL_CTRLB _SFR_MEM8(0x0461)
++#define XCL_CTRLC _SFR_MEM8(0x0462)
++#define XCL_CTRLD _SFR_MEM8(0x0463)
++#define XCL_CTRLE _SFR_MEM8(0x0464)
++#define XCL_CTRLF _SFR_MEM8(0x0465)
++#define XCL_CTRLG _SFR_MEM8(0x0466)
++#define XCL_INTCTRL _SFR_MEM8(0x0467)
++#define XCL_INTFLAGS _SFR_MEM8(0x0468)
++#define XCL_PLC _SFR_MEM8(0x0469)
++#define XCL_CNTL _SFR_MEM8(0x046A)
++#define XCL_CNTH _SFR_MEM8(0x046B)
++#define XCL_CMPL _SFR_MEM8(0x046C)
++#define XCL_CMPH _SFR_MEM8(0x046D)
++#define XCL_PERCAPTL _SFR_MEM8(0x046E)
++#define XCL_PERCAPTH _SFR_MEM8(0x046F)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INTMASK _SFR_MEM8(0x060A)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INTMASK _SFR_MEM8(0x064A)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INTMASK _SFR_MEM8(0x066A)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INTMASK _SFR_MEM8(0x07EA)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC4 - 16-bit Timer/Counter 4 */
++#define TCC4_CTRLA _SFR_MEM8(0x0800)
++#define TCC4_CTRLB _SFR_MEM8(0x0801)
++#define TCC4_CTRLC _SFR_MEM8(0x0802)
++#define TCC4_CTRLD _SFR_MEM8(0x0803)
++#define TCC4_CTRLE _SFR_MEM8(0x0804)
++#define TCC4_CTRLF _SFR_MEM8(0x0805)
++#define TCC4_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC4_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808)
++#define TCC4_CTRLGSET _SFR_MEM8(0x0809)
++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A)
++#define TCC4_CTRLHSET _SFR_MEM8(0x080B)
++#define TCC4_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC4_TEMP _SFR_MEM8(0x080F)
++#define TCC4_CNT _SFR_MEM16(0x0820)
++#define TCC4_PER _SFR_MEM16(0x0826)
++#define TCC4_CCA _SFR_MEM16(0x0828)
++#define TCC4_CCB _SFR_MEM16(0x082A)
++#define TCC4_CCC _SFR_MEM16(0x082C)
++#define TCC4_CCD _SFR_MEM16(0x082E)
++#define TCC4_PERBUF _SFR_MEM16(0x0836)
++#define TCC4_CCABUF _SFR_MEM16(0x0838)
++#define TCC4_CCBBUF _SFR_MEM16(0x083A)
++#define TCC4_CCCBUF _SFR_MEM16(0x083C)
++#define TCC4_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCC5_CTRLA _SFR_MEM8(0x0840)
++#define TCC5_CTRLB _SFR_MEM8(0x0841)
++#define TCC5_CTRLC _SFR_MEM8(0x0842)
++#define TCC5_CTRLD _SFR_MEM8(0x0843)
++#define TCC5_CTRLE _SFR_MEM8(0x0844)
++#define TCC5_CTRLF _SFR_MEM8(0x0845)
++#define TCC5_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC5_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848)
++#define TCC5_CTRLGSET _SFR_MEM8(0x0849)
++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A)
++#define TCC5_CTRLHSET _SFR_MEM8(0x084B)
++#define TCC5_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC5_TEMP _SFR_MEM8(0x084F)
++#define TCC5_CNT _SFR_MEM16(0x0860)
++#define TCC5_PER _SFR_MEM16(0x0866)
++#define TCC5_CCA _SFR_MEM16(0x0868)
++#define TCC5_CCB _SFR_MEM16(0x086A)
++#define TCC5_PERBUF _SFR_MEM16(0x0876)
++#define TCC5_CCABUF _SFR_MEM16(0x0878)
++#define TCC5_CCBBUF _SFR_MEM16(0x087A)
++
++/* FAULT - Fault Extension */
++#define FAULTC4_CTRLA _SFR_MEM8(0x0880)
++#define FAULTC4_CTRLB _SFR_MEM8(0x0881)
++#define FAULTC4_CTRLC _SFR_MEM8(0x0882)
++#define FAULTC4_CTRLD _SFR_MEM8(0x0883)
++#define FAULTC4_CTRLE _SFR_MEM8(0x0884)
++#define FAULTC4_STATUS _SFR_MEM8(0x0885)
++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886)
++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887)
++
++/* FAULT - Fault Extension */
++#define FAULTC5_CTRLA _SFR_MEM8(0x0890)
++#define FAULTC5_CTRLB _SFR_MEM8(0x0891)
++#define FAULTC5_CTRLC _SFR_MEM8(0x0892)
++#define FAULTC5_CTRLD _SFR_MEM8(0x0893)
++#define FAULTC5_CTRLE _SFR_MEM8(0x0894)
++#define FAULTC5_STATUS _SFR_MEM8(0x0895)
++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896)
++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897)
++
++/* WEX - Waveform Extension */
++#define WEXC_CTRL _SFR_MEM8(0x08A0)
++#define WEXC_DTBOTH _SFR_MEM8(0x08A1)
++#define WEXC_DTLS _SFR_MEM8(0x08A2)
++#define WEXC_DTHS _SFR_MEM8(0x08A3)
++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4)
++#define WEXC_STATUSSET _SFR_MEM8(0x08A5)
++#define WEXC_SWAP _SFR_MEM8(0x08A6)
++#define WEXC_PGO _SFR_MEM8(0x08A7)
++#define WEXC_PGV _SFR_MEM8(0x08A8)
++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA)
++#define WEXC_PGOBUF _SFR_MEM8(0x08AB)
++#define WEXC_PGVBUF _SFR_MEM8(0x08AC)
++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x08B0)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08C0)
++#define USARTC0_STATUS _SFR_MEM8(0x08C1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08C2)
++#define USARTC0_CTRLB _SFR_MEM8(0x08C3)
++#define USARTC0_CTRLC _SFR_MEM8(0x08C4)
++#define USARTC0_CTRLD _SFR_MEM8(0x08C5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7)
++
++/* SPI - Serial Peripheral Interface with Buffer Modes */
++#define SPIC_CTRL _SFR_MEM8(0x08E0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08E1)
++#define SPIC_STATUS _SFR_MEM8(0x08E2)
++#define SPIC_DATA _SFR_MEM8(0x08E3)
++#define SPIC_CTRLB _SFR_MEM8(0x08E4)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCD5_CTRLA _SFR_MEM8(0x0940)
++#define TCD5_CTRLB _SFR_MEM8(0x0941)
++#define TCD5_CTRLC _SFR_MEM8(0x0942)
++#define TCD5_CTRLD _SFR_MEM8(0x0943)
++#define TCD5_CTRLE _SFR_MEM8(0x0944)
++#define TCD5_CTRLF _SFR_MEM8(0x0945)
++#define TCD5_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD5_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948)
++#define TCD5_CTRLGSET _SFR_MEM8(0x0949)
++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A)
++#define TCD5_CTRLHSET _SFR_MEM8(0x094B)
++#define TCD5_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD5_TEMP _SFR_MEM8(0x094F)
++#define TCD5_CNT _SFR_MEM16(0x0960)
++#define TCD5_PER _SFR_MEM16(0x0966)
++#define TCD5_CCA _SFR_MEM16(0x0968)
++#define TCD5_CCB _SFR_MEM16(0x096A)
++#define TCD5_PERBUF _SFR_MEM16(0x0976)
++#define TCD5_CCABUF _SFR_MEM16(0x0978)
++#define TCD5_CCBBUF _SFR_MEM16(0x097A)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09C0)
++#define USARTD0_STATUS _SFR_MEM8(0x09C1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09C2)
++#define USARTD0_CTRLB _SFR_MEM8(0x09C3)
++#define USARTD0_CTRLC _SFR_MEM8(0x09C4)
++#define USARTD0_CTRLD _SFR_MEM8(0x09C5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */
++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */
++
++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */
++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */
++
++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */
++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */
++
++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */
++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */
++
++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */
++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */
++
++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */
++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */
++
++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */
++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */
++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C WEX bit position. */
++
++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */
++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */
++
++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */
++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC5 Predefined. */
++/* PR_TC5 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */
++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */
++
++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */
++
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */
++
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++/* OSC.RC8MCAL bit masks and bit positions */
++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */
++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */
++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */
++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */
++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */
++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */
++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */
++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */
++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */
++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */
++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */
++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */
++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */
++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */
++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */
++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */
++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */
++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.WEXLOCK bit masks and bit positions */
++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */
++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */
++
++/* MCU.FAULTLOCK bit masks and bit positions */
++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */
++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */
++
++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */
++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.CLKOUT bit masks and bit positions */
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */
++
++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */
++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */
++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */
++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */
++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */
++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */
++
++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
++
++/* PORTCFG.ACEVOUT bit masks and bit positions */
++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */
++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */
++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */
++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */
++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */
++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */
++
++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */
++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */
++
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */
++
++/* PORTCFG.SRLCTRL bit masks and bit positions */
++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */
++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */
++
++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */
++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */
++
++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */
++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */
++
++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */
++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EDMA - Enhanced DMA Controller */
++/* EDMA.CTRL bit masks and bit positions */
++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define EDMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define EDMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */
++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */
++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */
++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */
++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */
++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */
++
++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */
++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */
++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */
++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */
++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */
++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */
++
++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */
++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */
++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */
++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */
++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */
++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */
++
++/* EDMA.INTFLAGS bit masks and bit positions */
++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* EDMA.STATUS bit masks and bit positions */
++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */
++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */
++
++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */
++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */
++
++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */
++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */
++
++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */
++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */
++
++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */
++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */
++
++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */
++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */
++
++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */
++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */
++
++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */
++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */
++
++/* EDMA_CH.CTRLA bit masks and bit positions */
++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */
++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */
++
++/* EDMA_CH.CTRLB bit masks and bit positions */
++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */
++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */
++
++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */
++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */
++
++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */
++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */
++
++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */
++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */
++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */
++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */
++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */
++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */
++
++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */
++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */
++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */
++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */
++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */
++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */
++
++/* EDMA_CH.ADDRCTRL bit masks and bit positions */
++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */
++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */
++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */
++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */
++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */
++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */
++
++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */
++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */
++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */
++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */
++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */
++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */
++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */
++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */
++
++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */
++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */
++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */
++
++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */
++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */
++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */
++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */
++
++/* EDMA_CH.TRIGSRC bit masks and bit positions */
++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */
++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */
++
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.DFCTRL bit masks and bit positions */
++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */
++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */
++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */
++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */
++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */
++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */
++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */
++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */
++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */
++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */
++
++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */
++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */
++
++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */
++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */
++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */
++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */
++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */
++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */
++
++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */
++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */
++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */
++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */
++
++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */
++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */
++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */
++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */
++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */
++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */
++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */
++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */
++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */
++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */
++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */
++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */
++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */
++
++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */
++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */
++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */
++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */
++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */
++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */
++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */
++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */
++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */
++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */
++
++/* ADC_CH.CORRCTRL bit masks and bit positions */
++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */
++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */
++
++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */
++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */
++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */
++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */
++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */
++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */
++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */
++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */
++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */
++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */
++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.GAINCORR1 bit masks and bit positions */
++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */
++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */
++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */
++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */
++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */
++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */
++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */
++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */
++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */
++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.AVGCTRL bit masks and bit positions */
++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */
++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */
++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */
++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */
++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */
++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */
++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */
++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */
++
++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */
++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */
++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */
++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */
++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */
++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */
++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */
++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */
++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */
++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */
++#define ADC_START_bp 2 /* Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Clounter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */
++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */
++
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* RTC.CALIB bit masks and bit positions */
++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */
++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */
++
++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */
++#define RTC_ERROR_gp 0 /* Error Value group position. */
++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */
++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */
++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */
++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */
++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */
++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */
++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */
++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */
++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */
++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */
++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */
++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */
++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */
++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */
++
++/* XCL - XMEGA Custom Logic */
++/* XCL.CTRLA bit masks and bit positions */
++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */
++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */
++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */
++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */
++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */
++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */
++
++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */
++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */
++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */
++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */
++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */
++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */
++
++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */
++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */
++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */
++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */
++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */
++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */
++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */
++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */
++
++/* XCL.CTRLB bit masks and bit positions */
++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */
++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */
++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */
++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */
++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */
++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */
++
++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */
++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */
++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */
++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */
++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */
++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */
++
++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */
++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */
++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */
++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */
++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */
++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */
++
++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */
++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */
++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */
++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */
++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */
++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */
++
++/* XCL.CTRLC bit masks and bit positions */
++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */
++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */
++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */
++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */
++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */
++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */
++
++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */
++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */
++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */
++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */
++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */
++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */
++
++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */
++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */
++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */
++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */
++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */
++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */
++
++/* XCL.CTRLD bit masks and bit positions */
++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */
++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */
++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */
++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */
++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */
++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */
++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */
++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */
++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */
++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */
++
++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */
++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */
++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */
++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */
++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */
++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */
++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */
++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */
++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */
++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */
++
++/* XCL.CTRLE bit masks and bit positions */
++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */
++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */
++
++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */
++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */
++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */
++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */
++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */
++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */
++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */
++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */
++
++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */
++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* XCL.CTRLF bit masks and bit positions */
++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */
++#define XCL_CMDEN_gp 6 /* Command Enable group position. */
++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */
++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */
++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */
++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */
++
++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */
++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */
++
++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */
++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */
++
++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */
++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */
++
++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */
++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */
++
++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */
++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */
++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */
++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */
++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */
++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */
++
++/* XCL.CTRLG bit masks and bit positions */
++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */
++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */
++
++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */
++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */
++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */
++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */
++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */
++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */
++
++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */
++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */
++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */
++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */
++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */
++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */
++
++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */
++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */
++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */
++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */
++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */
++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */
++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */
++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */
++
++/* XCL.INTCTRL bit masks and bit positions */
++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */
++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */
++
++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */
++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */
++
++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */
++
++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */
++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */
++
++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */
++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */
++
++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */
++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */
++
++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */
++
++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */
++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */
++
++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */
++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */
++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */
++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */
++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */
++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */
++
++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */
++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */
++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */
++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */
++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */
++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */
++
++/* XCL.INTFLAGS bit masks and bit positions */
++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */
++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */
++
++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */
++
++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */
++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */
++
++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */
++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */
++
++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */
++
++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */
++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */
++
++/* XCL.PLC bit masks and bit positions */
++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */
++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */
++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */
++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */
++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */
++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */
++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */
++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */
++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */
++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */
++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */
++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */
++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */
++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */
++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */
++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */
++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */
++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */
++
++/* XCL.CNTL bit masks and bit positions */
++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */
++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */
++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */
++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */
++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */
++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */
++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */
++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */
++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */
++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */
++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */
++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */
++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */
++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */
++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */
++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */
++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */
++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */
++
++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */
++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */
++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */
++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */
++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */
++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */
++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */
++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */
++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */
++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */
++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */
++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */
++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */
++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */
++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */
++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */
++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */
++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */
++
++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */
++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */
++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */
++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */
++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */
++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */
++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */
++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */
++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */
++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */
++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */
++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */
++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */
++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */
++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */
++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */
++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */
++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */
++
++/* XCL.CNTH bit masks and bit positions */
++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */
++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */
++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */
++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */
++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */
++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */
++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */
++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */
++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */
++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */
++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */
++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */
++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */
++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */
++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */
++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */
++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */
++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */
++
++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */
++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */
++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */
++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */
++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */
++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */
++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */
++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */
++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */
++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */
++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */
++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */
++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */
++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */
++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */
++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */
++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */
++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */
++
++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */
++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */
++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */
++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */
++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */
++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */
++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */
++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */
++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */
++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */
++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */
++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */
++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */
++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */
++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */
++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */
++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */
++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */
++
++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */
++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */
++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */
++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */
++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */
++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */
++
++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */
++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */
++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */
++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */
++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */
++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */
++
++/* XCL.CMPL bit masks and bit positions */
++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */
++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */
++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */
++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */
++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */
++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */
++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */
++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */
++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */
++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */
++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */
++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */
++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */
++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */
++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */
++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */
++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */
++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */
++
++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */
++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */
++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */
++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */
++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */
++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */
++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */
++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */
++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */
++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */
++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */
++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */
++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */
++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */
++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */
++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */
++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */
++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */
++
++/* XCL.CMPH bit masks and bit positions */
++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */
++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */
++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */
++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */
++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */
++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */
++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */
++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */
++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */
++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */
++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */
++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */
++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */
++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */
++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */
++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */
++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */
++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */
++
++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */
++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */
++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */
++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */
++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */
++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */
++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */
++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */
++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */
++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */
++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */
++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */
++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */
++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */
++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */
++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */
++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */
++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */
++
++/* XCL.PERCAPTL bit masks and bit positions */
++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */
++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */
++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */
++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */
++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */
++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */
++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */
++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */
++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */
++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */
++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */
++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */
++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */
++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */
++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */
++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */
++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */
++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */
++
++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */
++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */
++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */
++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */
++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */
++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */
++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */
++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */
++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */
++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */
++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */
++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */
++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */
++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */
++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */
++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */
++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */
++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */
++
++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */
++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */
++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */
++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */
++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */
++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */
++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */
++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */
++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */
++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */
++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */
++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */
++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */
++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */
++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */
++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */
++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */
++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */
++
++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */
++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */
++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */
++
++/* XCL.PERCAPTH bit masks and bit positions */
++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */
++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */
++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */
++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */
++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */
++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */
++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */
++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */
++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */
++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */
++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */
++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */
++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */
++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */
++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */
++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */
++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */
++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */
++
++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */
++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */
++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */
++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */
++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */
++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */
++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */
++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */
++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */
++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */
++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */
++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */
++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */
++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */
++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */
++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */
++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */
++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */
++
++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */
++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */
++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */
++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */
++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */
++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */
++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */
++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */
++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */
++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */
++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */
++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */
++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */
++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */
++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */
++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */
++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */
++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */
++
++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */
++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */
++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */
++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */
++
++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */
++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */
++
++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */
++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */
++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */
++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */
++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */
++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */
++
++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */
++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */
++
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* PORT - Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */
++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */
++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */
++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */
++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */
++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */
++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */
++
++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */
++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */
++
++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */
++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */
++
++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */
++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */
++
++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */
++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */
++
++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */
++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */
++
++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */
++#define PORT_USART0_bp 4 /* Usart0 bit position. */
++
++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */
++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */
++
++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */
++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */
++
++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */
++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */
++
++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */
++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC4.CTRLA bit masks and bit positions */
++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC4.CTRLB bit masks and bit positions */
++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC4.CTRLC bit masks and bit positions */
++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */
++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */
++
++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */
++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */
++
++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */
++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */
++
++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */
++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */
++
++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */
++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */
++
++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */
++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */
++
++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */
++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */
++
++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */
++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */
++
++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC4.CTRLD bit masks and bit positions */
++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC4_EVACT_gp 5 /* Event Action group position. */
++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC4.CTRLE bit masks and bit positions */
++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */
++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */
++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */
++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */
++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */
++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */
++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */
++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */
++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */
++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */
++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */
++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */
++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */
++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */
++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */
++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */
++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC4.CTRLF bit masks and bit positions */
++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */
++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */
++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */
++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */
++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */
++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */
++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC4.INTCTRLA bit masks and bit positions */
++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC4.INTCTRLB bit masks and bit positions */
++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */
++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */
++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */
++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */
++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */
++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */
++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC4.CTRLGCLR bit masks and bit positions */
++#define TC4_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC4_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC4_CMD_gm 0x0C /* Command group mask. */
++#define TC4_CMD_gp 2 /* Command group position. */
++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC4_CMD0_bp 2 /* Command bit 0 position. */
++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC4_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC4_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC4_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC4.CTRLGSET bit masks and bit positions */
++/* TC4_STOP Predefined. */
++/* TC4_STOP Predefined. */
++
++/* TC4_CMD Predefined. */
++/* TC4_CMD Predefined. */
++
++/* TC4_LUPD Predefined. */
++/* TC4_LUPD Predefined. */
++
++/* TC4_DIR Predefined. */
++/* TC4_DIR Predefined. */
++
++/* TC4.CTRLHCLR bit masks and bit positions */
++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC4.CTRLHSET bit masks and bit positions */
++/* TC4_CCDBV Predefined. */
++/* TC4_CCDBV Predefined. */
++
++/* TC4_CCCBV Predefined. */
++/* TC4_CCCBV Predefined. */
++
++/* TC4_CCBBV Predefined. */
++/* TC4_CCBBV Predefined. */
++
++/* TC4_CCABV Predefined. */
++/* TC4_CCABV Predefined. */
++
++/* TC4_PERBV Predefined. */
++/* TC4_PERBV Predefined. */
++
++/* TC4_LCCDBV Predefined. */
++/* TC4_LCCDBV Predefined. */
++
++/* TC4_LCCCBV Predefined. */
++/* TC4_LCCCBV Predefined. */
++
++/* TC4_LCCBBV Predefined. */
++/* TC4_LCCBBV Predefined. */
++
++/* TC4_LCCABV Predefined. */
++/* TC4_LCCABV Predefined. */
++
++/* TC4_LPERBV Predefined. */
++/* TC4_LPERBV Predefined. */
++
++/* TC4.INTFLAGS bit masks and bit positions */
++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* TC5.CTRLA bit masks and bit positions */
++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC5.CTRLB bit masks and bit positions */
++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC5.CTRLC bit masks and bit positions */
++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC5.CTRLD bit masks and bit positions */
++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC5_EVACT_gp 5 /* Event Action group position. */
++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC5.CTRLE bit masks and bit positions */
++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC5.CTRLF bit masks and bit positions */
++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC5.INTCTRLA bit masks and bit positions */
++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC5.INTCTRLB bit masks and bit positions */
++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC5.CTRLGCLR bit masks and bit positions */
++#define TC5_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC5_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC5_CMD_gm 0x0C /* Command group mask. */
++#define TC5_CMD_gp 2 /* Command group position. */
++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC5_CMD0_bp 2 /* Command bit 0 position. */
++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC5_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC5_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC5_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC5.CTRLGSET bit masks and bit positions */
++/* TC5_STOP Predefined. */
++/* TC5_STOP Predefined. */
++
++/* TC5_CMD Predefined. */
++/* TC5_CMD Predefined. */
++
++/* TC5_LUPD Predefined. */
++/* TC5_LUPD Predefined. */
++
++/* TC5_DIR Predefined. */
++/* TC5_DIR Predefined. */
++
++/* TC5.CTRLHCLR bit masks and bit positions */
++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC5.CTRLHSET bit masks and bit positions */
++/* TC5_CCBBV Predefined. */
++/* TC5_CCBBV Predefined. */
++
++/* TC5_CCABV Predefined. */
++/* TC5_CCABV Predefined. */
++
++/* TC5_PERBV Predefined. */
++/* TC5_PERBV Predefined. */
++
++/* TC5_LCCBBV Predefined. */
++/* TC5_LCCBBV Predefined. */
++
++/* TC5_LCCABV Predefined. */
++/* TC5_LCCABV Predefined. */
++
++/* TC5_LPERBV Predefined. */
++/* TC5_LPERBV Predefined. */
++
++/* TC5.INTFLAGS bit masks and bit positions */
++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* FAULT - Fault Extension */
++/* FAULT.CTRLA bit masks and bit positions */
++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */
++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */
++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */
++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */
++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */
++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */
++
++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */
++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */
++
++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */
++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */
++
++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */
++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */
++
++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */
++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */
++
++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */
++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */
++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */
++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */
++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */
++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */
++
++/* FAULT.CTRLB bit masks and bit positions */
++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */
++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */
++
++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */
++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */
++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */
++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */
++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */
++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */
++
++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */
++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */
++
++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */
++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */
++
++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */
++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */
++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */
++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */
++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */
++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */
++
++/* FAULT.CTRLC bit masks and bit positions */
++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */
++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */
++
++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */
++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */
++
++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */
++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */
++
++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */
++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */
++
++/* FAULT.CTRLD bit masks and bit positions */
++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */
++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */
++
++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */
++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */
++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */
++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */
++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */
++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */
++
++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */
++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */
++
++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */
++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */
++
++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */
++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */
++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */
++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */
++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */
++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */
++
++/* FAULT.CTRLE bit masks and bit positions */
++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */
++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */
++
++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */
++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */
++
++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */
++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */
++
++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */
++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */
++
++/* FAULT.STATUS bit masks and bit positions */
++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */
++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */
++
++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */
++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */
++
++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */
++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */
++
++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */
++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */
++
++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGCLR bit masks and bit positions */
++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */
++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */
++
++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */
++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */
++
++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */
++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */
++
++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGSET bit masks and bit positions */
++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */
++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */
++
++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */
++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */
++
++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */
++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */
++
++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */
++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */
++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */
++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */
++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */
++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */
++
++/* WEX - Waveform Extension */
++/* WEX.CTRL bit masks and bit positions */
++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */
++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */
++
++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */
++#define WEX_OTMX_gp 4 /* Output Matrix group position. */
++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */
++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */
++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */
++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */
++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */
++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */
++
++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */
++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */
++
++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */
++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */
++
++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */
++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */
++
++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */
++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */
++
++/* WEX.STATUSCLR bit masks and bit positions */
++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */
++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */
++
++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */
++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */
++
++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */
++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */
++
++/* WEX.STATUSSET bit masks and bit positions */
++/* WEX_SWAPBUF Predefined. */
++/* WEX_SWAPBUF Predefined. */
++
++/* WEX_PGVBUFV Predefined. */
++/* WEX_PGVBUFV Predefined. */
++
++/* WEX_PGOBUFV Predefined. */
++/* WEX_PGOBUFV Predefined. */
++
++/* WEX.SWAP bit masks and bit positions */
++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* WEX.SWAPBUF bit masks and bit positions */
++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* HIRES - High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */
++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */
++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */
++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */
++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */
++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */
++
++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */
++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */
++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */
++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */
++
++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */
++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */
++
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */
++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */
++
++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */
++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */
++
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.CTRLD bit masks and bit positions */
++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */
++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */
++
++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */
++
++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */
++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */
++
++/* SPI.CTRLB bit masks and bit positions */
++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */
++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */
++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */
++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */
++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */
++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */
++
++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */
++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */
++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */
++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */
++
++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */
++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */
++
++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */
++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */
++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */
++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */
++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */
++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */
++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */
++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */
++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */
++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */
++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */
++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */
++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */
++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT_vect_num 2
++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */
++
++/* EDMA interrupt vectors */
++#define EDMA_CH0_vect_num 3
++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */
++#define EDMA_CH1_vect_num 4
++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */
++#define EDMA_CH2_vect_num 5
++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */
++#define EDMA_CH3_vect_num 6
++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 7
++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 8
++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT_vect_num 9
++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 10
++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 11
++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */
++
++/* TCC4 interrupt vectors */
++#define TCC4_OVF_vect_num 12
++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */
++#define TCC4_ERR_vect_num 13
++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */
++#define TCC4_CCA_vect_num 14
++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */
++#define TCC4_CCB_vect_num 15
++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */
++#define TCC4_CCC_vect_num 16
++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */
++#define TCC4_CCD_vect_num 17
++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */
++
++/* TCC5 interrupt vectors */
++#define TCC5_OVF_vect_num 18
++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */
++#define TCC5_ERR_vect_num 19
++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */
++#define TCC5_CCA_vect_num 20
++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */
++#define TCC5_CCB_vect_num 21
++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 22
++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 23
++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 24
++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 25
++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 26
++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */
++#define NVM_SPM_vect_num 27
++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */
++
++/* XCL interrupt vectors */
++#define XCL_UNF_vect_num 28
++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */
++#define XCL_CC_vect_num 29
++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT_vect_num 30
++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 31
++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 32
++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 33
++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 34
++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT_vect_num 35
++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */
++
++/* TCD5 interrupt vectors */
++#define TCD5_OVF_vect_num 36
++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */
++#define TCD5_ERR_vect_num 37
++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */
++#define TCD5_CCA_vect_num 38
++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */
++#define TCD5_CCB_vect_num 39
++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 40
++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 41
++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 42
++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (43 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (20480)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (16384)
++#define APP_SECTION_PAGE_SIZE (128)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x3000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (128)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x4000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (128)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (10240)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (512)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (2048)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (512)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (128)
++#define USER_SIGNATURES_PAGE_SIZE (128)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (128)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHSTART PROGMEM_START
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 128
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 7
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* Fuse Byte 6 */
++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */
++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */
++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */
++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */
++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */
++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */
++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */
++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */
++#define FUSE6_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x94
++#define SIGNATURE_2 0x45
++
++
++#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox32e5.h avr-libc-1.8.0/include/avr/iox32e5.h
+--- avr-libc-1.8.0.orig/include/avr/iox32e5.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox32e5.h 2013-01-18 10:08:40.000000000 +0100
+@@ -0,0 +1,7559 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox32e5.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA32E5_H_INCLUDED
++#define _AVR_ATXMEGA32E5_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */
++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */
++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */
++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */
++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t WEXLOCK; /* WEX Lock */
++ register8_t FAULTLOCK; /* FAULT Lock */
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t reserved_0x03;
++ register8_t CLKOUT; /* Clock Out Register */
++ register8_t reserved_0x05;
++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */
++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */
++} PORTCFG_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* RTC Clock Output Port */
++typedef enum PORTCFG_RTCCLKOUT_enum
++{
++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */
++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */
++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */
++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */
++} PORTCFG_RTCCLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */
++} PORTCFG_CLKOUT_t;
++
++/* Analog Comparator Output Port */
++typedef enum PORTCFG_ACOUT_enum
++{
++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */
++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */
++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */
++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */
++} PORTCFG_ACOUT_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */
++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EDMA - Enhanced DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* EDMA Channel */
++typedef struct EDMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control A */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */
++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ register8_t reserved_0x05;
++ register8_t TRFCNTL; /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */
++ register8_t TRFCNTH; /* Channel Block Transfer Count High for Standard Channels Only */
++ register8_t ADDRL; /* Channel Memory Address Low for Peripheral Ch., or Channel Source Address Low for Standard Ch. */
++ register8_t ADDRH; /* Channel Memory Address High for Peripheral Ch., or Channel Source Address High for Standard Ch. */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDRL; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t DESTADDRH; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} EDMA_CH_t;
++
++
++/* Enhanced DMA Controller */
++typedef struct EDMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ EDMA_CH_t CH0; /* EDMA Channel 0 */
++ EDMA_CH_t CH1; /* EDMA Channel 1 */
++ EDMA_CH_t CH2; /* EDMA Channel 2 */
++ EDMA_CH_t CH3; /* EDMA Channel 3 */
++} EDMA_t;
++
++/* Channel mode */
++typedef enum EDMA_CHMODE_enum
++{
++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */
++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */
++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */
++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */
++} EDMA_CHMODE_t;
++
++/* Double buffer mode */
++typedef enum EDMA_DBUFMODE_enum
++{
++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */
++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */
++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */
++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */
++} EDMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum EDMA_PRIMODE_enum
++{
++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */
++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */
++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */
++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */
++} EDMA_PRIMODE_t;
++
++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */
++typedef enum EDMA_CH_RELOAD_enum
++{
++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */
++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */
++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */
++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */
++} EDMA_CH_RELOAD_t;
++
++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */
++typedef enum EDMA_CH_DIR_enum
++{
++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */
++} EDMA_CH_DIR_t;
++
++/* Destination addressing mode */
++typedef enum EDMA_CH_DESTDIR_enum
++{
++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */
++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */
++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */
++} EDMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum EDMA_CH_TRIGSRC_enum
++{
++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */
++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */
++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */
++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */
++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */
++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */
++} EDMA_CH_TRIGSRC_t;
++
++/* Interrupt level */
++typedef enum EDMA_CH_INTLVL_enum
++{
++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */
++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */
++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */
++} EDMA_CH_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++ register8_t DFCTRL; /* Digital Filter Control Register */
++} EVSYS_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */
++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */
++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */
++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */
++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */
++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */
++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */
++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */
++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */
++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */
++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */
++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */
++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */
++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */
++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */
++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */
++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */
++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */
++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */
++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<0), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<0), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<0), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<0), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Prescaler Filter */
++typedef enum EVSYS_PRESCFILT_enum
++{
++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */
++ EVSYS_PRESCFILT_CH15_gc = (0x08<<4), /* Enable prescaler filter for either channel 1 or 5 */
++ EVSYS_PRESCFILT_CH26_gc = (0x40<<4), /* Enable prescaler filter for either channel 2 or 6 */
++ EVSYS_PRESCFILT_CH37_gc = (0x3E8<<4), /* Enable prescaler filter for either channel 3 or 7 */
++} EVSYS_PRESCFILT_t;
++
++/* Prescaler */
++typedef enum EVSYS_PRESCALER_enum
++{
++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */
++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */
++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */
++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */
++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */
++} EVSYS_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t CORRCTRL; /* Correction Control Register */
++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */
++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */
++ register8_t GAINCORR0; /* Gain Correction Register 0 */
++ register8_t GAINCORR1; /* Gain Correction Register 1 */
++ register8_t AVGCTRL; /* Average Control Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Current Limitation */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */
++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */
++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */
++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */
++} ADC_CURRLIMIT_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */
++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */
++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */
++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */
++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */
++} ADC_CH_INPUTMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection when gain on 4 LSB pins */
++typedef enum ADC_CH_MUXNEGL_enum
++{
++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */
++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */
++} ADC_CH_MUXNEGL_t;
++
++/* Negative input multiplexer selection when gain on 4 MSB pins */
++typedef enum ADC_CH_MUXNEGH_enum
++{
++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */
++ ADC_CH_MUXNEGH_INTGND_gc = (0x04<<0), /* Internal ground */
++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */
++} ADC_CH_MUXNEGH_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++} ADC_CH_MUXNEG_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Averaged Number of Samples */
++typedef enum ADC_SAMPNUM_enum
++{
++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */
++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */
++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */
++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */
++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */
++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */
++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */
++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */
++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */
++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */
++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */
++} ADC_SAMPNUM_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Clounter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t CALIB; /* Calibration Register */
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++XCL - XMEGA Custom Logic
++--------------------------------------------------------------------------
++*/
++
++/* XMEGA Custom Logic */
++typedef struct XCL_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t PLC; /* Peripheral Lenght Control Register */
++ register8_t CNTL; /* Counter Register Low */
++ register8_t CNTH; /* Counter Register High */
++ register8_t CMPL; /* Compare Register Low */
++ register8_t CMPH; /* Compare Register High */
++ register8_t PERCAPTL; /* Period or Capture Register Low */
++ register8_t PERCAPTH; /* Period or Capture Register High */
++} XCL_t;
++
++/* LUT0 Output Enable */
++typedef enum XCL_LUTOUTEN_enum
++{
++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */
++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */
++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */
++} XCL_LUTOUTEN_t;
++
++/* Port Selection */
++typedef enum XCL_PORTSEL_enum
++{
++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */
++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */
++} XCL_PORTSEL_t;
++
++/* LUT Configuration */
++typedef enum XCL_LUTCONF_enum
++{
++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */
++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */
++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */
++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */
++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */
++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */
++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */
++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */
++} XCL_LUTCONF_t;
++
++/* Input Selection */
++typedef enum XCL_INSEL_enum
++{
++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */
++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */
++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */
++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */
++} XCL_INSEL_t;
++
++/* Delay Configuration on LUT */
++typedef enum XCL_DLYCONF_enum
++{
++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */
++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */
++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */
++} XCL_DLYCONF_t;
++
++/* Delay Selection */
++typedef enum XCL_DLYSEL_enum
++{
++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */
++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */
++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */
++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */
++} XCL_DLYSEL_t;
++
++/* Clock Selection */
++typedef enum XCL_CLKSEL_enum
++{
++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */
++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */
++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */
++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */
++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */
++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */
++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */
++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */
++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */
++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */
++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */
++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */
++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */
++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */
++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */
++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */
++} XCL_CLKSEL_t;
++
++/* Timer/Counter Command Selection */
++typedef enum XCL_CMDSEL_enum
++{
++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */
++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */
++} XCL_CMDSEL_t;
++
++/* Timer/Counter Selection */
++typedef enum XCL_TCSEL_enum
++{
++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */
++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */
++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */
++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */
++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */
++} XCL_TCSEL_t;
++
++/* Timer/Counter Mode */
++typedef enum XCL_TCMODE_enum
++{
++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */
++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */
++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */
++} XCL_TCMODE_t;
++
++/* Compare Output Value Timer */
++typedef enum XCL_CMPEN_enum
++{
++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */
++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */
++} XCL_CMPEN_t;
++
++/* Command Enable */
++typedef enum XCL_CMDEN_enum
++{
++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */
++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */
++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */
++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */
++} XCL_CMDEN_t;
++
++/* Timer/Counter Event Source Selection */
++typedef enum XCL_EVSRC_enum
++{
++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */
++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */
++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */
++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */
++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */
++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */
++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */
++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */
++} XCL_EVSRC_t;
++
++/* Timer/Counter Event Action Selection */
++typedef enum XCL_EVACT_enum
++{
++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */
++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */
++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */
++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */
++} XCL_EVACT_t;
++
++/* Underflow Interrupt level */
++typedef enum XCL_UNF_INTLVL_enum
++{
++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */
++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */
++} XCL_UNF_INTLVL_t;
++
++/* Compare/Capture Interrupt level */
++typedef enum XCL_CC_INTLVL_enum
++{
++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} XCL_CC_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTMASK; /* Port Interrupt Mask */
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt Level */
++typedef enum PORT_INTLVL_enum
++{
++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INTLVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 4 */
++typedef struct TC4_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC4_t;
++
++
++/* 16-bit Timer/Counter 5 */
++typedef struct TC5_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} TC5_t;
++
++/* Clock Selection */
++typedef enum TC45_CLKSEL_enum
++{
++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC45_BYTEM_enum
++{
++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */
++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */
++} TC45_BYTEM_t;
++
++/* Circular Enable Mode */
++typedef enum TC45_CIRCEN_enum
++{
++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */
++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */
++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */
++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */
++} TC45_CIRCEN_t;
++
++/* Waveform Generation Mode */
++typedef enum TC45_WGMODE_enum
++{
++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */
++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC45_WGMODE_t;
++
++/* Event Action */
++typedef enum TC45_EVACT_enum
++{
++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */
++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */
++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */
++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */
++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */
++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */
++} TC45_EVACT_t;
++
++/* Event Selection */
++typedef enum TC45_EVSEL_enum
++{
++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_EVSEL_t;
++
++/* Compare or Capture Channel A Mode */
++typedef enum TC45_CCAMODE_enum
++{
++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_CCAMODE_t;
++
++/* Compare or Capture Channel B Mode */
++typedef enum TC45_CCBMODE_enum
++{
++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_CCBMODE_t;
++
++/* Compare or Capture Channel C Mode */
++typedef enum TC45_CCCMODE_enum
++{
++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_CCCMODE_t;
++
++/* Compare or Capture Channel D Mode */
++typedef enum TC45_CCDMODE_enum
++{
++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_CCDMODE_t;
++
++/* Compare or Capture Low Channel A Mode */
++typedef enum TC45_LCCAMODE_enum
++{
++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_LCCAMODE_t;
++
++/* Compare or Capture Low Channel B Mode */
++typedef enum TC45_LCCBMODE_enum
++{
++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_LCCBMODE_t;
++
++/* Compare or Capture Low Channel C Mode */
++typedef enum TC45_LCCCMODE_enum
++{
++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_LCCCMODE_t;
++
++/* Compare or Capture Low Channel D Mode */
++typedef enum TC45_LCCDMODE_enum
++{
++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_LCCDMODE_t;
++
++/* Compare or Capture High Channel A Mode */
++typedef enum TC45_HCCAMODE_enum
++{
++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_HCCAMODE_t;
++
++/* Compare or Capture High Channel B Mode */
++typedef enum TC45_HCCBMODE_enum
++{
++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_HCCBMODE_t;
++
++/* Compare or Capture High Channel C Mode */
++typedef enum TC45_HCCCMODE_enum
++{
++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_HCCCMODE_t;
++
++/* Compare or Capture High Channel D Mode */
++typedef enum TC45_HCCDMODE_enum
++{
++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_HCCDMODE_t;
++
++/* Timer Trigger Restart Interrupt Level */
++typedef enum TC45_TRGINTLVL_enum
++{
++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_TRGINTLVL_t;
++
++/* Error Interrupt Level */
++typedef enum TC45_ERRINTLVL_enum
++{
++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC45_OVFINTLVL_enum
++{
++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_OVFINTLVL_t;
++
++/* Compare or Capture Channel A Interrupt Level */
++typedef enum TC45_CCAINTLVL_enum
++{
++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_CCAINTLVL_t;
++
++/* Compare or Capture Channel B Interrupt Level */
++typedef enum TC45_CCBINTLVL_enum
++{
++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_CCBINTLVL_t;
++
++/* Compare or Capture Channel C Interrupt Level */
++typedef enum TC45_CCCINTLVL_enum
++{
++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_CCCINTLVL_t;
++
++/* Compare or Capture Channel D Interrupt Level */
++typedef enum TC45_CCDINTLVL_enum
++{
++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_CCDINTLVL_t;
++
++/* Compare or Capture Low Channel A Interrupt Level */
++typedef enum TC45_LCCAINTLVL_enum
++{
++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_LCCAINTLVL_t;
++
++/* Compare or Capture Low Channel B Interrupt Level */
++typedef enum TC45_LCCBINTLVL_enum
++{
++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_LCCBINTLVL_t;
++
++/* Compare or Capture Low Channel C Interrupt Level */
++typedef enum TC45_LCCCINTLVL_enum
++{
++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_LCCCINTLVL_t;
++
++/* Compare or Capture Low Channel D Interrupt Level */
++typedef enum TC45_LCCDINTLVL_enum
++{
++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_LCCDINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC45_CMD_enum
++{
++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC45_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++FAULT - Fault Extension
++--------------------------------------------------------------------------
++*/
++
++/* Fault Extension */
++typedef struct FAULT_struct
++{
++ register8_t CTRLA; /* Control A Register */
++ register8_t CTRLB; /* Control B Register */
++ register8_t CTRLC; /* Control C Register */
++ register8_t CTRLD; /* Control D Register */
++ register8_t CTRLE; /* Control E Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G set */
++} FAULT_t;
++
++/* Ramp Mode Selection */
++typedef enum FAULT_RAMP_enum
++{
++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */
++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */
++} FAULT_RAMP_t;
++
++/* Fault E Input Source Selection */
++typedef enum FAULT_SRCE_enum
++{
++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */
++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */
++} FAULT_SRCE_t;
++
++/* Fault A Halt Action Selection */
++typedef enum FAULT_HALTA_enum
++{
++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTA_t;
++
++/* Fault A Source Selection */
++typedef enum FAULT_SRCA_enum
++{
++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */
++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */
++} FAULT_SRCA_t;
++
++/* Fault B Halt Action Selection */
++typedef enum FAULT_HALTB_enum
++{
++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTB_t;
++
++/* Fault B Source Selection */
++typedef enum FAULT_SRCB_enum
++{
++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */
++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */
++} FAULT_SRCB_t;
++
++/* Channel index Command */
++typedef enum FAULT_IDXCMD_enum
++{
++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */
++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */
++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */
++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */
++} FAULT_IDXCMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++WEX - Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Waveform Extension */
++typedef struct WEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */
++ register8_t DTLS; /* Dead-time Low Side Register */
++ register8_t DTHS; /* Dead-time High Side Register */
++ register8_t STATUSCLR; /* Status Clear Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t SWAP; /* Swap Register */
++ register8_t PGO; /* Pattern Generation Override Register */
++ register8_t PGV; /* Pattern Generation Value Register */
++ register8_t reserved_0x09;
++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */
++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */
++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t OUTOVDIS; /* Output Override Disable Register */
++} WEX_t;
++
++/* Output Matrix Mode */
++typedef enum WEX_OTMX_enum
++{
++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */
++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */
++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */
++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */
++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */
++} WEX_OTMX_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register A */
++} HIRES_t;
++
++/* High Resolution Plus Mode */
++typedef enum HIRES_HRPLUS_enum
++{
++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */
++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */
++ HIRES_HRPLUS_HRP5_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 5 */
++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */
++} HIRES_HRPLUS_t;
++
++/* High Resolution Mode */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */
++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */
++ HIRES_HREN_HRP5_gc = (0x03<<0), /* Hi-Res enabled on Timer 5 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Start Interrupt level */
++typedef enum USART_RXSINTLVL_enum
++{
++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_RXSINTLVL_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++/* Encoding and Decoding Type */
++typedef enum USART_DECTYPE_enum
++{
++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */
++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */
++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */
++} USART_DECTYPE_t;
++
++/* XCL LUT Action */
++typedef enum USART_LUTACT_enum
++{
++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */
++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */
++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */
++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */
++} USART_LUTACT_t;
++
++/* XCL Peripheral Counter Action */
++typedef enum USART_PECACT_enum
++{
++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */
++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */
++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */
++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */
++} USART_PECACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface with Buffer Modes */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++ register8_t CTRLB; /* Control Register B */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++/* Buffer Modes */
++typedef enum SPI_BUFMODE_enum
++{
++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */
++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */
++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */
++} SPI_BUFMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++ register8_t FUSEBYTE6; /* Fault State */
++} NVM_FUSES_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BOD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */
++ register8_t reserved_0x01;
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */
++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */
++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */
++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */
++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */
++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++#define OSC_RC8MCAL _SFR_MEM8(0x0057)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_WEXLOCK _SFR_MEM8(0x0099)
++#define MCU_FAULTLOCK _SFR_MEM8(0x009A)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6)
++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EDMA - Enhanced DMA Controller */
++#define EDMA_CTRL _SFR_MEM8(0x0100)
++#define EDMA_INTFLAGS _SFR_MEM8(0x0103)
++#define EDMA_STATUS _SFR_MEM8(0x0104)
++#define EDMA_TEMP _SFR_MEM8(0x0106)
++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113)
++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114)
++#define EDMA_CH0_TRFCNTL _SFR_MEM8(0x0116)
++#define EDMA_CH0_TRFCNTH _SFR_MEM8(0x0117)
++#define EDMA_CH0_ADDRL _SFR_MEM8(0x0118)
++#define EDMA_CH0_ADDRH _SFR_MEM8(0x0119)
++#define EDMA_CH0_DESTADDRL _SFR_MEM8(0x011C)
++#define EDMA_CH0_DESTADDRH _SFR_MEM8(0x011D)
++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123)
++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124)
++#define EDMA_CH1_TRFCNTL _SFR_MEM8(0x0126)
++#define EDMA_CH1_TRFCNTH _SFR_MEM8(0x0127)
++#define EDMA_CH1_ADDRL _SFR_MEM8(0x0128)
++#define EDMA_CH1_ADDRH _SFR_MEM8(0x0129)
++#define EDMA_CH1_DESTADDRL _SFR_MEM8(0x012C)
++#define EDMA_CH1_DESTADDRH _SFR_MEM8(0x012D)
++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133)
++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134)
++#define EDMA_CH2_TRFCNTL _SFR_MEM8(0x0136)
++#define EDMA_CH2_TRFCNTH _SFR_MEM8(0x0137)
++#define EDMA_CH2_ADDRL _SFR_MEM8(0x0138)
++#define EDMA_CH2_ADDRH _SFR_MEM8(0x0139)
++#define EDMA_CH2_DESTADDRL _SFR_MEM8(0x013C)
++#define EDMA_CH2_DESTADDRH _SFR_MEM8(0x013D)
++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143)
++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144)
++#define EDMA_CH3_TRFCNTL _SFR_MEM8(0x0146)
++#define EDMA_CH3_TRFCNTH _SFR_MEM8(0x0147)
++#define EDMA_CH3_ADDRL _SFR_MEM8(0x0148)
++#define EDMA_CH3_ADDRH _SFR_MEM8(0x0149)
++#define EDMA_CH3_DESTADDRL _SFR_MEM8(0x014C)
++#define EDMA_CH3_DESTADDRH _SFR_MEM8(0x014D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++#define EVSYS_DFCTRL _SFR_MEM8(0x0192)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227)
++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228)
++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229)
++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A)
++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B)
++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACA_CTRLA _SFR_MEM8(0x0300)
++#define DACA_CTRLB _SFR_MEM8(0x0301)
++#define DACA_CTRLC _SFR_MEM8(0x0302)
++#define DACA_EVCTRL _SFR_MEM8(0x0303)
++#define DACA_TIMCTRL _SFR_MEM8(0x0304)
++#define DACA_STATUS _SFR_MEM8(0x0305)
++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308)
++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309)
++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A)
++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B)
++#define DACA_CH0DATA _SFR_MEM16(0x0318)
++#define DACA_CH1DATA _SFR_MEM16(0x031A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++#define ACA_CURRCTRL _SFR_MEM8(0x0388)
++#define ACA_CURRCALIB _SFR_MEM8(0x0389)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CALIB _SFR_MEM8(0x0406)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* XCL - XMEGA Custom Logic */
++#define XCL_CTRLA _SFR_MEM8(0x0460)
++#define XCL_CTRLB _SFR_MEM8(0x0461)
++#define XCL_CTRLC _SFR_MEM8(0x0462)
++#define XCL_CTRLD _SFR_MEM8(0x0463)
++#define XCL_CTRLE _SFR_MEM8(0x0464)
++#define XCL_CTRLF _SFR_MEM8(0x0465)
++#define XCL_CTRLG _SFR_MEM8(0x0466)
++#define XCL_INTCTRL _SFR_MEM8(0x0467)
++#define XCL_INTFLAGS _SFR_MEM8(0x0468)
++#define XCL_PLC _SFR_MEM8(0x0469)
++#define XCL_CNTL _SFR_MEM8(0x046A)
++#define XCL_CNTH _SFR_MEM8(0x046B)
++#define XCL_CMPL _SFR_MEM8(0x046C)
++#define XCL_CMPH _SFR_MEM8(0x046D)
++#define XCL_PERCAPTL _SFR_MEM8(0x046E)
++#define XCL_PERCAPTH _SFR_MEM8(0x046F)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INTMASK _SFR_MEM8(0x060A)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INTMASK _SFR_MEM8(0x064A)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INTMASK _SFR_MEM8(0x066A)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INTMASK _SFR_MEM8(0x07EA)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC4 - 16-bit Timer/Counter 4 */
++#define TCC4_CTRLA _SFR_MEM8(0x0800)
++#define TCC4_CTRLB _SFR_MEM8(0x0801)
++#define TCC4_CTRLC _SFR_MEM8(0x0802)
++#define TCC4_CTRLD _SFR_MEM8(0x0803)
++#define TCC4_CTRLE _SFR_MEM8(0x0804)
++#define TCC4_CTRLF _SFR_MEM8(0x0805)
++#define TCC4_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC4_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808)
++#define TCC4_CTRLGSET _SFR_MEM8(0x0809)
++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A)
++#define TCC4_CTRLHSET _SFR_MEM8(0x080B)
++#define TCC4_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC4_TEMP _SFR_MEM8(0x080F)
++#define TCC4_CNT _SFR_MEM16(0x0820)
++#define TCC4_PER _SFR_MEM16(0x0826)
++#define TCC4_CCA _SFR_MEM16(0x0828)
++#define TCC4_CCB _SFR_MEM16(0x082A)
++#define TCC4_CCC _SFR_MEM16(0x082C)
++#define TCC4_CCD _SFR_MEM16(0x082E)
++#define TCC4_PERBUF _SFR_MEM16(0x0836)
++#define TCC4_CCABUF _SFR_MEM16(0x0838)
++#define TCC4_CCBBUF _SFR_MEM16(0x083A)
++#define TCC4_CCCBUF _SFR_MEM16(0x083C)
++#define TCC4_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCC5_CTRLA _SFR_MEM8(0x0840)
++#define TCC5_CTRLB _SFR_MEM8(0x0841)
++#define TCC5_CTRLC _SFR_MEM8(0x0842)
++#define TCC5_CTRLD _SFR_MEM8(0x0843)
++#define TCC5_CTRLE _SFR_MEM8(0x0844)
++#define TCC5_CTRLF _SFR_MEM8(0x0845)
++#define TCC5_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC5_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848)
++#define TCC5_CTRLGSET _SFR_MEM8(0x0849)
++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A)
++#define TCC5_CTRLHSET _SFR_MEM8(0x084B)
++#define TCC5_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC5_TEMP _SFR_MEM8(0x084F)
++#define TCC5_CNT _SFR_MEM16(0x0860)
++#define TCC5_PER _SFR_MEM16(0x0866)
++#define TCC5_CCA _SFR_MEM16(0x0868)
++#define TCC5_CCB _SFR_MEM16(0x086A)
++#define TCC5_PERBUF _SFR_MEM16(0x0876)
++#define TCC5_CCABUF _SFR_MEM16(0x0878)
++#define TCC5_CCBBUF _SFR_MEM16(0x087A)
++
++/* FAULT - Fault Extension */
++#define FAULTC4_CTRLA _SFR_MEM8(0x0880)
++#define FAULTC4_CTRLB _SFR_MEM8(0x0881)
++#define FAULTC4_CTRLC _SFR_MEM8(0x0882)
++#define FAULTC4_CTRLD _SFR_MEM8(0x0883)
++#define FAULTC4_CTRLE _SFR_MEM8(0x0884)
++#define FAULTC4_STATUS _SFR_MEM8(0x0885)
++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886)
++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887)
++
++/* FAULT - Fault Extension */
++#define FAULTC5_CTRLA _SFR_MEM8(0x0890)
++#define FAULTC5_CTRLB _SFR_MEM8(0x0891)
++#define FAULTC5_CTRLC _SFR_MEM8(0x0892)
++#define FAULTC5_CTRLD _SFR_MEM8(0x0893)
++#define FAULTC5_CTRLE _SFR_MEM8(0x0894)
++#define FAULTC5_STATUS _SFR_MEM8(0x0895)
++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896)
++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897)
++
++/* WEX - Waveform Extension */
++#define WEXC_CTRL _SFR_MEM8(0x08A0)
++#define WEXC_DTBOTH _SFR_MEM8(0x08A1)
++#define WEXC_DTLS _SFR_MEM8(0x08A2)
++#define WEXC_DTHS _SFR_MEM8(0x08A3)
++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4)
++#define WEXC_STATUSSET _SFR_MEM8(0x08A5)
++#define WEXC_SWAP _SFR_MEM8(0x08A6)
++#define WEXC_PGO _SFR_MEM8(0x08A7)
++#define WEXC_PGV _SFR_MEM8(0x08A8)
++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA)
++#define WEXC_PGOBUF _SFR_MEM8(0x08AB)
++#define WEXC_PGVBUF _SFR_MEM8(0x08AC)
++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x08B0)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08C0)
++#define USARTC0_STATUS _SFR_MEM8(0x08C1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08C2)
++#define USARTC0_CTRLB _SFR_MEM8(0x08C3)
++#define USARTC0_CTRLC _SFR_MEM8(0x08C4)
++#define USARTC0_CTRLD _SFR_MEM8(0x08C5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7)
++
++/* SPI - Serial Peripheral Interface with Buffer Modes */
++#define SPIC_CTRL _SFR_MEM8(0x08E0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08E1)
++#define SPIC_STATUS _SFR_MEM8(0x08E2)
++#define SPIC_DATA _SFR_MEM8(0x08E3)
++#define SPIC_CTRLB _SFR_MEM8(0x08E4)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCD5_CTRLA _SFR_MEM8(0x0940)
++#define TCD5_CTRLB _SFR_MEM8(0x0941)
++#define TCD5_CTRLC _SFR_MEM8(0x0942)
++#define TCD5_CTRLD _SFR_MEM8(0x0943)
++#define TCD5_CTRLE _SFR_MEM8(0x0944)
++#define TCD5_CTRLF _SFR_MEM8(0x0945)
++#define TCD5_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD5_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948)
++#define TCD5_CTRLGSET _SFR_MEM8(0x0949)
++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A)
++#define TCD5_CTRLHSET _SFR_MEM8(0x094B)
++#define TCD5_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD5_TEMP _SFR_MEM8(0x094F)
++#define TCD5_CNT _SFR_MEM16(0x0960)
++#define TCD5_PER _SFR_MEM16(0x0966)
++#define TCD5_CCA _SFR_MEM16(0x0968)
++#define TCD5_CCB _SFR_MEM16(0x096A)
++#define TCD5_PERBUF _SFR_MEM16(0x0976)
++#define TCD5_CCABUF _SFR_MEM16(0x0978)
++#define TCD5_CCBBUF _SFR_MEM16(0x097A)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09C0)
++#define USARTD0_STATUS _SFR_MEM8(0x09C1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09C2)
++#define USARTD0_CTRLB _SFR_MEM8(0x09C3)
++#define USARTD0_CTRLC _SFR_MEM8(0x09C4)
++#define USARTD0_CTRLD _SFR_MEM8(0x09C5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */
++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */
++
++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */
++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */
++
++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */
++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */
++
++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */
++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */
++
++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */
++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */
++
++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */
++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */
++
++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */
++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */
++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C WEX bit position. */
++
++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */
++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */
++
++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */
++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC5 Predefined. */
++/* PR_TC5 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */
++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */
++
++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */
++
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */
++
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++/* OSC.RC8MCAL bit masks and bit positions */
++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */
++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */
++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */
++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */
++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */
++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */
++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */
++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */
++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */
++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */
++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */
++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */
++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */
++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */
++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */
++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */
++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */
++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.WEXLOCK bit masks and bit positions */
++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */
++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */
++
++/* MCU.FAULTLOCK bit masks and bit positions */
++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */
++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */
++
++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */
++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.CLKOUT bit masks and bit positions */
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */
++
++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */
++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */
++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */
++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */
++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */
++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */
++
++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
++
++/* PORTCFG.ACEVOUT bit masks and bit positions */
++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */
++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */
++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */
++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */
++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */
++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */
++
++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */
++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */
++
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */
++
++/* PORTCFG.SRLCTRL bit masks and bit positions */
++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */
++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */
++
++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */
++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */
++
++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */
++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */
++
++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */
++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EDMA - Enhanced DMA Controller */
++/* EDMA.CTRL bit masks and bit positions */
++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define EDMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define EDMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */
++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */
++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */
++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */
++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */
++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */
++
++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */
++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */
++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */
++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */
++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */
++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */
++
++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */
++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */
++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */
++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */
++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */
++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */
++
++/* EDMA.INTFLAGS bit masks and bit positions */
++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* EDMA.STATUS bit masks and bit positions */
++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */
++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */
++
++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */
++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */
++
++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */
++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */
++
++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */
++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */
++
++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */
++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */
++
++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */
++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */
++
++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */
++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */
++
++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */
++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */
++
++/* EDMA_CH.CTRLA bit masks and bit positions */
++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */
++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */
++
++/* EDMA_CH.CTRLB bit masks and bit positions */
++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */
++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */
++
++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */
++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */
++
++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */
++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */
++
++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */
++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */
++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */
++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */
++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */
++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */
++
++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */
++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */
++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */
++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */
++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */
++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */
++
++/* EDMA_CH.ADDRCTRL bit masks and bit positions */
++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */
++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */
++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */
++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */
++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */
++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */
++
++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */
++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */
++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */
++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */
++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */
++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */
++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */
++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */
++
++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */
++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */
++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */
++
++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */
++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */
++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */
++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */
++
++/* EDMA_CH.TRIGSRC bit masks and bit positions */
++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */
++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */
++
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.DFCTRL bit masks and bit positions */
++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */
++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */
++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */
++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */
++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */
++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */
++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */
++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */
++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */
++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */
++
++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */
++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */
++
++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */
++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */
++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */
++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */
++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */
++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */
++
++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */
++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */
++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */
++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */
++
++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */
++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */
++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */
++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */
++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */
++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */
++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */
++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */
++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */
++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */
++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */
++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */
++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */
++
++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */
++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */
++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */
++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */
++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */
++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */
++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */
++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */
++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */
++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */
++
++/* ADC_CH.CORRCTRL bit masks and bit positions */
++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */
++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */
++
++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */
++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */
++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */
++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */
++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */
++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */
++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */
++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */
++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */
++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */
++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.GAINCORR1 bit masks and bit positions */
++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */
++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */
++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */
++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */
++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */
++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */
++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */
++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */
++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */
++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.AVGCTRL bit masks and bit positions */
++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */
++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */
++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */
++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */
++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */
++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */
++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */
++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */
++
++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */
++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */
++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */
++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */
++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */
++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */
++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */
++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */
++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */
++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */
++#define ADC_START_bp 2 /* Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Clounter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */
++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */
++
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* RTC.CALIB bit masks and bit positions */
++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */
++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */
++
++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */
++#define RTC_ERROR_gp 0 /* Error Value group position. */
++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */
++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */
++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */
++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */
++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */
++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */
++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */
++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */
++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */
++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */
++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */
++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */
++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */
++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */
++
++/* XCL - XMEGA Custom Logic */
++/* XCL.CTRLA bit masks and bit positions */
++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */
++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */
++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */
++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */
++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */
++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */
++
++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */
++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */
++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */
++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */
++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */
++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */
++
++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */
++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */
++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */
++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */
++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */
++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */
++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */
++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */
++
++/* XCL.CTRLB bit masks and bit positions */
++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */
++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */
++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */
++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */
++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */
++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */
++
++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */
++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */
++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */
++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */
++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */
++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */
++
++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */
++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */
++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */
++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */
++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */
++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */
++
++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */
++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */
++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */
++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */
++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */
++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */
++
++/* XCL.CTRLC bit masks and bit positions */
++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */
++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */
++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */
++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */
++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */
++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */
++
++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */
++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */
++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */
++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */
++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */
++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */
++
++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */
++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */
++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */
++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */
++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */
++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */
++
++/* XCL.CTRLD bit masks and bit positions */
++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */
++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */
++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */
++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */
++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */
++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */
++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */
++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */
++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */
++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */
++
++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */
++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */
++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */
++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */
++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */
++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */
++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */
++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */
++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */
++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */
++
++/* XCL.CTRLE bit masks and bit positions */
++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */
++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */
++
++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */
++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */
++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */
++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */
++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */
++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */
++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */
++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */
++
++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */
++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* XCL.CTRLF bit masks and bit positions */
++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */
++#define XCL_CMDEN_gp 6 /* Command Enable group position. */
++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */
++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */
++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */
++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */
++
++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */
++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */
++
++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */
++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */
++
++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */
++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */
++
++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */
++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */
++
++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */
++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */
++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */
++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */
++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */
++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */
++
++/* XCL.CTRLG bit masks and bit positions */
++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */
++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */
++
++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */
++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */
++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */
++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */
++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */
++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */
++
++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */
++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */
++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */
++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */
++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */
++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */
++
++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */
++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */
++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */
++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */
++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */
++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */
++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */
++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */
++
++/* XCL.INTCTRL bit masks and bit positions */
++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */
++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */
++
++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */
++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */
++
++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */
++
++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */
++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */
++
++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */
++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */
++
++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */
++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */
++
++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */
++
++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */
++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */
++
++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */
++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */
++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */
++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */
++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */
++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */
++
++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */
++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */
++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */
++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */
++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */
++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */
++
++/* XCL.INTFLAGS bit masks and bit positions */
++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */
++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */
++
++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */
++
++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */
++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */
++
++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */
++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */
++
++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */
++
++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */
++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */
++
++/* XCL.PLC bit masks and bit positions */
++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */
++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */
++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */
++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */
++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */
++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */
++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */
++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */
++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */
++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */
++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */
++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */
++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */
++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */
++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */
++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */
++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */
++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */
++
++/* XCL.CNTL bit masks and bit positions */
++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */
++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */
++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */
++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */
++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */
++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */
++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */
++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */
++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */
++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */
++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */
++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */
++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */
++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */
++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */
++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */
++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */
++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */
++
++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */
++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */
++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */
++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */
++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */
++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */
++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */
++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */
++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */
++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */
++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */
++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */
++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */
++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */
++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */
++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */
++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */
++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */
++
++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */
++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */
++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */
++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */
++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */
++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */
++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */
++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */
++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */
++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */
++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */
++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */
++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */
++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */
++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */
++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */
++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */
++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */
++
++/* XCL.CNTH bit masks and bit positions */
++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */
++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */
++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */
++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */
++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */
++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */
++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */
++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */
++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */
++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */
++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */
++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */
++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */
++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */
++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */
++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */
++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */
++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */
++
++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */
++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */
++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */
++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */
++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */
++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */
++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */
++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */
++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */
++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */
++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */
++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */
++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */
++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */
++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */
++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */
++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */
++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */
++
++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */
++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */
++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */
++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */
++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */
++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */
++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */
++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */
++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */
++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */
++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */
++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */
++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */
++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */
++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */
++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */
++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */
++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */
++
++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */
++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */
++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */
++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */
++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */
++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */
++
++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */
++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */
++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */
++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */
++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */
++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */
++
++/* XCL.CMPL bit masks and bit positions */
++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */
++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */
++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */
++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */
++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */
++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */
++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */
++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */
++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */
++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */
++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */
++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */
++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */
++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */
++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */
++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */
++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */
++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */
++
++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */
++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */
++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */
++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */
++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */
++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */
++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */
++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */
++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */
++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */
++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */
++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */
++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */
++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */
++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */
++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */
++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */
++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */
++
++/* XCL.CMPH bit masks and bit positions */
++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */
++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */
++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */
++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */
++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */
++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */
++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */
++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */
++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */
++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */
++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */
++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */
++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */
++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */
++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */
++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */
++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */
++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */
++
++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */
++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */
++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */
++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */
++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */
++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */
++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */
++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */
++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */
++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */
++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */
++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */
++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */
++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */
++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */
++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */
++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */
++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */
++
++/* XCL.PERCAPTL bit masks and bit positions */
++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */
++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */
++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */
++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */
++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */
++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */
++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */
++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */
++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */
++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */
++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */
++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */
++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */
++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */
++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */
++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */
++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */
++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */
++
++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */
++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */
++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */
++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */
++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */
++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */
++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */
++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */
++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */
++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */
++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */
++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */
++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */
++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */
++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */
++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */
++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */
++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */
++
++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */
++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */
++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */
++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */
++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */
++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */
++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */
++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */
++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */
++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */
++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */
++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */
++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */
++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */
++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */
++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */
++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */
++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */
++
++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */
++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */
++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */
++
++/* XCL.PERCAPTH bit masks and bit positions */
++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */
++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */
++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */
++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */
++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */
++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */
++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */
++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */
++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */
++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */
++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */
++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */
++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */
++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */
++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */
++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */
++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */
++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */
++
++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */
++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */
++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */
++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */
++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */
++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */
++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */
++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */
++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */
++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */
++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */
++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */
++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */
++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */
++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */
++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */
++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */
++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */
++
++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */
++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */
++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */
++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */
++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */
++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */
++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */
++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */
++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */
++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */
++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */
++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */
++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */
++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */
++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */
++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */
++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */
++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */
++
++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */
++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */
++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */
++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */
++
++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */
++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */
++
++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */
++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */
++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */
++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */
++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */
++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */
++
++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */
++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */
++
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* PORT - Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */
++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */
++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */
++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */
++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */
++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */
++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */
++
++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */
++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */
++
++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */
++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */
++
++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */
++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */
++
++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */
++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */
++
++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */
++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */
++
++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */
++#define PORT_USART0_bp 4 /* Usart0 bit position. */
++
++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */
++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */
++
++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */
++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */
++
++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */
++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */
++
++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */
++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC4.CTRLA bit masks and bit positions */
++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC4.CTRLB bit masks and bit positions */
++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC4.CTRLC bit masks and bit positions */
++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */
++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */
++
++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */
++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */
++
++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */
++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */
++
++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */
++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */
++
++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */
++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */
++
++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */
++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */
++
++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */
++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */
++
++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */
++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */
++
++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC4.CTRLD bit masks and bit positions */
++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC4_EVACT_gp 5 /* Event Action group position. */
++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC4.CTRLE bit masks and bit positions */
++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */
++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */
++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */
++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */
++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */
++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */
++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */
++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */
++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */
++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */
++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */
++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */
++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */
++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */
++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */
++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */
++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC4.CTRLF bit masks and bit positions */
++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */
++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */
++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */
++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */
++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */
++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */
++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC4.INTCTRLA bit masks and bit positions */
++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC4.INTCTRLB bit masks and bit positions */
++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */
++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */
++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */
++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */
++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */
++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */
++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC4.CTRLGCLR bit masks and bit positions */
++#define TC4_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC4_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC4_CMD_gm 0x0C /* Command group mask. */
++#define TC4_CMD_gp 2 /* Command group position. */
++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC4_CMD0_bp 2 /* Command bit 0 position. */
++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC4_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC4_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC4_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC4.CTRLGSET bit masks and bit positions */
++/* TC4_STOP Predefined. */
++/* TC4_STOP Predefined. */
++
++/* TC4_CMD Predefined. */
++/* TC4_CMD Predefined. */
++
++/* TC4_LUPD Predefined. */
++/* TC4_LUPD Predefined. */
++
++/* TC4_DIR Predefined. */
++/* TC4_DIR Predefined. */
++
++/* TC4.CTRLHCLR bit masks and bit positions */
++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC4.CTRLHSET bit masks and bit positions */
++/* TC4_CCDBV Predefined. */
++/* TC4_CCDBV Predefined. */
++
++/* TC4_CCCBV Predefined. */
++/* TC4_CCCBV Predefined. */
++
++/* TC4_CCBBV Predefined. */
++/* TC4_CCBBV Predefined. */
++
++/* TC4_CCABV Predefined. */
++/* TC4_CCABV Predefined. */
++
++/* TC4_PERBV Predefined. */
++/* TC4_PERBV Predefined. */
++
++/* TC4_LCCDBV Predefined. */
++/* TC4_LCCDBV Predefined. */
++
++/* TC4_LCCCBV Predefined. */
++/* TC4_LCCCBV Predefined. */
++
++/* TC4_LCCBBV Predefined. */
++/* TC4_LCCBBV Predefined. */
++
++/* TC4_LCCABV Predefined. */
++/* TC4_LCCABV Predefined. */
++
++/* TC4_LPERBV Predefined. */
++/* TC4_LPERBV Predefined. */
++
++/* TC4.INTFLAGS bit masks and bit positions */
++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* TC5.CTRLA bit masks and bit positions */
++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC5.CTRLB bit masks and bit positions */
++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC5.CTRLC bit masks and bit positions */
++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC5.CTRLD bit masks and bit positions */
++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC5_EVACT_gp 5 /* Event Action group position. */
++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC5.CTRLE bit masks and bit positions */
++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC5.CTRLF bit masks and bit positions */
++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC5.INTCTRLA bit masks and bit positions */
++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC5.INTCTRLB bit masks and bit positions */
++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC5.CTRLGCLR bit masks and bit positions */
++#define TC5_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC5_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC5_CMD_gm 0x0C /* Command group mask. */
++#define TC5_CMD_gp 2 /* Command group position. */
++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC5_CMD0_bp 2 /* Command bit 0 position. */
++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC5_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC5_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC5_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC5.CTRLGSET bit masks and bit positions */
++/* TC5_STOP Predefined. */
++/* TC5_STOP Predefined. */
++
++/* TC5_CMD Predefined. */
++/* TC5_CMD Predefined. */
++
++/* TC5_LUPD Predefined. */
++/* TC5_LUPD Predefined. */
++
++/* TC5_DIR Predefined. */
++/* TC5_DIR Predefined. */
++
++/* TC5.CTRLHCLR bit masks and bit positions */
++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC5.CTRLHSET bit masks and bit positions */
++/* TC5_CCBBV Predefined. */
++/* TC5_CCBBV Predefined. */
++
++/* TC5_CCABV Predefined. */
++/* TC5_CCABV Predefined. */
++
++/* TC5_PERBV Predefined. */
++/* TC5_PERBV Predefined. */
++
++/* TC5_LCCBBV Predefined. */
++/* TC5_LCCBBV Predefined. */
++
++/* TC5_LCCABV Predefined. */
++/* TC5_LCCABV Predefined. */
++
++/* TC5_LPERBV Predefined. */
++/* TC5_LPERBV Predefined. */
++
++/* TC5.INTFLAGS bit masks and bit positions */
++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* FAULT - Fault Extension */
++/* FAULT.CTRLA bit masks and bit positions */
++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */
++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */
++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */
++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */
++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */
++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */
++
++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */
++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */
++
++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */
++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */
++
++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */
++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */
++
++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */
++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */
++
++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */
++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */
++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */
++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */
++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */
++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */
++
++/* FAULT.CTRLB bit masks and bit positions */
++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */
++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */
++
++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */
++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */
++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */
++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */
++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */
++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */
++
++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */
++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */
++
++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */
++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */
++
++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */
++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */
++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */
++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */
++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */
++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */
++
++/* FAULT.CTRLC bit masks and bit positions */
++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */
++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */
++
++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */
++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */
++
++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */
++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */
++
++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */
++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */
++
++/* FAULT.CTRLD bit masks and bit positions */
++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */
++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */
++
++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */
++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */
++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */
++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */
++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */
++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */
++
++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */
++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */
++
++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */
++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */
++
++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */
++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */
++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */
++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */
++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */
++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */
++
++/* FAULT.CTRLE bit masks and bit positions */
++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */
++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */
++
++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */
++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */
++
++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */
++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */
++
++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */
++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */
++
++/* FAULT.STATUS bit masks and bit positions */
++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */
++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */
++
++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */
++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */
++
++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */
++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */
++
++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */
++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */
++
++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGCLR bit masks and bit positions */
++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */
++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */
++
++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */
++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */
++
++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */
++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */
++
++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGSET bit masks and bit positions */
++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */
++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */
++
++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */
++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */
++
++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */
++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */
++
++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */
++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */
++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */
++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */
++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */
++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */
++
++/* WEX - Waveform Extension */
++/* WEX.CTRL bit masks and bit positions */
++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */
++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */
++
++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */
++#define WEX_OTMX_gp 4 /* Output Matrix group position. */
++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */
++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */
++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */
++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */
++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */
++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */
++
++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */
++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */
++
++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */
++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */
++
++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */
++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */
++
++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */
++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */
++
++/* WEX.STATUSCLR bit masks and bit positions */
++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */
++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */
++
++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */
++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */
++
++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */
++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */
++
++/* WEX.STATUSSET bit masks and bit positions */
++/* WEX_SWAPBUF Predefined. */
++/* WEX_SWAPBUF Predefined. */
++
++/* WEX_PGVBUFV Predefined. */
++/* WEX_PGVBUFV Predefined. */
++
++/* WEX_PGOBUFV Predefined. */
++/* WEX_PGOBUFV Predefined. */
++
++/* WEX.SWAP bit masks and bit positions */
++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* WEX.SWAPBUF bit masks and bit positions */
++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* HIRES - High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */
++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */
++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */
++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */
++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */
++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */
++
++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */
++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */
++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */
++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */
++
++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */
++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */
++
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */
++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */
++
++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */
++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */
++
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.CTRLD bit masks and bit positions */
++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */
++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */
++
++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */
++
++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */
++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */
++
++/* SPI.CTRLB bit masks and bit positions */
++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */
++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */
++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */
++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */
++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */
++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */
++
++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */
++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */
++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */
++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */
++
++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */
++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */
++
++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */
++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */
++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */
++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */
++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */
++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */
++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */
++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */
++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */
++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */
++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */
++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */
++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */
++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT_vect_num 2
++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */
++
++/* EDMA interrupt vectors */
++#define EDMA_CH0_vect_num 3
++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */
++#define EDMA_CH1_vect_num 4
++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */
++#define EDMA_CH2_vect_num 5
++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */
++#define EDMA_CH3_vect_num 6
++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 7
++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 8
++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT_vect_num 9
++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 10
++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 11
++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */
++
++/* TCC4 interrupt vectors */
++#define TCC4_OVF_vect_num 12
++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */
++#define TCC4_ERR_vect_num 13
++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */
++#define TCC4_CCA_vect_num 14
++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */
++#define TCC4_CCB_vect_num 15
++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */
++#define TCC4_CCC_vect_num 16
++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */
++#define TCC4_CCD_vect_num 17
++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */
++
++/* TCC5 interrupt vectors */
++#define TCC5_OVF_vect_num 18
++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */
++#define TCC5_ERR_vect_num 19
++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */
++#define TCC5_CCA_vect_num 20
++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */
++#define TCC5_CCB_vect_num 21
++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 22
++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 23
++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 24
++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 25
++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 26
++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */
++#define NVM_SPM_vect_num 27
++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */
++
++/* XCL interrupt vectors */
++#define XCL_UNF_vect_num 28
++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */
++#define XCL_CC_vect_num 29
++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT_vect_num 30
++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 31
++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 32
++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 33
++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 34
++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT_vect_num 35
++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */
++
++/* TCD5 interrupt vectors */
++#define TCD5_OVF_vect_num 36
++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */
++#define TCD5_ERR_vect_num 37
++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */
++#define TCD5_CCA_vect_num 38
++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */
++#define TCD5_CCB_vect_num 39
++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 40
++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 41
++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 42
++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (43 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (36864)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (32768)
++#define APP_SECTION_PAGE_SIZE (128)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x7000)
++#define APPTABLE_SECTION_SIZE (4096)
++#define APPTABLE_SECTION_PAGE_SIZE (128)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x8000)
++#define BOOT_SECTION_SIZE (4096)
++#define BOOT_SECTION_PAGE_SIZE (128)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (12288)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (1024)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (4096)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (1024)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (128)
++#define USER_SIGNATURES_PAGE_SIZE (128)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (128)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHSTART PROGMEM_START
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 128
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 7
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* Fuse Byte 6 */
++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */
++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */
++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */
++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */
++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */
++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */
++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */
++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */
++#define FUSE6_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x95
++#define SIGNATURE_2 0x4C
++
++
++#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */
++
+diff -urN avr-libc-1.8.0.orig/include/avr/iox8e5.h avr-libc-1.8.0/include/avr/iox8e5.h
+--- avr-libc-1.8.0.orig/include/avr/iox8e5.h 1970-01-01 01:00:00.000000000 +0100
++++ avr-libc-1.8.0/include/avr/iox8e5.h 2013-01-18 10:08:40.000000000 +0100
+@@ -0,0 +1,7559 @@
++/*****************************************************************************
++ *
++ * Copyright (C) 2012 Atmel Corporation
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in
++ * the documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of the copyright holders nor the names of
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ ****************************************************************************/
++
++
++#ifndef _AVR_IO_H_
++# error "Include <avr/io.h> instead of this file."
++#endif
++
++#ifndef _AVR_IOXXX_H_
++# define _AVR_IOXXX_H_ "iox8e5.h"
++#else
++# error "Attempt to include more than one <avr/ioXXX.h> file."
++#endif
++
++#ifndef _AVR_ATXMEGA8E5_H_INCLUDED
++#define _AVR_ATXMEGA8E5_H_INCLUDED
++
++/* Ungrouped common registers */
++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++/* Deprecated */
++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
++
++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
++#define SREG _SFR_MEM8(0x003F) /* Status Register */
++
++/* C Language Only */
++#if !defined (__ASSEMBLER__)
++
++#include <stdint.h>
++
++typedef volatile uint8_t register8_t;
++typedef volatile uint16_t register16_t;
++typedef volatile uint32_t register32_t;
++
++
++#ifdef _WORDREGISTER
++#undef _WORDREGISTER
++#endif
++#define _WORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register16_t regname; \
++ struct \
++ { \
++ register8_t regname ## L; \
++ register8_t regname ## H; \
++ }; \
++ }
++
++#ifdef _DWORDREGISTER
++#undef _DWORDREGISTER
++#endif
++#define _DWORDREGISTER(regname) \
++ __extension__ union \
++ { \
++ register32_t regname; \
++ struct \
++ { \
++ register8_t regname ## 0; \
++ register8_t regname ## 1; \
++ register8_t regname ## 2; \
++ register8_t regname ## 3; \
++ }; \
++ }
++
++
++/*
++==========================================================================
++IO Module Structures
++==========================================================================
++*/
++
++
++/*
++--------------------------------------------------------------------------
++VPORT - Virtual Ports
++--------------------------------------------------------------------------
++*/
++
++/* Virtual Port */
++typedef struct VPORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t OUT; /* I/O Port Output */
++ register8_t IN; /* I/O Port Input */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++} VPORT_t;
++
++
++/*
++--------------------------------------------------------------------------
++XOCD - On-Chip Debug System
++--------------------------------------------------------------------------
++*/
++
++/* On-Chip Debug System */
++typedef struct OCD_struct
++{
++ register8_t OCDR0; /* OCD Register 0 */
++ register8_t OCDR1; /* OCD Register 1 */
++} OCD_t;
++
++
++/*
++--------------------------------------------------------------------------
++CPU - CPU
++--------------------------------------------------------------------------
++*/
++
++/* CCP signatures */
++typedef enum CCP_enum
++{
++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
++} CCP_t;
++
++
++/*
++--------------------------------------------------------------------------
++CLK - Clock System
++--------------------------------------------------------------------------
++*/
++
++/* Clock System */
++typedef struct CLK_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t PSCTRL; /* Prescaler Control Register */
++ register8_t LOCK; /* Lock register */
++ register8_t RTCCTRL; /* RTC Control Register */
++ register8_t reserved_0x04;
++} CLK_t;
++
++
++/* Power Reduction */
++typedef struct PR_struct
++{
++ register8_t PRGEN; /* General Power Reduction */
++ register8_t PRPA; /* Power Reduction Port A */
++ register8_t reserved_0x02;
++ register8_t PRPC; /* Power Reduction Port C */
++ register8_t PRPD; /* Power Reduction Port D */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++} PR_t;
++
++/* System Clock Selection */
++typedef enum CLK_SCLKSEL_enum
++{
++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */
++} CLK_SCLKSEL_t;
++
++/* Prescaler A Division Factor */
++typedef enum CLK_PSADIV_enum
++{
++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */
++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */
++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */
++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */
++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */
++} CLK_PSADIV_t;
++
++/* Prescaler B and C Division Factor */
++typedef enum CLK_PSBCDIV_enum
++{
++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
++} CLK_PSBCDIV_t;
++
++/* RTC Clock Source */
++typedef enum CLK_RTCSRC_enum
++{
++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */
++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */
++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
++} CLK_RTCSRC_t;
++
++
++/*
++--------------------------------------------------------------------------
++SLEEP - Sleep Controller
++--------------------------------------------------------------------------
++*/
++
++/* Sleep Controller */
++typedef struct SLEEP_struct
++{
++ register8_t CTRL; /* Control Register */
++} SLEEP_t;
++
++/* Sleep Mode */
++typedef enum SLEEP_SMODE_enum
++{
++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
++} SLEEP_SMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++OSC - Oscillator
++--------------------------------------------------------------------------
++*/
++
++/* Oscillator */
++typedef struct OSC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t XOSCCTRL; /* External Oscillator Control Register */
++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */
++ register8_t PLLCTRL; /* PLL Control Register */
++ register8_t DFLLCTRL; /* DFLL Control Register */
++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */
++} OSC_t;
++
++/* Oscillator Frequency Range */
++typedef enum OSC_FRQRANGE_enum
++{
++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
++} OSC_FRQRANGE_t;
++
++/* External Oscillator Selection and Startup Time */
++typedef enum OSC_XOSCSEL_enum
++{
++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */
++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */
++} OSC_XOSCSEL_t;
++
++/* PLL Clock Source */
++typedef enum OSC_PLLSRC_enum
++{
++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */
++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
++} OSC_PLLSRC_t;
++
++/* 32 MHz DFLL Calibration Reference */
++typedef enum OSC_RC32MCREF_enum
++{
++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */
++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */
++} OSC_RC32MCREF_t;
++
++
++/*
++--------------------------------------------------------------------------
++DFLL - DFLL
++--------------------------------------------------------------------------
++*/
++
++/* DFLL */
++typedef struct DFLL_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t reserved_0x01;
++ register8_t CALA; /* Calibration Register A */
++ register8_t CALB; /* Calibration Register B */
++ register8_t COMP0; /* Oscillator Compare Register 0 */
++ register8_t COMP1; /* Oscillator Compare Register 1 */
++ register8_t COMP2; /* Oscillator Compare Register 2 */
++ register8_t reserved_0x07;
++} DFLL_t;
++
++
++/*
++--------------------------------------------------------------------------
++RST - Reset
++--------------------------------------------------------------------------
++*/
++
++/* Reset */
++typedef struct RST_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t CTRL; /* Control Register */
++} RST_t;
++
++
++/*
++--------------------------------------------------------------------------
++WDT - Watch-Dog Timer
++--------------------------------------------------------------------------
++*/
++
++/* Watch-Dog Timer */
++typedef struct WDT_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t WINCTRL; /* Windowed Mode Control */
++ register8_t STATUS; /* Status */
++} WDT_t;
++
++/* Period setting */
++typedef enum WDT_PER_enum
++{
++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_PER_t;
++
++/* Closed window period */
++typedef enum WDT_WPER_enum
++{
++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
++} WDT_WPER_t;
++
++
++/*
++--------------------------------------------------------------------------
++MCU - MCU Control
++--------------------------------------------------------------------------
++*/
++
++/* MCU Control */
++typedef struct MCU_struct
++{
++ register8_t DEVID0; /* Device ID byte 0 */
++ register8_t DEVID1; /* Device ID byte 1 */
++ register8_t DEVID2; /* Device ID byte 2 */
++ register8_t REVID; /* Revision ID */
++ register8_t reserved_0x04;
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t ANAINIT; /* Analog Startup Delay */
++ register8_t EVSYSLOCK; /* Event System Lock */
++ register8_t WEXLOCK; /* WEX Lock */
++ register8_t FAULTLOCK; /* FAULT Lock */
++ register8_t reserved_0x0B;
++} MCU_t;
++
++
++/*
++--------------------------------------------------------------------------
++PMIC - Programmable Multi-level Interrupt Controller
++--------------------------------------------------------------------------
++*/
++
++/* Programmable Multi-level Interrupt Controller */
++typedef struct PMIC_struct
++{
++ register8_t STATUS; /* Status Register */
++ register8_t INTPRI; /* Interrupt Priority */
++ register8_t CTRL; /* Control Register */
++} PMIC_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORTCFG - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O port Configuration */
++typedef struct PORTCFG_struct
++{
++ register8_t MPCMASK; /* Multi-pin Configuration Mask */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t reserved_0x03;
++ register8_t CLKOUT; /* Clock Out Register */
++ register8_t reserved_0x05;
++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */
++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */
++} PORTCFG_t;
++
++/* Clock and Event Output Port */
++typedef enum PORTCFG_CLKEVPIN_enum
++{
++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */
++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */
++} PORTCFG_CLKEVPIN_t;
++
++/* RTC Clock Output Port */
++typedef enum PORTCFG_RTCCLKOUT_enum
++{
++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */
++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */
++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */
++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */
++} PORTCFG_RTCCLKOUT_t;
++
++/* Peripheral Clock Output Select */
++typedef enum PORTCFG_CLKOUTSEL_enum
++{
++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */
++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */
++} PORTCFG_CLKOUTSEL_t;
++
++/* System Clock Output Port */
++typedef enum PORTCFG_CLKOUT_enum
++{
++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */
++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */
++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */
++} PORTCFG_CLKOUT_t;
++
++/* Analog Comparator Output Port */
++typedef enum PORTCFG_ACOUT_enum
++{
++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */
++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */
++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */
++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */
++} PORTCFG_ACOUT_t;
++
++/* Event Output Port */
++typedef enum PORTCFG_EVOUT_enum
++{
++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */
++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */
++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */
++} PORTCFG_EVOUT_t;
++
++/* Event Output Select */
++typedef enum PORTCFG_EVOUTSEL_enum
++{
++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */
++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */
++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */
++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */
++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */
++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */
++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */
++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */
++} PORTCFG_EVOUTSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++CRC - Cyclic Redundancy Checker
++--------------------------------------------------------------------------
++*/
++
++/* Cyclic Redundancy Checker */
++typedef struct CRC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t reserved_0x02;
++ register8_t DATAIN; /* Data Input */
++ register8_t CHECKSUM0; /* Checksum byte 0 */
++ register8_t CHECKSUM1; /* Checksum byte 1 */
++ register8_t CHECKSUM2; /* Checksum byte 2 */
++ register8_t CHECKSUM3; /* Checksum byte 3 */
++} CRC_t;
++
++/* Reset */
++typedef enum CRC_RESET_enum
++{
++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */
++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
++} CRC_RESET_t;
++
++/* Input Source */
++typedef enum CRC_SOURCE_enum
++{
++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */
++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
++} CRC_SOURCE_t;
++
++
++/*
++--------------------------------------------------------------------------
++EDMA - Enhanced DMA Controller
++--------------------------------------------------------------------------
++*/
++
++/* EDMA Channel */
++typedef struct EDMA_CH_struct
++{
++ register8_t CTRLA; /* Channel Control A */
++ register8_t CTRLB; /* Channel Control */
++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */
++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */
++ register8_t TRIGSRC; /* Channel Trigger Source */
++ register8_t reserved_0x05;
++ register8_t TRFCNTL; /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */
++ register8_t TRFCNTH; /* Channel Block Transfer Count High for Standard Channels Only */
++ register8_t ADDRL; /* Channel Memory Address Low for Peripheral Ch., or Channel Source Address Low for Standard Ch. */
++ register8_t ADDRH; /* Channel Memory Address High for Peripheral Ch., or Channel Source Address High for Standard Ch. */
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t DESTADDRL; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t DESTADDRH; /* Channel Destination Address High for Standard Channels Only. */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} EDMA_CH_t;
++
++
++/* Enhanced DMA Controller */
++typedef struct EDMA_struct
++{
++ register8_t CTRL; /* Control */
++ register8_t reserved_0x01;
++ register8_t reserved_0x02;
++ register8_t INTFLAGS; /* Transfer Interrupt Status */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x05;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ EDMA_CH_t CH0; /* EDMA Channel 0 */
++ EDMA_CH_t CH1; /* EDMA Channel 1 */
++ EDMA_CH_t CH2; /* EDMA Channel 2 */
++ EDMA_CH_t CH3; /* EDMA Channel 3 */
++} EDMA_t;
++
++/* Channel mode */
++typedef enum EDMA_CHMODE_enum
++{
++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */
++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */
++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */
++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */
++} EDMA_CHMODE_t;
++
++/* Double buffer mode */
++typedef enum EDMA_DBUFMODE_enum
++{
++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */
++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */
++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */
++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */
++} EDMA_DBUFMODE_t;
++
++/* Priority mode */
++typedef enum EDMA_PRIMODE_enum
++{
++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */
++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */
++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */
++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */
++} EDMA_PRIMODE_t;
++
++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */
++typedef enum EDMA_CH_RELOAD_enum
++{
++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */
++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */
++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */
++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */
++} EDMA_CH_RELOAD_t;
++
++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */
++typedef enum EDMA_CH_DIR_enum
++{
++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */
++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */
++} EDMA_CH_DIR_t;
++
++/* Destination addressing mode */
++typedef enum EDMA_CH_DESTDIR_enum
++{
++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */
++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */
++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */
++} EDMA_CH_DESTDIR_t;
++
++/* Transfer trigger source */
++typedef enum EDMA_CH_TRIGSRC_enum
++{
++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */
++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */
++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */
++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */
++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */
++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */
++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */
++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */
++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */
++} EDMA_CH_TRIGSRC_t;
++
++/* Interrupt level */
++typedef enum EDMA_CH_INTLVL_enum
++{
++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */
++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */
++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */
++} EDMA_CH_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++EVSYS - Event System
++--------------------------------------------------------------------------
++*/
++
++/* Event System */
++typedef struct EVSYS_struct
++{
++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
++ register8_t CH0CTRL; /* Channel 0 Control Register */
++ register8_t CH1CTRL; /* Channel 1 Control Register */
++ register8_t CH2CTRL; /* Channel 2 Control Register */
++ register8_t CH3CTRL; /* Channel 3 Control Register */
++ register8_t CH4CTRL; /* Channel 4 Control Register */
++ register8_t CH5CTRL; /* Channel 5 Control Register */
++ register8_t CH6CTRL; /* Channel 6 Control Register */
++ register8_t CH7CTRL; /* Channel 7 Control Register */
++ register8_t STROBE; /* Event Strobe */
++ register8_t DATA; /* Event Data */
++ register8_t DFCTRL; /* Digital Filter Control Register */
++} EVSYS_t;
++
++/* Event Channel multiplexer input selection */
++typedef enum EVSYS_CHMUX_enum
++{
++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */
++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */
++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */
++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */
++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */
++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */
++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */
++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */
++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */
++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */
++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */
++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */
++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */
++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */
++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */
++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */
++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */
++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */
++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */
++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */
++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */
++} EVSYS_CHMUX_t;
++
++/* Quadrature Decoder Index Recognition Mode */
++typedef enum EVSYS_QDIRM_enum
++{
++ EVSYS_QDIRM_00_gc = (0x00<<0), /* QDPH0 = 0, QDPH90 = 0 */
++ EVSYS_QDIRM_01_gc = (0x01<<0), /* QDPH0 = 0, QDPH90 = 1 */
++ EVSYS_QDIRM_10_gc = (0x02<<0), /* QDPH0 = 1, QDPH90 = 0 */
++ EVSYS_QDIRM_11_gc = (0x03<<0), /* QDPH0 = 1, QDPH90 = 1 */
++} EVSYS_QDIRM_t;
++
++/* Digital filter coefficient */
++typedef enum EVSYS_DIGFILT_enum
++{
++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
++} EVSYS_DIGFILT_t;
++
++/* Prescaler Filter */
++typedef enum EVSYS_PRESCFILT_enum
++{
++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */
++ EVSYS_PRESCFILT_CH15_gc = (0x08<<4), /* Enable prescaler filter for either channel 1 or 5 */
++ EVSYS_PRESCFILT_CH26_gc = (0x40<<4), /* Enable prescaler filter for either channel 2 or 6 */
++ EVSYS_PRESCFILT_CH37_gc = (0x3E8<<4), /* Enable prescaler filter for either channel 3 or 7 */
++} EVSYS_PRESCFILT_t;
++
++/* Prescaler */
++typedef enum EVSYS_PRESCALER_enum
++{
++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */
++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */
++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */
++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */
++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */
++} EVSYS_PRESCALER_t;
++
++
++/*
++--------------------------------------------------------------------------
++NVM - Non Volatile Memory Controller
++--------------------------------------------------------------------------
++*/
++
++/* Non-volatile Memory Controller */
++typedef struct NVM_struct
++{
++ register8_t ADDR0; /* Address Register 0 */
++ register8_t ADDR1; /* Address Register 1 */
++ register8_t ADDR2; /* Address Register 2 */
++ register8_t reserved_0x03;
++ register8_t DATA0; /* Data Register 0 */
++ register8_t DATA1; /* Data Register 1 */
++ register8_t DATA2; /* Data Register 2 */
++ register8_t reserved_0x07;
++ register8_t reserved_0x08;
++ register8_t reserved_0x09;
++ register8_t CMD; /* Command */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t INTCTRL; /* Interrupt Control */
++ register8_t reserved_0x0E;
++ register8_t STATUS; /* Status */
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_t;
++
++/* NVM Command */
++typedef enum NVM_CMD_enum
++{
++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */
++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */
++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */
++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */
++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */
++} NVM_CMD_t;
++
++/* SPM ready interrupt level */
++typedef enum NVM_SPMLVL_enum
++{
++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
++} NVM_SPMLVL_t;
++
++/* EEPROM ready interrupt level */
++typedef enum NVM_EELVL_enum
++{
++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
++} NVM_EELVL_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum NVM_BLBB_enum
++{
++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} NVM_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum NVM_BLBA_enum
++{
++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} NVM_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum NVM_BLBAT_enum
++{
++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} NVM_BLBAT_t;
++
++/* Lock bits */
++typedef enum NVM_LB_enum
++{
++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} NVM_LB_t;
++
++
++/*
++--------------------------------------------------------------------------
++ADC - Analog/Digital Converter
++--------------------------------------------------------------------------
++*/
++
++/* ADC Channel */
++typedef struct ADC_CH_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t MUXCTRL; /* MUX Control */
++ register8_t INTCTRL; /* Channel Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ _WORDREGISTER(RES); /* Channel Result */
++ register8_t SCAN; /* Input Channel Scan */
++ register8_t CORRCTRL; /* Correction Control Register */
++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */
++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */
++ register8_t GAINCORR0; /* Gain Correction Register 0 */
++ register8_t GAINCORR1; /* Gain Correction Register 1 */
++ register8_t AVGCTRL; /* Average Control Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++} ADC_CH_t;
++
++
++/* Analog-to-Digital Converter */
++typedef struct ADC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t REFCTRL; /* Reference Control */
++ register8_t EVCTRL; /* Event Control */
++ register8_t PRESCALER; /* Clock Prescaler */
++ register8_t reserved_0x05;
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary Register */
++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */
++ register8_t reserved_0x09;
++ register8_t reserved_0x0A;
++ register8_t reserved_0x0B;
++ _WORDREGISTER(CAL); /* Calibration Value */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ _WORDREGISTER(CH0RES); /* Channel 0 Result */
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CMP); /* Compare Value */
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ ADC_CH_t CH0; /* ADC Channel 0 */
++} ADC_t;
++
++/* Current Limitation */
++typedef enum ADC_CURRLIMIT_enum
++{
++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */
++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */
++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */
++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */
++} ADC_CURRLIMIT_t;
++
++/* Conversion result resolution */
++typedef enum ADC_RESOLUTION_enum
++{
++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */
++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
++} ADC_RESOLUTION_t;
++
++/* Voltage reference selection */
++typedef enum ADC_REFSEL_enum
++{
++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */
++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */
++} ADC_REFSEL_t;
++
++/* Event channel input selection */
++typedef enum ADC_EVSEL_enum
++{
++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */
++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */
++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */
++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */
++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */
++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */
++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */
++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
++} ADC_EVSEL_t;
++
++/* Event action selection */
++typedef enum ADC_EVACT_enum
++{
++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */
++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
++} ADC_EVACT_t;
++
++/* Clock prescaler */
++typedef enum ADC_PRESCALER_enum
++{
++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
++} ADC_PRESCALER_t;
++
++/* Gain factor */
++typedef enum ADC_CH_GAIN_enum
++{
++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */
++} ADC_CH_GAIN_t;
++
++/* Input mode */
++typedef enum ADC_CH_INPUTMODE_enum
++{
++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */
++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */
++} ADC_CH_INPUTMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum ADC_CH_MUXPOS_enum
++{
++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
++} ADC_CH_MUXPOS_t;
++
++/* Internal input multiplexer selections */
++typedef enum ADC_CH_MUXINT_enum
++{
++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */
++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */
++} ADC_CH_MUXINT_t;
++
++/* Negative input multiplexer selection when gain on 4 LSB pins */
++typedef enum ADC_CH_MUXNEGL_enum
++{
++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */
++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */
++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */
++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */
++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */
++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */
++} ADC_CH_MUXNEGL_t;
++
++/* Negative input multiplexer selection when gain on 4 MSB pins */
++typedef enum ADC_CH_MUXNEGH_enum
++{
++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */
++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */
++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */
++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */
++ ADC_CH_MUXNEGH_INTGND_gc = (0x04<<0), /* Internal ground */
++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */
++} ADC_CH_MUXNEGH_t;
++
++/* Negative input multiplexer selection */
++typedef enum ADC_CH_MUXNEG_enum
++{
++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
++} ADC_CH_MUXNEG_t;
++
++/* Interupt mode */
++typedef enum ADC_CH_INTMODE_enum
++{
++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
++} ADC_CH_INTMODE_t;
++
++/* Interrupt level */
++typedef enum ADC_CH_INTLVL_enum
++{
++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
++} ADC_CH_INTLVL_t;
++
++/* Averaged Number of Samples */
++typedef enum ADC_SAMPNUM_enum
++{
++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */
++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */
++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */
++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */
++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */
++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */
++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */
++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */
++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */
++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */
++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */
++} ADC_SAMPNUM_t;
++
++
++/*
++--------------------------------------------------------------------------
++DAC - Digital/Analog Converter
++--------------------------------------------------------------------------
++*/
++
++/* Digital-to-Analog Converter */
++typedef struct DAC_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t EVCTRL; /* Event Input Control */
++ register8_t TIMCTRL; /* Timing Control */
++ register8_t STATUS; /* Status */
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t CH0GAINCAL; /* Gain Calibration */
++ register8_t CH0OFFSETCAL; /* Offset Calibration */
++ register8_t CH1GAINCAL; /* Gain Calibration */
++ register8_t CH1OFFSETCAL; /* Offset Calibration */
++ register8_t reserved_0x0C;
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
++} DAC_t;
++
++/* Output channel selection */
++typedef enum DAC_CHSEL_enum
++{
++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */
++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */
++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */
++} DAC_CHSEL_t;
++
++/* Reference voltage selection */
++typedef enum DAC_REFSEL_enum
++{
++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
++} DAC_REFSEL_t;
++
++/* Event channel selection */
++typedef enum DAC_EVSEL_enum
++{
++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
++} DAC_EVSEL_t;
++
++/* Conversion interval */
++typedef enum DAC_CONINTVAL_enum
++{
++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
++} DAC_CONINTVAL_t;
++
++/* Refresh rate */
++typedef enum DAC_REFRESH_enum
++{
++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */
++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
++} DAC_REFRESH_t;
++
++
++/*
++--------------------------------------------------------------------------
++AC - Analog Comparator
++--------------------------------------------------------------------------
++*/
++
++/* Analog Comparator */
++typedef struct AC_struct
++{
++ register8_t AC0CTRL; /* Analog Comparator 0 Control */
++ register8_t AC1CTRL; /* Analog Comparator 1 Control */
++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t WINCTRL; /* Window Mode Control */
++ register8_t STATUS; /* Status */
++ register8_t CURRCTRL; /* Current Source Control Register */
++ register8_t CURRCALIB; /* Current Source Calibration Register */
++} AC_t;
++
++/* Interrupt mode */
++typedef enum AC_INTMODE_enum
++{
++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
++} AC_INTMODE_t;
++
++/* Interrupt level */
++typedef enum AC_INTLVL_enum
++{
++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
++} AC_INTLVL_t;
++
++/* Hysteresis mode selection */
++typedef enum AC_HYSMODE_enum
++{
++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
++} AC_HYSMODE_t;
++
++/* Positive input multiplexer selection */
++typedef enum AC_MUXPOS_enum
++{
++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
++} AC_MUXPOS_t;
++
++/* Negative input multiplexer selection */
++typedef enum AC_MUXNEG_enum
++{
++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
++} AC_MUXNEG_t;
++
++/* Windows interrupt mode */
++typedef enum AC_WINTMODE_enum
++{
++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
++} AC_WINTMODE_t;
++
++/* Window interrupt level */
++typedef enum AC_WINTLVL_enum
++{
++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
++} AC_WINTLVL_t;
++
++/* Window mode state */
++typedef enum AC_WSTATE_enum
++{
++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
++} AC_WSTATE_t;
++
++
++/*
++--------------------------------------------------------------------------
++RTC - Real-Time Clounter
++--------------------------------------------------------------------------
++*/
++
++/* Real-Time Counter */
++typedef struct RTC_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flags */
++ register8_t TEMP; /* Temporary register */
++ register8_t reserved_0x05;
++ register8_t CALIB; /* Calibration Register */
++ register8_t reserved_0x07;
++ _WORDREGISTER(CNT); /* Count Register */
++ _WORDREGISTER(PER); /* Period Register */
++ _WORDREGISTER(COMP); /* Compare Register */
++} RTC_t;
++
++/* Prescaler Factor */
++typedef enum RTC_PRESCALER_enum
++{
++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
++} RTC_PRESCALER_t;
++
++/* Compare Interrupt level */
++typedef enum RTC_COMPINTLVL_enum
++{
++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
++} RTC_COMPINTLVL_t;
++
++/* Overflow Interrupt level */
++typedef enum RTC_OVFINTLVL_enum
++{
++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} RTC_OVFINTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++XCL - XMEGA Custom Logic
++--------------------------------------------------------------------------
++*/
++
++/* XMEGA Custom Logic */
++typedef struct XCL_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t CTRLG; /* Control Register G */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t PLC; /* Peripheral Lenght Control Register */
++ register8_t CNTL; /* Counter Register Low */
++ register8_t CNTH; /* Counter Register High */
++ register8_t CMPL; /* Compare Register Low */
++ register8_t CMPH; /* Compare Register High */
++ register8_t PERCAPTL; /* Period or Capture Register Low */
++ register8_t PERCAPTH; /* Period or Capture Register High */
++} XCL_t;
++
++/* LUT0 Output Enable */
++typedef enum XCL_LUTOUTEN_enum
++{
++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */
++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */
++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */
++} XCL_LUTOUTEN_t;
++
++/* Port Selection */
++typedef enum XCL_PORTSEL_enum
++{
++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */
++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */
++} XCL_PORTSEL_t;
++
++/* LUT Configuration */
++typedef enum XCL_LUTCONF_enum
++{
++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */
++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */
++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */
++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */
++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */
++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */
++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */
++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */
++} XCL_LUTCONF_t;
++
++/* Input Selection */
++typedef enum XCL_INSEL_enum
++{
++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */
++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */
++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */
++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */
++} XCL_INSEL_t;
++
++/* Delay Configuration on LUT */
++typedef enum XCL_DLYCONF_enum
++{
++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */
++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */
++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */
++} XCL_DLYCONF_t;
++
++/* Delay Selection */
++typedef enum XCL_DLYSEL_enum
++{
++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */
++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */
++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */
++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */
++} XCL_DLYSEL_t;
++
++/* Clock Selection */
++typedef enum XCL_CLKSEL_enum
++{
++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */
++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */
++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */
++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */
++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */
++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */
++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */
++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */
++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */
++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */
++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */
++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */
++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */
++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */
++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */
++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */
++} XCL_CLKSEL_t;
++
++/* Timer/Counter Command Selection */
++typedef enum XCL_CMDSEL_enum
++{
++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */
++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */
++} XCL_CMDSEL_t;
++
++/* Timer/Counter Selection */
++typedef enum XCL_TCSEL_enum
++{
++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */
++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */
++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */
++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */
++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */
++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */
++} XCL_TCSEL_t;
++
++/* Timer/Counter Mode */
++typedef enum XCL_TCMODE_enum
++{
++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */
++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */
++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */
++} XCL_TCMODE_t;
++
++/* Compare Output Value Timer */
++typedef enum XCL_CMPEN_enum
++{
++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */
++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */
++} XCL_CMPEN_t;
++
++/* Command Enable */
++typedef enum XCL_CMDEN_enum
++{
++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */
++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */
++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */
++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */
++} XCL_CMDEN_t;
++
++/* Timer/Counter Event Source Selection */
++typedef enum XCL_EVSRC_enum
++{
++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */
++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */
++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */
++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */
++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */
++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */
++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */
++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */
++} XCL_EVSRC_t;
++
++/* Timer/Counter Event Action Selection */
++typedef enum XCL_EVACT_enum
++{
++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */
++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */
++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */
++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */
++} XCL_EVACT_t;
++
++/* Underflow Interrupt level */
++typedef enum XCL_UNF_INTLVL_enum
++{
++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */
++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */
++} XCL_UNF_INTLVL_t;
++
++/* Compare/Capture Interrupt level */
++typedef enum XCL_CC_INTLVL_enum
++{
++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} XCL_CC_INTLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++TWI - Two-Wire Interface
++--------------------------------------------------------------------------
++*/
++
++/* */
++typedef struct TWI_MASTER_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t STATUS; /* Status Register */
++ register8_t BAUD; /* Baurd Rate Control Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++} TWI_MASTER_t;
++
++
++/* */
++typedef struct TWI_SLAVE_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t STATUS; /* Status Register */
++ register8_t ADDR; /* Address Register */
++ register8_t DATA; /* Data Register */
++ register8_t ADDRMASK; /* Address Mask Register */
++} TWI_SLAVE_t;
++
++
++/* Two-Wire Interface */
++typedef struct TWI_struct
++{
++ register8_t CTRL; /* TWI Common Control Register */
++ TWI_MASTER_t MASTER; /* TWI master module */
++ TWI_SLAVE_t SLAVE; /* TWI slave module */
++} TWI_t;
++
++/* SDA Hold Time */
++typedef enum TWI_SDAHOLD_enum
++{
++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */
++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */
++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */
++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */
++} TWI_SDAHOLD_t;
++
++/* Master Interrupt Level */
++typedef enum TWI_MASTER_INTLVL_enum
++{
++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_MASTER_INTLVL_t;
++
++/* Inactive Timeout */
++typedef enum TWI_MASTER_TIMEOUT_enum
++{
++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
++} TWI_MASTER_TIMEOUT_t;
++
++/* Master Command */
++typedef enum TWI_MASTER_CMD_enum
++{
++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
++} TWI_MASTER_CMD_t;
++
++/* Master Bus State */
++typedef enum TWI_MASTER_BUSSTATE_enum
++{
++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
++} TWI_MASTER_BUSSTATE_t;
++
++/* Slave Interrupt Level */
++typedef enum TWI_SLAVE_INTLVL_enum
++{
++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
++} TWI_SLAVE_INTLVL_t;
++
++/* Slave Command */
++typedef enum TWI_SLAVE_CMD_enum
++{
++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
++} TWI_SLAVE_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++PORT - Port Configuration
++--------------------------------------------------------------------------
++*/
++
++/* I/O Ports */
++typedef struct PORT_struct
++{
++ register8_t DIR; /* I/O Port Data Direction */
++ register8_t DIRSET; /* I/O Port Data Direction Set */
++ register8_t DIRCLR; /* I/O Port Data Direction Clear */
++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
++ register8_t OUT; /* I/O Port Output */
++ register8_t OUTSET; /* I/O Port Output Set */
++ register8_t OUTCLR; /* I/O Port Output Clear */
++ register8_t OUTTGL; /* I/O Port Output Toggle */
++ register8_t IN; /* I/O port Input */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t INTMASK; /* Port Interrupt Mask */
++ register8_t reserved_0x0B;
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t REMAP; /* Pin Remap Register */
++ register8_t reserved_0x0F;
++ register8_t PIN0CTRL; /* Pin 0 Control Register */
++ register8_t PIN1CTRL; /* Pin 1 Control Register */
++ register8_t PIN2CTRL; /* Pin 2 Control Register */
++ register8_t PIN3CTRL; /* Pin 3 Control Register */
++ register8_t PIN4CTRL; /* Pin 4 Control Register */
++ register8_t PIN5CTRL; /* Pin 5 Control Register */
++ register8_t PIN6CTRL; /* Pin 6 Control Register */
++ register8_t PIN7CTRL; /* Pin 7 Control Register */
++} PORT_t;
++
++/* Port Interrupt Level */
++typedef enum PORT_INTLVL_enum
++{
++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} PORT_INTLVL_t;
++
++/* Output/Pull Configuration */
++typedef enum PORT_OPC_enum
++{
++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
++} PORT_OPC_t;
++
++/* Input/Sense Configuration */
++typedef enum PORT_ISC_enum
++{
++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */
++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
++} PORT_ISC_t;
++
++
++/*
++--------------------------------------------------------------------------
++TC - 16-bit Timer/Counter With PWM
++--------------------------------------------------------------------------
++*/
++
++/* 16-bit Timer/Counter 4 */
++typedef struct TC4_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ _WORDREGISTER(CCC); /* Compare or Capture C */
++ _WORDREGISTER(CCD); /* Compare or Capture D */
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
++} TC4_t;
++
++
++/* 16-bit Timer/Counter 5 */
++typedef struct TC5_struct
++{
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t CTRLE; /* Control Register E */
++ register8_t CTRLF; /* Control Register F */
++ register8_t INTCTRLA; /* Interrupt Control Register A */
++ register8_t INTCTRLB; /* Interrupt Control Register B */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G Set */
++ register8_t CTRLHCLR; /* Control Register H Clear */
++ register8_t CTRLHSET; /* Control Register H Set */
++ register8_t INTFLAGS; /* Interrupt Flag Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t TEMP; /* Temporary Register For 16-bit Access */
++ register8_t reserved_0x10;
++ register8_t reserved_0x11;
++ register8_t reserved_0x12;
++ register8_t reserved_0x13;
++ register8_t reserved_0x14;
++ register8_t reserved_0x15;
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ _WORDREGISTER(CNT); /* Count */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ _WORDREGISTER(PER); /* Period */
++ _WORDREGISTER(CCA); /* Compare or Capture A */
++ _WORDREGISTER(CCB); /* Compare or Capture B */
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t reserved_0x2E;
++ register8_t reserved_0x2F;
++ register8_t reserved_0x30;
++ register8_t reserved_0x31;
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t reserved_0x34;
++ register8_t reserved_0x35;
++ _WORDREGISTER(PERBUF); /* Period Buffer */
++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} TC5_t;
++
++/* Clock Selection */
++typedef enum TC45_CLKSEL_enum
++{
++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_CLKSEL_t;
++
++/* Byte Mode */
++typedef enum TC45_BYTEM_enum
++{
++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */
++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */
++} TC45_BYTEM_t;
++
++/* Circular Enable Mode */
++typedef enum TC45_CIRCEN_enum
++{
++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */
++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */
++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */
++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */
++} TC45_CIRCEN_t;
++
++/* Waveform Generation Mode */
++typedef enum TC45_WGMODE_enum
++{
++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */
++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */
++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */
++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
++} TC45_WGMODE_t;
++
++/* Event Action */
++typedef enum TC45_EVACT_enum
++{
++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */
++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */
++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */
++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */
++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */
++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */
++} TC45_EVACT_t;
++
++/* Event Selection */
++typedef enum TC45_EVSEL_enum
++{
++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
++} TC45_EVSEL_t;
++
++/* Compare or Capture Channel A Mode */
++typedef enum TC45_CCAMODE_enum
++{
++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_CCAMODE_t;
++
++/* Compare or Capture Channel B Mode */
++typedef enum TC45_CCBMODE_enum
++{
++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_CCBMODE_t;
++
++/* Compare or Capture Channel C Mode */
++typedef enum TC45_CCCMODE_enum
++{
++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_CCCMODE_t;
++
++/* Compare or Capture Channel D Mode */
++typedef enum TC45_CCDMODE_enum
++{
++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_CCDMODE_t;
++
++/* Compare or Capture Low Channel A Mode */
++typedef enum TC45_LCCAMODE_enum
++{
++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_LCCAMODE_t;
++
++/* Compare or Capture Low Channel B Mode */
++typedef enum TC45_LCCBMODE_enum
++{
++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_LCCBMODE_t;
++
++/* Compare or Capture Low Channel C Mode */
++typedef enum TC45_LCCCMODE_enum
++{
++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_LCCCMODE_t;
++
++/* Compare or Capture Low Channel D Mode */
++typedef enum TC45_LCCDMODE_enum
++{
++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_LCCDMODE_t;
++
++/* Compare or Capture High Channel A Mode */
++typedef enum TC45_HCCAMODE_enum
++{
++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */
++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */
++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */
++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */
++} TC45_HCCAMODE_t;
++
++/* Compare or Capture High Channel B Mode */
++typedef enum TC45_HCCBMODE_enum
++{
++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */
++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */
++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */
++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */
++} TC45_HCCBMODE_t;
++
++/* Compare or Capture High Channel C Mode */
++typedef enum TC45_HCCCMODE_enum
++{
++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */
++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */
++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */
++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */
++} TC45_HCCCMODE_t;
++
++/* Compare or Capture High Channel D Mode */
++typedef enum TC45_HCCDMODE_enum
++{
++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */
++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */
++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */
++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */
++} TC45_HCCDMODE_t;
++
++/* Timer Trigger Restart Interrupt Level */
++typedef enum TC45_TRGINTLVL_enum
++{
++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_TRGINTLVL_t;
++
++/* Error Interrupt Level */
++typedef enum TC45_ERRINTLVL_enum
++{
++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_ERRINTLVL_t;
++
++/* Overflow Interrupt Level */
++typedef enum TC45_OVFINTLVL_enum
++{
++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_OVFINTLVL_t;
++
++/* Compare or Capture Channel A Interrupt Level */
++typedef enum TC45_CCAINTLVL_enum
++{
++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_CCAINTLVL_t;
++
++/* Compare or Capture Channel B Interrupt Level */
++typedef enum TC45_CCBINTLVL_enum
++{
++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_CCBINTLVL_t;
++
++/* Compare or Capture Channel C Interrupt Level */
++typedef enum TC45_CCCINTLVL_enum
++{
++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_CCCINTLVL_t;
++
++/* Compare or Capture Channel D Interrupt Level */
++typedef enum TC45_CCDINTLVL_enum
++{
++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_CCDINTLVL_t;
++
++/* Compare or Capture Low Channel A Interrupt Level */
++typedef enum TC45_LCCAINTLVL_enum
++{
++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */
++} TC45_LCCAINTLVL_t;
++
++/* Compare or Capture Low Channel B Interrupt Level */
++typedef enum TC45_LCCBINTLVL_enum
++{
++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */
++} TC45_LCCBINTLVL_t;
++
++/* Compare or Capture Low Channel C Interrupt Level */
++typedef enum TC45_LCCCINTLVL_enum
++{
++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} TC45_LCCCINTLVL_t;
++
++/* Compare or Capture Low Channel D Interrupt Level */
++typedef enum TC45_LCCDINTLVL_enum
++{
++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */
++} TC45_LCCDINTLVL_t;
++
++/* Timer/Counter Command */
++typedef enum TC45_CMD_enum
++{
++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */
++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
++} TC45_CMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++FAULT - Fault Extension
++--------------------------------------------------------------------------
++*/
++
++/* Fault Extension */
++typedef struct FAULT_struct
++{
++ register8_t CTRLA; /* Control A Register */
++ register8_t CTRLB; /* Control B Register */
++ register8_t CTRLC; /* Control C Register */
++ register8_t CTRLD; /* Control D Register */
++ register8_t CTRLE; /* Control E Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLGCLR; /* Control Register G Clear */
++ register8_t CTRLGSET; /* Control Register G set */
++} FAULT_t;
++
++/* Ramp Mode Selection */
++typedef enum FAULT_RAMP_enum
++{
++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */
++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */
++} FAULT_RAMP_t;
++
++/* Fault E Input Source Selection */
++typedef enum FAULT_SRCE_enum
++{
++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */
++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */
++} FAULT_SRCE_t;
++
++/* Fault A Halt Action Selection */
++typedef enum FAULT_HALTA_enum
++{
++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTA_t;
++
++/* Fault A Source Selection */
++typedef enum FAULT_SRCA_enum
++{
++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */
++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */
++} FAULT_SRCA_t;
++
++/* Fault B Halt Action Selection */
++typedef enum FAULT_HALTB_enum
++{
++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */
++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */
++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */
++} FAULT_HALTB_t;
++
++/* Fault B Source Selection */
++typedef enum FAULT_SRCB_enum
++{
++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */
++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */
++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */
++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */
++} FAULT_SRCB_t;
++
++/* Channel index Command */
++typedef enum FAULT_IDXCMD_enum
++{
++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */
++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */
++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */
++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */
++} FAULT_IDXCMD_t;
++
++
++/*
++--------------------------------------------------------------------------
++WEX - Waveform Extension
++--------------------------------------------------------------------------
++*/
++
++/* Waveform Extension */
++typedef struct WEX_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */
++ register8_t DTLS; /* Dead-time Low Side Register */
++ register8_t DTHS; /* Dead-time High Side Register */
++ register8_t STATUSCLR; /* Status Clear Register */
++ register8_t STATUSSET; /* Status Set Register */
++ register8_t SWAP; /* Swap Register */
++ register8_t PGO; /* Pattern Generation Override Register */
++ register8_t PGV; /* Pattern Generation Value Register */
++ register8_t reserved_0x09;
++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */
++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */
++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */
++ register8_t reserved_0x0D;
++ register8_t reserved_0x0E;
++ register8_t OUTOVDIS; /* Output Override Disable Register */
++} WEX_t;
++
++/* Output Matrix Mode */
++typedef enum WEX_OTMX_enum
++{
++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */
++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */
++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */
++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */
++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */
++} WEX_OTMX_t;
++
++
++/*
++--------------------------------------------------------------------------
++HIRES - High-Resolution Extension
++--------------------------------------------------------------------------
++*/
++
++/* High-Resolution Extension */
++typedef struct HIRES_struct
++{
++ register8_t CTRLA; /* Control Register A */
++} HIRES_t;
++
++/* High Resolution Plus Mode */
++typedef enum HIRES_HRPLUS_enum
++{
++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */
++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */
++ HIRES_HRPLUS_HRP5_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 5 */
++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */
++} HIRES_HRPLUS_t;
++
++/* High Resolution Mode */
++typedef enum HIRES_HREN_enum
++{
++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */
++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */
++ HIRES_HREN_HRP5_gc = (0x03<<0), /* Hi-Res enabled on Timer 5 */
++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */
++} HIRES_HREN_t;
++
++
++/*
++--------------------------------------------------------------------------
++USART - Universal Asynchronous Receiver-Transmitter
++--------------------------------------------------------------------------
++*/
++
++/* Universal Synchronous/Asynchronous Receiver/Transmitter */
++typedef struct USART_struct
++{
++ register8_t DATA; /* Data Register */
++ register8_t STATUS; /* Status Register */
++ register8_t CTRLA; /* Control Register A */
++ register8_t CTRLB; /* Control Register B */
++ register8_t CTRLC; /* Control Register C */
++ register8_t CTRLD; /* Control Register D */
++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
++} USART_t;
++
++/* Receive Start Interrupt level */
++typedef enum USART_RXSINTLVL_enum
++{
++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_RXSINTLVL_t;
++
++/* Receive Complete Interrupt level */
++typedef enum USART_RXCINTLVL_enum
++{
++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
++} USART_RXCINTLVL_t;
++
++/* Transmit Complete Interrupt level */
++typedef enum USART_TXCINTLVL_enum
++{
++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
++} USART_TXCINTLVL_t;
++
++/* Data Register Empty Interrupt level */
++typedef enum USART_DREINTLVL_enum
++{
++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
++} USART_DREINTLVL_t;
++
++/* Character Size */
++typedef enum USART_CHSIZE_enum
++{
++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
++} USART_CHSIZE_t;
++
++/* Communication Mode */
++typedef enum USART_CMODE_enum
++{
++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
++} USART_CMODE_t;
++
++/* Parity Mode */
++typedef enum USART_PMODE_enum
++{
++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
++} USART_PMODE_t;
++
++/* Encoding and Decoding Type */
++typedef enum USART_DECTYPE_enum
++{
++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */
++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */
++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */
++} USART_DECTYPE_t;
++
++/* XCL LUT Action */
++typedef enum USART_LUTACT_enum
++{
++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */
++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */
++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */
++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */
++} USART_LUTACT_t;
++
++/* XCL Peripheral Counter Action */
++typedef enum USART_PECACT_enum
++{
++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */
++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */
++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */
++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */
++} USART_PECACT_t;
++
++
++/*
++--------------------------------------------------------------------------
++SPI - Serial Peripheral Interface
++--------------------------------------------------------------------------
++*/
++
++/* Serial Peripheral Interface with Buffer Modes */
++typedef struct SPI_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t INTCTRL; /* Interrupt Control Register */
++ register8_t STATUS; /* Status Register */
++ register8_t DATA; /* Data Register */
++ register8_t CTRLB; /* Control Register B */
++} SPI_t;
++
++/* SPI Mode */
++typedef enum SPI_MODE_enum
++{
++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */
++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */
++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */
++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */
++} SPI_MODE_t;
++
++/* Prescaler setting */
++typedef enum SPI_PRESCALER_enum
++{
++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */
++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */
++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */
++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */
++} SPI_PRESCALER_t;
++
++/* Interrupt level */
++typedef enum SPI_INTLVL_enum
++{
++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
++} SPI_INTLVL_t;
++
++/* Buffer Modes */
++typedef enum SPI_BUFMODE_enum
++{
++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */
++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */
++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */
++} SPI_BUFMODE_t;
++
++
++/*
++--------------------------------------------------------------------------
++IRCOM - IR Communication Module
++--------------------------------------------------------------------------
++*/
++
++/* IR Communication Module */
++typedef struct IRCOM_struct
++{
++ register8_t CTRL; /* Control Register */
++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
++} IRCOM_t;
++
++/* Event channel selection */
++typedef enum IRDA_EVSEL_enum
++{
++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
++} IRDA_EVSEL_t;
++
++
++/*
++--------------------------------------------------------------------------
++FUSE - Fuses and Lockbits
++--------------------------------------------------------------------------
++*/
++
++/* Lock Bits */
++typedef struct NVM_LOCKBITS_struct
++{
++ register8_t LOCKBITS; /* Lock Bits */
++} NVM_LOCKBITS_t;
++
++
++/* Fuses */
++typedef struct NVM_FUSES_struct
++{
++ register8_t reserved_0x00;
++ register8_t FUSEBYTE1; /* Watchdog Configuration */
++ register8_t FUSEBYTE2; /* Reset Configuration */
++ register8_t reserved_0x03;
++ register8_t FUSEBYTE4; /* Start-up Configuration */
++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
++ register8_t FUSEBYTE6; /* Fault State */
++} NVM_FUSES_t;
++
++/* Boot lock bits - boot setcion */
++typedef enum FUSE_BLBB_enum
++{
++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
++} FUSE_BLBB_t;
++
++/* Boot lock bits - application section */
++typedef enum FUSE_BLBA_enum
++{
++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
++} FUSE_BLBA_t;
++
++/* Boot lock bits - application table section */
++typedef enum FUSE_BLBAT_enum
++{
++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
++} FUSE_BLBAT_t;
++
++/* Lock bits */
++typedef enum FUSE_LB_enum
++{
++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */
++} FUSE_LB_t;
++
++/* Boot Loader Section Reset Vector */
++typedef enum BOOTRST_enum
++{
++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
++} BOOTRST_t;
++
++/* BOD operation */
++typedef enum BOD_enum
++{
++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */
++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */
++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */
++} BOD_t;
++
++/* Watchdog (Window) Timeout Period */
++typedef enum WD_enum
++{
++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
++} WD_t;
++
++/* Start-up Time */
++typedef enum SUT_enum
++{
++ SUT_0MS_gc = (0x03<<2), /* 0 ms */
++ SUT_4MS_gc = (0x01<<2), /* 4 ms */
++ SUT_64MS_gc = (0x00<<2), /* 64 ms */
++} SUT_t;
++
++/* Brown Out Detection Voltage Level */
++typedef enum BODLVL_enum
++{
++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */
++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */
++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */
++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */
++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */
++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */
++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */
++} BODLVL_t;
++
++
++/*
++--------------------------------------------------------------------------
++SIGROW - Signature Row
++--------------------------------------------------------------------------
++*/
++
++/* Production Signatures */
++typedef struct NVM_PROD_SIGNATURES_struct
++{
++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */
++ register8_t reserved_0x01;
++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */
++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */
++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */
++ register8_t reserved_0x05;
++ register8_t reserved_0x06;
++ register8_t reserved_0x07;
++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
++ register8_t reserved_0x0E;
++ register8_t reserved_0x0F;
++ register8_t WAFNUM; /* Wafer Number */
++ register8_t reserved_0x11;
++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
++ register8_t reserved_0x16;
++ register8_t reserved_0x17;
++ register8_t reserved_0x18;
++ register8_t reserved_0x19;
++ register8_t reserved_0x1A;
++ register8_t reserved_0x1B;
++ register8_t reserved_0x1C;
++ register8_t reserved_0x1D;
++ register8_t reserved_0x1E;
++ register8_t reserved_0x1F;
++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
++ register8_t reserved_0x22;
++ register8_t reserved_0x23;
++ register8_t reserved_0x24;
++ register8_t reserved_0x25;
++ register8_t reserved_0x26;
++ register8_t reserved_0x27;
++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */
++ register8_t reserved_0x29;
++ register8_t reserved_0x2A;
++ register8_t reserved_0x2B;
++ register8_t reserved_0x2C;
++ register8_t reserved_0x2D;
++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */
++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */
++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */
++ register8_t reserved_0x32;
++ register8_t reserved_0x33;
++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */
++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */
++ register8_t reserved_0x36;
++ register8_t reserved_0x37;
++ register8_t reserved_0x38;
++ register8_t reserved_0x39;
++ register8_t reserved_0x3A;
++ register8_t reserved_0x3B;
++ register8_t reserved_0x3C;
++ register8_t reserved_0x3D;
++ register8_t reserved_0x3E;
++ register8_t reserved_0x3F;
++} NVM_PROD_SIGNATURES_t;
++
++/*
++==========================================================================
++IO Module Instances. Mapped to memory.
++==========================================================================
++*/
++
++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */
++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */
++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */
++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */
++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
++#define CLK (*(CLK_t *) 0x0040) /* Clock System */
++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */
++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */
++#define PR (*(PR_t *) 0x0070) /* Power Reduction */
++#define RST (*(RST_t *) 0x0078) /* Reset */
++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */
++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */
++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */
++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */
++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */
++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */
++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */
++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */
++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */
++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */
++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */
++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */
++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */
++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */
++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */
++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */
++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */
++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */
++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */
++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */
++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */
++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */
++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */
++
++
++#endif /* !defined (__ASSEMBLER__) */
++
++
++/* ========== Flattened fully qualified IO register names ========== */
++
++/* GPIO - General Purpose IO Registers */
++#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
++#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
++#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
++#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
++
++/* Deprecated */
++#define GPIO_GPIO0 _SFR_MEM8(0x0000)
++#define GPIO_GPIO1 _SFR_MEM8(0x0001)
++#define GPIO_GPIO2 _SFR_MEM8(0x0002)
++#define GPIO_GPIO3 _SFR_MEM8(0x0003)
++
++/* NVM_FUSES - Fuses */
++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001)
++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002)
++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004)
++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005)
++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006)
++
++/* NVM_LOCKBITS - Lock Bits */
++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000)
++
++/* NVM_PROD_SIGNATURES - Production Signatures */
++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000)
++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002)
++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003)
++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004)
++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008)
++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009)
++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A)
++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B)
++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C)
++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D)
++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010)
++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012)
++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013)
++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014)
++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015)
++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020)
++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021)
++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028)
++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E)
++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F)
++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030)
++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031)
++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034)
++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035)
++
++/* VPORT - Virtual Port */
++#define VPORT0_DIR _SFR_MEM8(0x0010)
++#define VPORT0_OUT _SFR_MEM8(0x0011)
++#define VPORT0_IN _SFR_MEM8(0x0012)
++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
++
++/* VPORT - Virtual Port */
++#define VPORT1_DIR _SFR_MEM8(0x0014)
++#define VPORT1_OUT _SFR_MEM8(0x0015)
++#define VPORT1_IN _SFR_MEM8(0x0016)
++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
++
++/* VPORT - Virtual Port */
++#define VPORT2_DIR _SFR_MEM8(0x0018)
++#define VPORT2_OUT _SFR_MEM8(0x0019)
++#define VPORT2_IN _SFR_MEM8(0x001A)
++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
++
++/* VPORT - Virtual Port */
++#define VPORT3_DIR _SFR_MEM8(0x001C)
++#define VPORT3_OUT _SFR_MEM8(0x001D)
++#define VPORT3_IN _SFR_MEM8(0x001E)
++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
++
++/* OCD - On-Chip Debug System */
++#define OCD_OCDR0 _SFR_MEM8(0x002E)
++#define OCD_OCDR1 _SFR_MEM8(0x002F)
++
++/* CPU - CPU registers */
++#define CPU_CCP _SFR_MEM8(0x0034)
++#define CPU_RAMPD _SFR_MEM8(0x0038)
++#define CPU_RAMPX _SFR_MEM8(0x0039)
++#define CPU_RAMPY _SFR_MEM8(0x003A)
++#define CPU_RAMPZ _SFR_MEM8(0x003B)
++#define CPU_EIND _SFR_MEM8(0x003C)
++#define CPU_SPL _SFR_MEM8(0x003D)
++#define CPU_SPH _SFR_MEM8(0x003E)
++#define CPU_SREG _SFR_MEM8(0x003F)
++
++/* CLK - Clock System */
++#define CLK_CTRL _SFR_MEM8(0x0040)
++#define CLK_PSCTRL _SFR_MEM8(0x0041)
++#define CLK_LOCK _SFR_MEM8(0x0042)
++#define CLK_RTCCTRL _SFR_MEM8(0x0043)
++
++/* SLEEP - Sleep Controller */
++#define SLEEP_CTRL _SFR_MEM8(0x0048)
++
++/* OSC - Oscillator */
++#define OSC_CTRL _SFR_MEM8(0x0050)
++#define OSC_STATUS _SFR_MEM8(0x0051)
++#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
++#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
++#define OSC_RC32KCAL _SFR_MEM8(0x0054)
++#define OSC_PLLCTRL _SFR_MEM8(0x0055)
++#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
++#define OSC_RC8MCAL _SFR_MEM8(0x0057)
++
++/* DFLL - DFLL */
++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
++#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
++#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
++
++/* PR - Power Reduction */
++#define PR_PRGEN _SFR_MEM8(0x0070)
++#define PR_PRPA _SFR_MEM8(0x0071)
++#define PR_PRPC _SFR_MEM8(0x0073)
++#define PR_PRPD _SFR_MEM8(0x0074)
++
++/* RST - Reset */
++#define RST_STATUS _SFR_MEM8(0x0078)
++#define RST_CTRL _SFR_MEM8(0x0079)
++
++/* WDT - Watch-Dog Timer */
++#define WDT_CTRL _SFR_MEM8(0x0080)
++#define WDT_WINCTRL _SFR_MEM8(0x0081)
++#define WDT_STATUS _SFR_MEM8(0x0082)
++
++/* MCU - MCU Control */
++#define MCU_DEVID0 _SFR_MEM8(0x0090)
++#define MCU_DEVID1 _SFR_MEM8(0x0091)
++#define MCU_DEVID2 _SFR_MEM8(0x0092)
++#define MCU_REVID _SFR_MEM8(0x0093)
++#define MCU_ANAINIT _SFR_MEM8(0x0097)
++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
++#define MCU_WEXLOCK _SFR_MEM8(0x0099)
++#define MCU_FAULTLOCK _SFR_MEM8(0x009A)
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++#define PMIC_STATUS _SFR_MEM8(0x00A0)
++#define PMIC_INTPRI _SFR_MEM8(0x00A1)
++#define PMIC_CTRL _SFR_MEM8(0x00A2)
++
++/* PORTCFG - I/O port Configuration */
++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4)
++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6)
++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7)
++
++/* CRC - Cyclic Redundancy Checker */
++#define CRC_CTRL _SFR_MEM8(0x00D0)
++#define CRC_STATUS _SFR_MEM8(0x00D1)
++#define CRC_DATAIN _SFR_MEM8(0x00D3)
++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
++
++/* EDMA - Enhanced DMA Controller */
++#define EDMA_CTRL _SFR_MEM8(0x0100)
++#define EDMA_INTFLAGS _SFR_MEM8(0x0103)
++#define EDMA_STATUS _SFR_MEM8(0x0104)
++#define EDMA_TEMP _SFR_MEM8(0x0106)
++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110)
++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111)
++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113)
++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114)
++#define EDMA_CH0_TRFCNTL _SFR_MEM8(0x0116)
++#define EDMA_CH0_TRFCNTH _SFR_MEM8(0x0117)
++#define EDMA_CH0_ADDRL _SFR_MEM8(0x0118)
++#define EDMA_CH0_ADDRH _SFR_MEM8(0x0119)
++#define EDMA_CH0_DESTADDRL _SFR_MEM8(0x011C)
++#define EDMA_CH0_DESTADDRH _SFR_MEM8(0x011D)
++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120)
++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121)
++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123)
++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124)
++#define EDMA_CH1_TRFCNTL _SFR_MEM8(0x0126)
++#define EDMA_CH1_TRFCNTH _SFR_MEM8(0x0127)
++#define EDMA_CH1_ADDRL _SFR_MEM8(0x0128)
++#define EDMA_CH1_ADDRH _SFR_MEM8(0x0129)
++#define EDMA_CH1_DESTADDRL _SFR_MEM8(0x012C)
++#define EDMA_CH1_DESTADDRH _SFR_MEM8(0x012D)
++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130)
++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131)
++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133)
++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134)
++#define EDMA_CH2_TRFCNTL _SFR_MEM8(0x0136)
++#define EDMA_CH2_TRFCNTH _SFR_MEM8(0x0137)
++#define EDMA_CH2_ADDRL _SFR_MEM8(0x0138)
++#define EDMA_CH2_ADDRH _SFR_MEM8(0x0139)
++#define EDMA_CH2_DESTADDRL _SFR_MEM8(0x013C)
++#define EDMA_CH2_DESTADDRH _SFR_MEM8(0x013D)
++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140)
++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141)
++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143)
++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144)
++#define EDMA_CH3_TRFCNTL _SFR_MEM8(0x0146)
++#define EDMA_CH3_TRFCNTH _SFR_MEM8(0x0147)
++#define EDMA_CH3_ADDRL _SFR_MEM8(0x0148)
++#define EDMA_CH3_ADDRH _SFR_MEM8(0x0149)
++#define EDMA_CH3_DESTADDRL _SFR_MEM8(0x014C)
++#define EDMA_CH3_DESTADDRH _SFR_MEM8(0x014D)
++
++/* EVSYS - Event System */
++#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
++#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
++#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
++#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
++#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
++#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
++#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
++#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
++#define EVSYS_STROBE _SFR_MEM8(0x0190)
++#define EVSYS_DATA _SFR_MEM8(0x0191)
++#define EVSYS_DFCTRL _SFR_MEM8(0x0192)
++
++/* NVM - Non-volatile Memory Controller */
++#define NVM_ADDR0 _SFR_MEM8(0x01C0)
++#define NVM_ADDR1 _SFR_MEM8(0x01C1)
++#define NVM_ADDR2 _SFR_MEM8(0x01C2)
++#define NVM_DATA0 _SFR_MEM8(0x01C4)
++#define NVM_DATA1 _SFR_MEM8(0x01C5)
++#define NVM_DATA2 _SFR_MEM8(0x01C6)
++#define NVM_CMD _SFR_MEM8(0x01CA)
++#define NVM_CTRLA _SFR_MEM8(0x01CB)
++#define NVM_CTRLB _SFR_MEM8(0x01CC)
++#define NVM_INTCTRL _SFR_MEM8(0x01CD)
++#define NVM_STATUS _SFR_MEM8(0x01CF)
++#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
++
++/* ADC - Analog-to-Digital Converter */
++#define ADCA_CTRLA _SFR_MEM8(0x0200)
++#define ADCA_CTRLB _SFR_MEM8(0x0201)
++#define ADCA_REFCTRL _SFR_MEM8(0x0202)
++#define ADCA_EVCTRL _SFR_MEM8(0x0203)
++#define ADCA_PRESCALER _SFR_MEM8(0x0204)
++#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
++#define ADCA_TEMP _SFR_MEM8(0x0207)
++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208)
++#define ADCA_CAL _SFR_MEM16(0x020C)
++#define ADCA_CH0RES _SFR_MEM16(0x0210)
++#define ADCA_CMP _SFR_MEM16(0x0218)
++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
++#define ADCA_CH0_RES _SFR_MEM16(0x0224)
++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226)
++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227)
++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228)
++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229)
++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A)
++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B)
++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C)
++
++/* DAC - Digital-to-Analog Converter */
++#define DACA_CTRLA _SFR_MEM8(0x0300)
++#define DACA_CTRLB _SFR_MEM8(0x0301)
++#define DACA_CTRLC _SFR_MEM8(0x0302)
++#define DACA_EVCTRL _SFR_MEM8(0x0303)
++#define DACA_TIMCTRL _SFR_MEM8(0x0304)
++#define DACA_STATUS _SFR_MEM8(0x0305)
++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308)
++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309)
++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A)
++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B)
++#define DACA_CH0DATA _SFR_MEM16(0x0318)
++#define DACA_CH1DATA _SFR_MEM16(0x031A)
++
++/* AC - Analog Comparator */
++#define ACA_AC0CTRL _SFR_MEM8(0x0380)
++#define ACA_AC1CTRL _SFR_MEM8(0x0381)
++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
++#define ACA_CTRLA _SFR_MEM8(0x0384)
++#define ACA_CTRLB _SFR_MEM8(0x0385)
++#define ACA_WINCTRL _SFR_MEM8(0x0386)
++#define ACA_STATUS _SFR_MEM8(0x0387)
++#define ACA_CURRCTRL _SFR_MEM8(0x0388)
++#define ACA_CURRCALIB _SFR_MEM8(0x0389)
++
++/* RTC - Real-Time Counter */
++#define RTC_CTRL _SFR_MEM8(0x0400)
++#define RTC_STATUS _SFR_MEM8(0x0401)
++#define RTC_INTCTRL _SFR_MEM8(0x0402)
++#define RTC_INTFLAGS _SFR_MEM8(0x0403)
++#define RTC_TEMP _SFR_MEM8(0x0404)
++#define RTC_CALIB _SFR_MEM8(0x0406)
++#define RTC_CNT _SFR_MEM16(0x0408)
++#define RTC_PER _SFR_MEM16(0x040A)
++#define RTC_COMP _SFR_MEM16(0x040C)
++
++/* XCL - XMEGA Custom Logic */
++#define XCL_CTRLA _SFR_MEM8(0x0460)
++#define XCL_CTRLB _SFR_MEM8(0x0461)
++#define XCL_CTRLC _SFR_MEM8(0x0462)
++#define XCL_CTRLD _SFR_MEM8(0x0463)
++#define XCL_CTRLE _SFR_MEM8(0x0464)
++#define XCL_CTRLF _SFR_MEM8(0x0465)
++#define XCL_CTRLG _SFR_MEM8(0x0466)
++#define XCL_INTCTRL _SFR_MEM8(0x0467)
++#define XCL_INTFLAGS _SFR_MEM8(0x0468)
++#define XCL_PLC _SFR_MEM8(0x0469)
++#define XCL_CNTL _SFR_MEM8(0x046A)
++#define XCL_CNTH _SFR_MEM8(0x046B)
++#define XCL_CMPL _SFR_MEM8(0x046C)
++#define XCL_CMPH _SFR_MEM8(0x046D)
++#define XCL_PERCAPTL _SFR_MEM8(0x046E)
++#define XCL_PERCAPTH _SFR_MEM8(0x046F)
++
++/* TWI - Two-Wire Interface */
++#define TWIC_CTRL _SFR_MEM8(0x0480)
++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
++
++/* PORT - I/O Ports */
++#define PORTA_DIR _SFR_MEM8(0x0600)
++#define PORTA_DIRSET _SFR_MEM8(0x0601)
++#define PORTA_DIRCLR _SFR_MEM8(0x0602)
++#define PORTA_DIRTGL _SFR_MEM8(0x0603)
++#define PORTA_OUT _SFR_MEM8(0x0604)
++#define PORTA_OUTSET _SFR_MEM8(0x0605)
++#define PORTA_OUTCLR _SFR_MEM8(0x0606)
++#define PORTA_OUTTGL _SFR_MEM8(0x0607)
++#define PORTA_IN _SFR_MEM8(0x0608)
++#define PORTA_INTCTRL _SFR_MEM8(0x0609)
++#define PORTA_INTMASK _SFR_MEM8(0x060A)
++#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
++#define PORTA_REMAP _SFR_MEM8(0x060E)
++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
++
++/* PORT - I/O Ports */
++#define PORTC_DIR _SFR_MEM8(0x0640)
++#define PORTC_DIRSET _SFR_MEM8(0x0641)
++#define PORTC_DIRCLR _SFR_MEM8(0x0642)
++#define PORTC_DIRTGL _SFR_MEM8(0x0643)
++#define PORTC_OUT _SFR_MEM8(0x0644)
++#define PORTC_OUTSET _SFR_MEM8(0x0645)
++#define PORTC_OUTCLR _SFR_MEM8(0x0646)
++#define PORTC_OUTTGL _SFR_MEM8(0x0647)
++#define PORTC_IN _SFR_MEM8(0x0648)
++#define PORTC_INTCTRL _SFR_MEM8(0x0649)
++#define PORTC_INTMASK _SFR_MEM8(0x064A)
++#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
++#define PORTC_REMAP _SFR_MEM8(0x064E)
++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
++
++/* PORT - I/O Ports */
++#define PORTD_DIR _SFR_MEM8(0x0660)
++#define PORTD_DIRSET _SFR_MEM8(0x0661)
++#define PORTD_DIRCLR _SFR_MEM8(0x0662)
++#define PORTD_DIRTGL _SFR_MEM8(0x0663)
++#define PORTD_OUT _SFR_MEM8(0x0664)
++#define PORTD_OUTSET _SFR_MEM8(0x0665)
++#define PORTD_OUTCLR _SFR_MEM8(0x0666)
++#define PORTD_OUTTGL _SFR_MEM8(0x0667)
++#define PORTD_IN _SFR_MEM8(0x0668)
++#define PORTD_INTCTRL _SFR_MEM8(0x0669)
++#define PORTD_INTMASK _SFR_MEM8(0x066A)
++#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
++#define PORTD_REMAP _SFR_MEM8(0x066E)
++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
++
++/* PORT - I/O Ports */
++#define PORTR_DIR _SFR_MEM8(0x07E0)
++#define PORTR_DIRSET _SFR_MEM8(0x07E1)
++#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
++#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
++#define PORTR_OUT _SFR_MEM8(0x07E4)
++#define PORTR_OUTSET _SFR_MEM8(0x07E5)
++#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
++#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
++#define PORTR_IN _SFR_MEM8(0x07E8)
++#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
++#define PORTR_INTMASK _SFR_MEM8(0x07EA)
++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
++#define PORTR_REMAP _SFR_MEM8(0x07EE)
++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
++
++/* TC4 - 16-bit Timer/Counter 4 */
++#define TCC4_CTRLA _SFR_MEM8(0x0800)
++#define TCC4_CTRLB _SFR_MEM8(0x0801)
++#define TCC4_CTRLC _SFR_MEM8(0x0802)
++#define TCC4_CTRLD _SFR_MEM8(0x0803)
++#define TCC4_CTRLE _SFR_MEM8(0x0804)
++#define TCC4_CTRLF _SFR_MEM8(0x0805)
++#define TCC4_INTCTRLA _SFR_MEM8(0x0806)
++#define TCC4_INTCTRLB _SFR_MEM8(0x0807)
++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808)
++#define TCC4_CTRLGSET _SFR_MEM8(0x0809)
++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A)
++#define TCC4_CTRLHSET _SFR_MEM8(0x080B)
++#define TCC4_INTFLAGS _SFR_MEM8(0x080C)
++#define TCC4_TEMP _SFR_MEM8(0x080F)
++#define TCC4_CNT _SFR_MEM16(0x0820)
++#define TCC4_PER _SFR_MEM16(0x0826)
++#define TCC4_CCA _SFR_MEM16(0x0828)
++#define TCC4_CCB _SFR_MEM16(0x082A)
++#define TCC4_CCC _SFR_MEM16(0x082C)
++#define TCC4_CCD _SFR_MEM16(0x082E)
++#define TCC4_PERBUF _SFR_MEM16(0x0836)
++#define TCC4_CCABUF _SFR_MEM16(0x0838)
++#define TCC4_CCBBUF _SFR_MEM16(0x083A)
++#define TCC4_CCCBUF _SFR_MEM16(0x083C)
++#define TCC4_CCDBUF _SFR_MEM16(0x083E)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCC5_CTRLA _SFR_MEM8(0x0840)
++#define TCC5_CTRLB _SFR_MEM8(0x0841)
++#define TCC5_CTRLC _SFR_MEM8(0x0842)
++#define TCC5_CTRLD _SFR_MEM8(0x0843)
++#define TCC5_CTRLE _SFR_MEM8(0x0844)
++#define TCC5_CTRLF _SFR_MEM8(0x0845)
++#define TCC5_INTCTRLA _SFR_MEM8(0x0846)
++#define TCC5_INTCTRLB _SFR_MEM8(0x0847)
++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848)
++#define TCC5_CTRLGSET _SFR_MEM8(0x0849)
++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A)
++#define TCC5_CTRLHSET _SFR_MEM8(0x084B)
++#define TCC5_INTFLAGS _SFR_MEM8(0x084C)
++#define TCC5_TEMP _SFR_MEM8(0x084F)
++#define TCC5_CNT _SFR_MEM16(0x0860)
++#define TCC5_PER _SFR_MEM16(0x0866)
++#define TCC5_CCA _SFR_MEM16(0x0868)
++#define TCC5_CCB _SFR_MEM16(0x086A)
++#define TCC5_PERBUF _SFR_MEM16(0x0876)
++#define TCC5_CCABUF _SFR_MEM16(0x0878)
++#define TCC5_CCBBUF _SFR_MEM16(0x087A)
++
++/* FAULT - Fault Extension */
++#define FAULTC4_CTRLA _SFR_MEM8(0x0880)
++#define FAULTC4_CTRLB _SFR_MEM8(0x0881)
++#define FAULTC4_CTRLC _SFR_MEM8(0x0882)
++#define FAULTC4_CTRLD _SFR_MEM8(0x0883)
++#define FAULTC4_CTRLE _SFR_MEM8(0x0884)
++#define FAULTC4_STATUS _SFR_MEM8(0x0885)
++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886)
++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887)
++
++/* FAULT - Fault Extension */
++#define FAULTC5_CTRLA _SFR_MEM8(0x0890)
++#define FAULTC5_CTRLB _SFR_MEM8(0x0891)
++#define FAULTC5_CTRLC _SFR_MEM8(0x0892)
++#define FAULTC5_CTRLD _SFR_MEM8(0x0893)
++#define FAULTC5_CTRLE _SFR_MEM8(0x0894)
++#define FAULTC5_STATUS _SFR_MEM8(0x0895)
++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896)
++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897)
++
++/* WEX - Waveform Extension */
++#define WEXC_CTRL _SFR_MEM8(0x08A0)
++#define WEXC_DTBOTH _SFR_MEM8(0x08A1)
++#define WEXC_DTLS _SFR_MEM8(0x08A2)
++#define WEXC_DTHS _SFR_MEM8(0x08A3)
++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4)
++#define WEXC_STATUSSET _SFR_MEM8(0x08A5)
++#define WEXC_SWAP _SFR_MEM8(0x08A6)
++#define WEXC_PGO _SFR_MEM8(0x08A7)
++#define WEXC_PGV _SFR_MEM8(0x08A8)
++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA)
++#define WEXC_PGOBUF _SFR_MEM8(0x08AB)
++#define WEXC_PGVBUF _SFR_MEM8(0x08AC)
++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF)
++
++/* HIRES - High-Resolution Extension */
++#define HIRESC_CTRLA _SFR_MEM8(0x08B0)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTC0_DATA _SFR_MEM8(0x08C0)
++#define USARTC0_STATUS _SFR_MEM8(0x08C1)
++#define USARTC0_CTRLA _SFR_MEM8(0x08C2)
++#define USARTC0_CTRLB _SFR_MEM8(0x08C3)
++#define USARTC0_CTRLC _SFR_MEM8(0x08C4)
++#define USARTC0_CTRLD _SFR_MEM8(0x08C5)
++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6)
++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7)
++
++/* SPI - Serial Peripheral Interface with Buffer Modes */
++#define SPIC_CTRL _SFR_MEM8(0x08E0)
++#define SPIC_INTCTRL _SFR_MEM8(0x08E1)
++#define SPIC_STATUS _SFR_MEM8(0x08E2)
++#define SPIC_DATA _SFR_MEM8(0x08E3)
++#define SPIC_CTRLB _SFR_MEM8(0x08E4)
++
++/* IRCOM - IR Communication Module */
++#define IRCOM_CTRL _SFR_MEM8(0x08F8)
++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
++
++/* TC5 - 16-bit Timer/Counter 5 */
++#define TCD5_CTRLA _SFR_MEM8(0x0940)
++#define TCD5_CTRLB _SFR_MEM8(0x0941)
++#define TCD5_CTRLC _SFR_MEM8(0x0942)
++#define TCD5_CTRLD _SFR_MEM8(0x0943)
++#define TCD5_CTRLE _SFR_MEM8(0x0944)
++#define TCD5_CTRLF _SFR_MEM8(0x0945)
++#define TCD5_INTCTRLA _SFR_MEM8(0x0946)
++#define TCD5_INTCTRLB _SFR_MEM8(0x0947)
++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948)
++#define TCD5_CTRLGSET _SFR_MEM8(0x0949)
++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A)
++#define TCD5_CTRLHSET _SFR_MEM8(0x094B)
++#define TCD5_INTFLAGS _SFR_MEM8(0x094C)
++#define TCD5_TEMP _SFR_MEM8(0x094F)
++#define TCD5_CNT _SFR_MEM16(0x0960)
++#define TCD5_PER _SFR_MEM16(0x0966)
++#define TCD5_CCA _SFR_MEM16(0x0968)
++#define TCD5_CCB _SFR_MEM16(0x096A)
++#define TCD5_PERBUF _SFR_MEM16(0x0976)
++#define TCD5_CCABUF _SFR_MEM16(0x0978)
++#define TCD5_CCBBUF _SFR_MEM16(0x097A)
++
++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */
++#define USARTD0_DATA _SFR_MEM8(0x09C0)
++#define USARTD0_STATUS _SFR_MEM8(0x09C1)
++#define USARTD0_CTRLA _SFR_MEM8(0x09C2)
++#define USARTD0_CTRLB _SFR_MEM8(0x09C3)
++#define USARTD0_CTRLC _SFR_MEM8(0x09C4)
++#define USARTD0_CTRLD _SFR_MEM8(0x09C5)
++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6)
++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7)
++
++
++
++/*================== Bitfield Definitions ================== */
++
++/* VPORT - Virtual Ports */
++/* VPORT.INTFLAGS bit masks and bit positions */
++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */
++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */
++
++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */
++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */
++
++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */
++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */
++
++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */
++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */
++
++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */
++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */
++
++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */
++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */
++
++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */
++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */
++
++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */
++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */
++
++/* XOCD - On-Chip Debug System */
++/* OCD.OCDR1 bit masks and bit positions */
++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
++
++/* CPU - CPU */
++/* CPU.CCP bit masks and bit positions */
++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
++#define CPU_CCP_gp 0 /* CCP signature group position. */
++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
++
++/* CPU.SREG bit masks and bit positions */
++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
++
++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
++#define CPU_T_bp 6 /* Transfer Bit bit position. */
++
++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
++#define CPU_H_bp 5 /* Half Carry Flag bit position. */
++
++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
++
++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
++
++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
++#define CPU_N_bp 2 /* Negative Flag bit position. */
++
++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
++#define CPU_Z_bp 1 /* Zero Flag bit position. */
++
++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
++#define CPU_C_bp 0 /* Carry Flag bit position. */
++
++/* CLK - Clock System */
++/* CLK.CTRL bit masks and bit positions */
++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
++
++/* CLK.PSCTRL bit masks and bit positions */
++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
++
++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
++
++/* CLK.LOCK bit masks and bit positions */
++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
++
++/* CLK.RTCCTRL bit masks and bit positions */
++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
++
++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */
++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */
++
++/* PR.PRGEN bit masks and bit positions */
++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */
++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */
++
++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
++#define PR_RTC_bp 2 /* Real-time Counter bit position. */
++
++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
++#define PR_EVSYS_bp 1 /* Event System bit position. */
++
++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */
++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */
++
++/* PR.PRPA bit masks and bit positions */
++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
++#define PR_DAC_bp 2 /* Port A DAC bit position. */
++
++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
++#define PR_ADC_bp 1 /* Port A ADC bit position. */
++
++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
++
++/* PR.PRPC bit masks and bit positions */
++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
++
++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
++#define PR_USART0_bp 4 /* Port C USART0 bit position. */
++
++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
++#define PR_SPI_bp 3 /* Port C SPI bit position. */
++
++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */
++#define PR_HIRES_bp 2 /* Port C WEX bit position. */
++
++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */
++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */
++
++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */
++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */
++
++/* PR.PRPD bit masks and bit positions */
++/* PR_USART0 Predefined. */
++/* PR_USART0 Predefined. */
++
++/* PR_TC5 Predefined. */
++/* PR_TC5 Predefined. */
++
++/* SLEEP - Sleep Controller */
++/* SLEEP.CTRL bit masks and bit positions */
++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
++
++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
++
++/* OSC - Oscillator */
++/* OSC.CTRL bit masks and bit positions */
++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */
++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */
++
++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */
++
++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
++
++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
++
++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */
++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */
++
++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */
++
++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */
++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */
++
++/* OSC.STATUS bit masks and bit positions */
++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */
++
++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
++
++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
++
++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */
++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */
++
++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */
++
++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */
++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */
++
++/* OSC.XOSCCTRL bit masks and bit positions */
++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
++
++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */
++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */
++
++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */
++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */
++
++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */
++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */
++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */
++
++/* OSC.XOSCFAIL bit masks and bit positions */
++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */
++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */
++
++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */
++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */
++
++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */
++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */
++
++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */
++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */
++
++/* OSC.PLLCTRL bit masks and bit positions */
++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
++
++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */
++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */
++
++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
++
++/* OSC.DFLLCTRL bit masks and bit positions */
++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */
++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */
++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */
++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */
++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */
++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */
++
++/* OSC.RC8MCAL bit masks and bit positions */
++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */
++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */
++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */
++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */
++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */
++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */
++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */
++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */
++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */
++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */
++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */
++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */
++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */
++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */
++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */
++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */
++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */
++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */
++
++/* DFLL - DFLL */
++/* DFLL.CTRL bit masks and bit positions */
++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
++
++/* DFLL.CALA bit masks and bit positions */
++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */
++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */
++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */
++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */
++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */
++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */
++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */
++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */
++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */
++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */
++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */
++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */
++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */
++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */
++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */
++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */
++
++/* DFLL.CALB bit masks and bit positions */
++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */
++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */
++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */
++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */
++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */
++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */
++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */
++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */
++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */
++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */
++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */
++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */
++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */
++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */
++
++/* RST - Reset */
++/* RST.STATUS bit masks and bit positions */
++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
++
++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
++
++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
++
++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
++
++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
++
++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
++
++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
++
++/* RST.CTRL bit masks and bit positions */
++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
++#define RST_SWRST_bp 0 /* Software Reset bit position. */
++
++/* WDT - Watch-Dog Timer */
++/* WDT.CTRL bit masks and bit positions */
++#define WDT_PER_gm 0x3C /* Period group mask. */
++#define WDT_PER_gp 2 /* Period group position. */
++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
++#define WDT_PER0_bp 2 /* Period bit 0 position. */
++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
++#define WDT_PER1_bp 3 /* Period bit 1 position. */
++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
++#define WDT_PER2_bp 4 /* Period bit 2 position. */
++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
++#define WDT_PER3_bp 5 /* Period bit 3 position. */
++
++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
++#define WDT_ENABLE_bp 1 /* Enable bit position. */
++
++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
++#define WDT_CEN_bp 0 /* Change Enable bit position. */
++
++/* WDT.WINCTRL bit masks and bit positions */
++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
++
++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
++
++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
++
++/* WDT.STATUS bit masks and bit positions */
++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
++
++/* MCU - MCU Control */
++/* MCU.ANAINIT bit masks and bit positions */
++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */
++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */
++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */
++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */
++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */
++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */
++
++/* MCU.EVSYSLOCK bit masks and bit positions */
++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
++
++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
++
++/* MCU.WEXLOCK bit masks and bit positions */
++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */
++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */
++
++/* MCU.FAULTLOCK bit masks and bit positions */
++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */
++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */
++
++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */
++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */
++
++/* PMIC - Programmable Multi-level Interrupt Controller */
++/* PMIC.STATUS bit masks and bit positions */
++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
++
++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
++
++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
++
++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
++
++/* PMIC.CTRL bit masks and bit positions */
++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
++
++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
++
++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
++
++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
++
++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
++
++/* PORTCFG - Port Configuration */
++/* PORTCFG.CLKOUT bit masks and bit positions */
++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */
++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */
++
++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */
++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */
++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */
++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */
++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */
++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */
++
++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */
++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */
++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */
++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */
++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */
++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */
++
++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
++
++/* PORTCFG.ACEVOUT bit masks and bit positions */
++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */
++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */
++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */
++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */
++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */
++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */
++
++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */
++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */
++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */
++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */
++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */
++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */
++
++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */
++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */
++
++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */
++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */
++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */
++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */
++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */
++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */
++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */
++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */
++
++/* PORTCFG.SRLCTRL bit masks and bit positions */
++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */
++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */
++
++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */
++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */
++
++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */
++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */
++
++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */
++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */
++
++/* CRC - Cyclic Redundancy Checker */
++/* CRC.CTRL bit masks and bit positions */
++#define CRC_RESET_gm 0xC0 /* Reset group mask. */
++#define CRC_RESET_gp 6 /* Reset group position. */
++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */
++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */
++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */
++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */
++
++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */
++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */
++
++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */
++#define CRC_SOURCE_gp 0 /* Input Source group position. */
++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */
++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */
++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */
++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */
++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */
++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */
++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */
++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */
++
++/* CRC.STATUS bit masks and bit positions */
++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */
++#define CRC_ZERO_bp 1 /* Zero detection bit position. */
++
++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */
++#define CRC_BUSY_bp 0 /* Busy bit position. */
++
++/* EDMA - Enhanced DMA Controller */
++/* EDMA.CTRL bit masks and bit positions */
++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */
++#define EDMA_ENABLE_bp 7 /* Enable bit position. */
++
++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */
++#define EDMA_RESET_bp 6 /* Software Reset bit position. */
++
++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */
++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */
++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */
++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */
++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */
++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */
++
++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */
++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */
++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */
++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */
++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */
++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */
++
++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */
++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */
++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */
++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */
++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */
++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */
++
++/* EDMA.INTFLAGS bit masks and bit positions */
++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
++
++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
++
++/* EDMA.STATUS bit masks and bit positions */
++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */
++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */
++
++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */
++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */
++
++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */
++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */
++
++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */
++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */
++
++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */
++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */
++
++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */
++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */
++
++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */
++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */
++
++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */
++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */
++
++/* EDMA_CH.CTRLA bit masks and bit positions */
++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
++
++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
++
++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
++
++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
++
++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
++
++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */
++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */
++
++/* EDMA_CH.CTRLB bit masks and bit positions */
++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */
++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */
++
++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */
++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */
++
++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */
++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */
++
++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */
++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */
++
++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */
++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */
++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */
++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */
++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */
++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */
++
++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */
++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */
++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */
++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */
++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */
++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */
++
++/* EDMA_CH.ADDRCTRL bit masks and bit positions */
++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */
++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */
++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */
++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */
++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */
++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */
++
++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */
++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */
++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */
++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */
++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */
++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */
++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */
++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */
++
++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */
++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */
++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */
++
++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */
++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */
++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */
++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */
++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */
++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */
++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */
++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */
++
++/* EDMA_CH.TRIGSRC bit masks and bit positions */
++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
++
++/* EVSYS - Event System */
++/* EVSYS.CH0MUX bit masks and bit positions */
++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
++
++/* EVSYS.CH1MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH2MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH3MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH4MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH5MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH6MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH7MUX bit masks and bit positions */
++/* EVSYS_CHMUX Predefined. */
++/* EVSYS_CHMUX Predefined. */
++
++/* EVSYS.CH0CTRL bit masks and bit positions */
++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */
++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */
++
++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
++
++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
++
++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
++
++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
++
++/* EVSYS.CH1CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH2CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH3CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH4CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH5CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH6CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.CH7CTRL bit masks and bit positions */
++/* EVSYS_DIGFILT Predefined. */
++/* EVSYS_DIGFILT Predefined. */
++
++/* EVSYS.DFCTRL bit masks and bit positions */
++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */
++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */
++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */
++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */
++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */
++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */
++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */
++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */
++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */
++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */
++
++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */
++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */
++
++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */
++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */
++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */
++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */
++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */
++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */
++
++/* NVM - Non Volatile Memory Controller */
++/* NVM.CMD bit masks and bit positions */
++#define NVM_CMD_gm 0x7F /* Command group mask. */
++#define NVM_CMD_gp 0 /* Command group position. */
++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define NVM_CMD0_bp 0 /* Command bit 0 position. */
++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define NVM_CMD1_bp 1 /* Command bit 1 position. */
++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
++#define NVM_CMD2_bp 2 /* Command bit 2 position. */
++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
++#define NVM_CMD3_bp 3 /* Command bit 3 position. */
++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
++#define NVM_CMD4_bp 4 /* Command bit 4 position. */
++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
++#define NVM_CMD5_bp 5 /* Command bit 5 position. */
++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
++#define NVM_CMD6_bp 6 /* Command bit 6 position. */
++
++/* NVM.CTRLA bit masks and bit positions */
++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
++
++/* NVM.CTRLB bit masks and bit positions */
++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
++
++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
++
++/* NVM.INTCTRL bit masks and bit positions */
++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
++
++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
++
++/* NVM.STATUS bit masks and bit positions */
++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
++
++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
++
++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
++
++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
++
++/* NVM.LOCKBITS bit masks and bit positions */
++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* ADC - Analog/Digital Converter */
++/* ADC_CH.CTRL bit masks and bit positions */
++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
++
++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */
++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */
++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */
++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */
++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */
++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */
++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */
++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */
++
++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
++
++/* ADC_CH.MUXCTRL bit masks and bit positions */
++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */
++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */
++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */
++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */
++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */
++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */
++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */
++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */
++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */
++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */
++
++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */
++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */
++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */
++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */
++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */
++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */
++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */
++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */
++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */
++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */
++
++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */
++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */
++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */
++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */
++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */
++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */
++
++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */
++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */
++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */
++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */
++
++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */
++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */
++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */
++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */
++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */
++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */
++
++/* ADC_CH.INTCTRL bit masks and bit positions */
++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
++
++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
++
++/* ADC_CH.INTFLAGS bit masks and bit positions */
++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */
++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */
++
++/* ADC_CH.SCAN bit masks and bit positions */
++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */
++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */
++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */
++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */
++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */
++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */
++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */
++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */
++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */
++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */
++
++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */
++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */
++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */
++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */
++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */
++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */
++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */
++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */
++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */
++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */
++
++/* ADC_CH.CORRCTRL bit masks and bit positions */
++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */
++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */
++
++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */
++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */
++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */
++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */
++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */
++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */
++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */
++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */
++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */
++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */
++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.GAINCORR1 bit masks and bit positions */
++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */
++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */
++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */
++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */
++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */
++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */
++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */
++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */
++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */
++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */
++
++/* ADC_CH.AVGCTRL bit masks and bit positions */
++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */
++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */
++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */
++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */
++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */
++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */
++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */
++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */
++
++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */
++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */
++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */
++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */
++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */
++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */
++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */
++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */
++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */
++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */
++
++/* ADC.CTRLA bit masks and bit positions */
++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */
++#define ADC_START_bp 2 /* Start Conversion bit position. */
++
++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
++
++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
++
++/* ADC.CTRLB bit masks and bit positions */
++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */
++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */
++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */
++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */
++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */
++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */
++
++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
++
++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
++
++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
++
++/* ADC.REFCTRL bit masks and bit positions */
++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
++
++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
++
++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
++
++/* ADC.EVCTRL bit masks and bit positions */
++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
++
++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
++#define ADC_EVACT_gp 0 /* Event Action Select group position. */
++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
++
++/* ADC.PRESCALER bit masks and bit positions */
++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
++
++/* ADC.INTFLAGS bit masks and bit positions */
++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
++
++/* ADC.SAMPCTRL bit masks and bit positions */
++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */
++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */
++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */
++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */
++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */
++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */
++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */
++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */
++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */
++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */
++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */
++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */
++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */
++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */
++
++/* DAC - Digital/Analog Converter */
++/* DAC.CTRLA bit masks and bit positions */
++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
++
++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
++
++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
++
++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
++
++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define DAC_ENABLE_bp 0 /* Enable bit position. */
++
++/* DAC.CTRLB bit masks and bit positions */
++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
++#define DAC_CHSEL_gp 5 /* Channel Select group position. */
++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
++
++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
++
++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
++
++/* DAC.CTRLC bit masks and bit positions */
++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
++#define DAC_REFSEL_gp 3 /* Reference Select group position. */
++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
++
++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
++
++/* DAC.EVCTRL bit masks and bit positions */
++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */
++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */
++
++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
++
++/* DAC.TIMCTRL bit masks and bit positions */
++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
++
++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
++
++/* DAC.STATUS bit masks and bit positions */
++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
++
++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
++
++/* DAC.CH0GAINCAL bit masks and bit positions */
++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH0OFFSETCAL bit masks and bit positions */
++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* DAC.CH1GAINCAL bit masks and bit positions */
++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */
++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */
++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */
++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */
++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */
++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */
++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */
++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */
++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */
++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */
++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */
++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */
++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */
++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */
++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */
++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */
++
++/* DAC.CH1OFFSETCAL bit masks and bit positions */
++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */
++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */
++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */
++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */
++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */
++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */
++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */
++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */
++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */
++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */
++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */
++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */
++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */
++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */
++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */
++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */
++
++/* AC - Analog Comparator */
++/* AC.AC0CTRL bit masks and bit positions */
++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
++
++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
++
++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
++
++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
++#define AC_ENABLE_bp 0 /* Enable bit position. */
++
++/* AC.AC1CTRL bit masks and bit positions */
++/* AC_INTMODE Predefined. */
++/* AC_INTMODE Predefined. */
++
++/* AC_INTLVL Predefined. */
++/* AC_INTLVL Predefined. */
++
++/* AC_HYSMODE Predefined. */
++/* AC_HYSMODE Predefined. */
++
++/* AC_ENABLE Predefined. */
++/* AC_ENABLE Predefined. */
++
++/* AC.AC0MUXCTRL bit masks and bit positions */
++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
++
++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
++
++/* AC.AC1MUXCTRL bit masks and bit positions */
++/* AC_MUXPOS Predefined. */
++/* AC_MUXPOS Predefined. */
++
++/* AC_MUXNEG Predefined. */
++/* AC_MUXNEG Predefined. */
++
++/* AC.CTRLA bit masks and bit positions */
++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */
++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */
++
++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */
++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */
++
++/* AC.CTRLB bit masks and bit positions */
++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
++
++/* AC.WINCTRL bit masks and bit positions */
++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
++
++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
++
++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
++
++/* AC.STATUS bit masks and bit positions */
++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
++#define AC_WSTATE_gp 6 /* Window Mode State group position. */
++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
++
++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */
++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */
++
++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */
++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */
++
++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
++
++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */
++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */
++
++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */
++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */
++
++/* AC.CURRCTRL bit masks and bit positions */
++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */
++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */
++
++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */
++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */
++
++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */
++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */
++
++/* AC.CURRCALIB bit masks and bit positions */
++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */
++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */
++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */
++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */
++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */
++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */
++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */
++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */
++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */
++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */
++
++/* RTC - Real-Time Clounter */
++/* RTC.CTRL bit masks and bit positions */
++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */
++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */
++
++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
++
++/* RTC.STATUS bit masks and bit positions */
++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
++
++/* RTC.INTCTRL bit masks and bit positions */
++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
++
++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
++
++/* RTC.INTFLAGS bit masks and bit positions */
++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
++
++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
++
++/* RTC.CALIB bit masks and bit positions */
++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */
++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */
++
++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */
++#define RTC_ERROR_gp 0 /* Error Value group position. */
++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */
++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */
++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */
++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */
++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */
++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */
++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */
++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */
++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */
++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */
++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */
++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */
++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */
++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */
++
++/* XCL - XMEGA Custom Logic */
++/* XCL.CTRLA bit masks and bit positions */
++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */
++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */
++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */
++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */
++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */
++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */
++
++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */
++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */
++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */
++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */
++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */
++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */
++
++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */
++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */
++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */
++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */
++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */
++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */
++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */
++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */
++
++/* XCL.CTRLB bit masks and bit positions */
++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */
++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */
++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */
++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */
++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */
++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */
++
++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */
++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */
++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */
++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */
++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */
++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */
++
++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */
++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */
++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */
++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */
++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */
++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */
++
++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */
++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */
++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */
++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */
++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */
++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */
++
++/* XCL.CTRLC bit masks and bit positions */
++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */
++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */
++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */
++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */
++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */
++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */
++
++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */
++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */
++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */
++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */
++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */
++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */
++
++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */
++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */
++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */
++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */
++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */
++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */
++
++/* XCL.CTRLD bit masks and bit positions */
++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */
++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */
++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */
++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */
++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */
++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */
++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */
++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */
++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */
++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */
++
++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */
++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */
++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */
++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */
++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */
++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */
++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */
++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */
++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */
++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */
++
++/* XCL.CTRLE bit masks and bit positions */
++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */
++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */
++
++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */
++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */
++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */
++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */
++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */
++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */
++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */
++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */
++
++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */
++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */
++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
++
++/* XCL.CTRLF bit masks and bit positions */
++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */
++#define XCL_CMDEN_gp 6 /* Command Enable group position. */
++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */
++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */
++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */
++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */
++
++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */
++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */
++
++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */
++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */
++
++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */
++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */
++
++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */
++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */
++
++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */
++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */
++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */
++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */
++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */
++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */
++
++/* XCL.CTRLG bit masks and bit positions */
++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */
++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */
++
++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */
++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */
++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */
++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */
++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */
++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */
++
++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */
++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */
++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */
++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */
++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */
++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */
++
++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */
++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */
++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */
++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */
++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */
++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */
++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */
++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */
++
++/* XCL.INTCTRL bit masks and bit positions */
++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */
++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */
++
++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */
++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */
++
++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */
++
++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */
++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */
++
++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */
++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */
++
++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */
++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */
++
++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */
++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */
++
++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */
++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */
++
++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */
++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */
++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */
++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */
++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */
++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */
++
++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */
++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */
++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */
++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */
++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */
++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */
++
++/* XCL.INTFLAGS bit masks and bit positions */
++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */
++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */
++
++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */
++
++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */
++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */
++
++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */
++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */
++
++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */
++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */
++
++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */
++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */
++
++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */
++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */
++
++/* XCL.PLC bit masks and bit positions */
++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */
++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */
++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */
++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */
++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */
++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */
++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */
++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */
++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */
++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */
++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */
++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */
++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */
++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */
++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */
++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */
++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */
++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */
++
++/* XCL.CNTL bit masks and bit positions */
++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */
++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */
++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */
++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */
++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */
++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */
++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */
++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */
++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */
++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */
++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */
++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */
++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */
++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */
++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */
++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */
++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */
++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */
++
++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */
++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */
++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */
++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */
++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */
++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */
++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */
++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */
++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */
++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */
++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */
++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */
++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */
++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */
++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */
++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */
++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */
++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */
++
++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */
++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */
++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */
++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */
++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */
++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */
++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */
++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */
++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */
++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */
++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */
++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */
++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */
++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */
++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */
++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */
++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */
++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */
++
++/* XCL.CNTH bit masks and bit positions */
++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */
++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */
++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */
++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */
++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */
++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */
++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */
++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */
++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */
++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */
++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */
++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */
++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */
++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */
++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */
++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */
++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */
++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */
++
++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */
++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */
++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */
++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */
++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */
++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */
++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */
++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */
++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */
++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */
++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */
++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */
++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */
++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */
++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */
++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */
++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */
++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */
++
++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */
++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */
++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */
++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */
++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */
++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */
++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */
++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */
++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */
++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */
++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */
++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */
++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */
++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */
++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */
++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */
++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */
++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */
++
++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */
++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */
++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */
++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */
++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */
++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */
++
++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */
++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */
++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */
++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */
++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */
++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */
++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */
++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */
++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */
++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */
++
++/* XCL.CMPL bit masks and bit positions */
++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */
++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */
++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */
++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */
++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */
++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */
++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */
++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */
++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */
++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */
++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */
++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */
++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */
++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */
++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */
++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */
++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */
++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */
++
++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */
++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */
++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */
++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */
++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */
++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */
++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */
++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */
++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */
++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */
++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */
++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */
++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */
++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */
++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */
++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */
++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */
++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */
++
++/* XCL.CMPH bit masks and bit positions */
++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */
++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */
++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */
++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */
++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */
++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */
++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */
++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */
++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */
++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */
++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */
++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */
++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */
++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */
++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */
++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */
++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */
++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */
++
++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */
++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */
++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */
++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */
++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */
++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */
++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */
++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */
++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */
++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */
++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */
++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */
++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */
++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */
++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */
++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */
++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */
++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */
++
++/* XCL.PERCAPTL bit masks and bit positions */
++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */
++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */
++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */
++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */
++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */
++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */
++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */
++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */
++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */
++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */
++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */
++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */
++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */
++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */
++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */
++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */
++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */
++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */
++
++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */
++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */
++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */
++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */
++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */
++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */
++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */
++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */
++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */
++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */
++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */
++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */
++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */
++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */
++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */
++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */
++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */
++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */
++
++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */
++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */
++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */
++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */
++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */
++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */
++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */
++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */
++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */
++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */
++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */
++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */
++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */
++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */
++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */
++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */
++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */
++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */
++
++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */
++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */
++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */
++
++/* XCL.PERCAPTH bit masks and bit positions */
++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */
++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */
++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */
++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */
++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */
++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */
++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */
++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */
++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */
++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */
++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */
++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */
++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */
++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */
++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */
++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */
++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */
++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */
++
++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */
++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */
++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */
++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */
++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */
++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */
++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */
++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */
++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */
++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */
++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */
++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */
++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */
++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */
++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */
++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */
++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */
++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */
++
++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */
++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */
++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */
++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */
++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */
++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */
++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */
++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */
++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */
++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */
++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */
++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */
++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */
++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */
++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */
++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */
++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */
++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */
++
++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */
++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */
++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */
++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */
++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */
++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */
++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */
++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */
++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */
++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */
++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */
++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */
++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */
++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */
++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */
++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */
++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */
++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */
++
++/* TWI - Two-Wire Interface */
++/* TWI.CTRL bit masks and bit positions */
++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */
++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */
++
++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */
++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */
++
++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */
++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */
++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */
++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */
++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */
++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */
++
++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */
++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */
++
++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */
++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */
++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */
++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */
++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */
++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */
++
++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
++
++/* TWI_MASTER.CTRLA bit masks and bit positions */
++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
++
++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
++
++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
++
++/* TWI_MASTER.CTRLB bit masks and bit positions */
++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
++
++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
++
++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_MASTER.CTRLC bit masks and bit positions */
++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
++#define TWI_MASTER_CMD_gp 0 /* Command group position. */
++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_MASTER.STATUS bit masks and bit positions */
++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
++
++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
++
++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
++
++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
++
++/* TWI_SLAVE.CTRLA bit masks and bit positions */
++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
++
++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
++
++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
++
++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
++
++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
++
++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
++
++/* TWI_SLAVE.CTRLB bit masks and bit positions */
++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
++
++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
++
++/* TWI_SLAVE.STATUS bit masks and bit positions */
++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
++
++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
++
++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
++
++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
++
++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
++
++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
++
++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
++
++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
++
++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
++
++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
++
++/* PORT - Port Configuration */
++/* PORT.INTCTRL bit masks and bit positions */
++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */
++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */
++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */
++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */
++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */
++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */
++
++/* PORT.INTFLAGS bit masks and bit positions */
++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */
++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */
++
++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */
++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */
++
++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */
++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */
++
++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */
++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */
++
++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */
++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */
++
++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */
++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */
++
++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */
++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */
++
++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */
++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */
++
++/* PORT.REMAP bit masks and bit positions */
++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */
++#define PORT_USART0_bp 4 /* Usart0 bit position. */
++
++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */
++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */
++
++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */
++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */
++
++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */
++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */
++
++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */
++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */
++
++/* PORT.PIN0CTRL bit masks and bit positions */
++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
++
++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
++
++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
++
++/* PORT.PIN1CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN2CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN3CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN4CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN5CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN6CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* PORT.PIN7CTRL bit masks and bit positions */
++/* PORT_INVEN Predefined. */
++/* PORT_INVEN Predefined. */
++
++/* PORT_OPC Predefined. */
++/* PORT_OPC Predefined. */
++
++/* PORT_ISC Predefined. */
++/* PORT_ISC Predefined. */
++
++/* TC - 16-bit Timer/Counter With PWM */
++/* TC4.CTRLA bit masks and bit positions */
++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC4.CTRLB bit masks and bit positions */
++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC4.CTRLC bit masks and bit positions */
++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */
++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */
++
++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */
++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */
++
++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */
++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */
++
++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */
++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */
++
++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */
++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */
++
++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */
++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */
++
++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */
++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */
++
++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */
++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */
++
++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC4.CTRLD bit masks and bit positions */
++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC4_EVACT_gp 5 /* Event Action group position. */
++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC4.CTRLE bit masks and bit positions */
++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */
++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */
++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */
++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */
++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */
++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */
++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */
++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */
++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */
++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */
++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */
++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */
++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */
++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */
++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */
++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */
++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC4.CTRLF bit masks and bit positions */
++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */
++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */
++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */
++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */
++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */
++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */
++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC4.INTCTRLA bit masks and bit positions */
++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC4.INTCTRLB bit masks and bit positions */
++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */
++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */
++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */
++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */
++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */
++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */
++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC4.CTRLGCLR bit masks and bit positions */
++#define TC4_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC4_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC4_CMD_gm 0x0C /* Command group mask. */
++#define TC4_CMD_gp 2 /* Command group position. */
++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC4_CMD0_bp 2 /* Command bit 0 position. */
++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC4_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC4_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC4_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC4.CTRLGSET bit masks and bit positions */
++/* TC4_STOP Predefined. */
++/* TC4_STOP Predefined. */
++
++/* TC4_CMD Predefined. */
++/* TC4_CMD Predefined. */
++
++/* TC4_LUPD Predefined. */
++/* TC4_LUPD Predefined. */
++
++/* TC4_DIR Predefined. */
++/* TC4_DIR Predefined. */
++
++/* TC4.CTRLHCLR bit masks and bit positions */
++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC4.CTRLHSET bit masks and bit positions */
++/* TC4_CCDBV Predefined. */
++/* TC4_CCDBV Predefined. */
++
++/* TC4_CCCBV Predefined. */
++/* TC4_CCCBV Predefined. */
++
++/* TC4_CCBBV Predefined. */
++/* TC4_CCBBV Predefined. */
++
++/* TC4_CCABV Predefined. */
++/* TC4_CCABV Predefined. */
++
++/* TC4_PERBV Predefined. */
++/* TC4_PERBV Predefined. */
++
++/* TC4_LCCDBV Predefined. */
++/* TC4_LCCDBV Predefined. */
++
++/* TC4_LCCCBV Predefined. */
++/* TC4_LCCCBV Predefined. */
++
++/* TC4_LCCBBV Predefined. */
++/* TC4_LCCBBV Predefined. */
++
++/* TC4_LCCABV Predefined. */
++/* TC4_LCCABV Predefined. */
++
++/* TC4_LPERBV Predefined. */
++/* TC4_LPERBV Predefined. */
++
++/* TC4.INTFLAGS bit masks and bit positions */
++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* TC5.CTRLA bit masks and bit positions */
++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */
++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */
++
++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */
++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */
++
++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */
++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */
++
++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */
++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */
++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */
++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */
++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */
++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */
++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */
++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */
++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */
++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */
++
++/* TC5.CTRLB bit masks and bit positions */
++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */
++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */
++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */
++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */
++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */
++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */
++
++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */
++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */
++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */
++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */
++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */
++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */
++
++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */
++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */
++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */
++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */
++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */
++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */
++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */
++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */
++
++/* TC5.CTRLC bit masks and bit positions */
++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */
++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */
++
++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */
++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */
++
++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */
++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */
++
++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */
++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */
++
++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */
++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */
++
++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */
++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */
++
++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */
++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */
++
++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */
++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */
++
++/* TC5.CTRLD bit masks and bit positions */
++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */
++#define TC5_EVACT_gp 5 /* Event Action group position. */
++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */
++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */
++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */
++
++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */
++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */
++
++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */
++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */
++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
++
++/* TC5.CTRLE bit masks and bit positions */
++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */
++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */
++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */
++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */
++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */
++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */
++
++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */
++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */
++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */
++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */
++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */
++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */
++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */
++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */
++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */
++
++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */
++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */
++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */
++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */
++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */
++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */
++
++/* TC5.CTRLF bit masks and bit positions */
++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */
++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */
++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */
++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */
++
++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */
++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */
++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */
++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */
++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */
++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */
++
++/* TC5.INTCTRLA bit masks and bit positions */
++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */
++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */
++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */
++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */
++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */
++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */
++
++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */
++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */
++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */
++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */
++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */
++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */
++
++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */
++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */
++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */
++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */
++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */
++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */
++
++/* TC5.INTCTRLB bit masks and bit positions */
++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */
++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */
++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */
++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */
++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */
++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */
++
++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */
++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */
++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */
++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */
++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */
++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */
++
++/* TC5.CTRLGCLR bit masks and bit positions */
++#define TC5_STOP_bm 0x10 /* Timer/Counter Stop bit mask. */
++#define TC5_STOP_bp 4 /* Timer/Counter Stop bit position. */
++
++#define TC5_CMD_gm 0x0C /* Command group mask. */
++#define TC5_CMD_gp 2 /* Command group position. */
++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */
++#define TC5_CMD0_bp 2 /* Command bit 0 position. */
++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */
++#define TC5_CMD1_bp 3 /* Command bit 1 position. */
++
++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */
++#define TC5_LUPD_bp 1 /* Lock Update bit position. */
++
++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */
++#define TC5_DIR_bp 0 /* Counter Direction bit position. */
++
++/* TC5.CTRLGSET bit masks and bit positions */
++/* TC5_STOP Predefined. */
++/* TC5_STOP Predefined. */
++
++/* TC5_CMD Predefined. */
++/* TC5_CMD Predefined. */
++
++/* TC5_LUPD Predefined. */
++/* TC5_LUPD Predefined. */
++
++/* TC5_DIR Predefined. */
++/* TC5_DIR Predefined. */
++
++/* TC5.CTRLHCLR bit masks and bit positions */
++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */
++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */
++
++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */
++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */
++
++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */
++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */
++
++/* TC5.CTRLHSET bit masks and bit positions */
++/* TC5_CCBBV Predefined. */
++/* TC5_CCBBV Predefined. */
++
++/* TC5_CCABV Predefined. */
++/* TC5_CCABV Predefined. */
++
++/* TC5_PERBV Predefined. */
++/* TC5_PERBV Predefined. */
++
++/* TC5_LCCBBV Predefined. */
++/* TC5_LCCBBV Predefined. */
++
++/* TC5_LCCABV Predefined. */
++/* TC5_LCCABV Predefined. */
++
++/* TC5_LPERBV Predefined. */
++/* TC5_LPERBV Predefined. */
++
++/* TC5.INTFLAGS bit masks and bit positions */
++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */
++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */
++
++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
++
++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */
++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */
++
++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */
++
++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */
++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */
++
++/* FAULT - Fault Extension */
++/* FAULT.CTRLA bit masks and bit positions */
++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */
++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */
++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */
++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */
++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */
++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */
++
++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */
++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */
++
++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */
++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */
++
++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */
++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */
++
++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */
++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */
++
++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */
++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */
++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */
++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */
++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */
++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */
++
++/* FAULT.CTRLB bit masks and bit positions */
++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */
++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */
++
++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */
++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */
++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */
++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */
++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */
++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */
++
++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */
++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */
++
++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */
++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */
++
++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */
++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */
++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */
++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */
++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */
++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */
++
++/* FAULT.CTRLC bit masks and bit positions */
++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */
++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */
++
++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */
++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */
++
++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */
++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */
++
++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */
++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */
++
++/* FAULT.CTRLD bit masks and bit positions */
++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */
++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */
++
++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */
++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */
++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */
++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */
++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */
++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */
++
++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */
++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */
++
++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */
++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */
++
++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */
++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */
++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */
++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */
++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */
++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */
++
++/* FAULT.CTRLE bit masks and bit positions */
++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */
++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */
++
++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */
++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */
++
++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */
++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */
++
++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */
++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */
++
++/* FAULT.STATUS bit masks and bit positions */
++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */
++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */
++
++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */
++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */
++
++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */
++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */
++
++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */
++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */
++
++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGCLR bit masks and bit positions */
++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */
++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */
++
++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */
++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */
++
++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */
++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */
++
++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */
++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */
++
++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */
++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */
++
++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */
++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */
++
++/* FAULT.CTRLGSET bit masks and bit positions */
++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */
++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */
++
++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */
++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */
++
++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */
++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */
++
++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */
++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */
++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */
++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */
++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */
++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */
++
++/* WEX - Waveform Extension */
++/* WEX.CTRL bit masks and bit positions */
++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */
++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */
++
++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */
++#define WEX_OTMX_gp 4 /* Output Matrix group position. */
++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */
++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */
++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */
++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */
++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */
++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */
++
++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */
++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */
++
++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */
++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */
++
++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */
++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */
++
++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */
++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */
++
++/* WEX.STATUSCLR bit masks and bit positions */
++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */
++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */
++
++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */
++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */
++
++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */
++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */
++
++/* WEX.STATUSSET bit masks and bit positions */
++/* WEX_SWAPBUF Predefined. */
++/* WEX_SWAPBUF Predefined. */
++
++/* WEX_PGVBUFV Predefined. */
++/* WEX_PGVBUFV Predefined. */
++
++/* WEX_PGOBUFV Predefined. */
++/* WEX_PGOBUFV Predefined. */
++
++/* WEX.SWAP bit masks and bit positions */
++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* WEX.SWAPBUF bit masks and bit positions */
++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */
++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */
++
++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */
++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */
++
++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */
++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */
++
++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */
++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */
++
++/* HIRES - High-Resolution Extension */
++/* HIRES.CTRLA bit masks and bit positions */
++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */
++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */
++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */
++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */
++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */
++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */
++
++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */
++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */
++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */
++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */
++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */
++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */
++
++/* USART - Universal Asynchronous Receiver-Transmitter */
++/* USART.STATUS bit masks and bit positions */
++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
++
++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
++
++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
++
++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
++#define USART_FERR_bp 4 /* Frame Error bit position. */
++
++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
++
++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
++#define USART_PERR_bp 2 /* Parity Error bit position. */
++
++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */
++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */
++
++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
++
++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */
++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */
++
++/* USART.CTRLA bit masks and bit positions */
++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */
++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */
++
++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */
++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */
++
++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.CTRLB bit masks and bit positions */
++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */
++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */
++
++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */
++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */
++
++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
++
++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
++
++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
++
++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
++
++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
++
++/* USART.CTRLC bit masks and bit positions */
++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
++#define USART_CMODE_gp 6 /* Communication Mode group position. */
++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
++
++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
++#define USART_PMODE_gp 4 /* Parity Mode group position. */
++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
++
++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
++
++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
++#define USART_CHSIZE_gp 0 /* Character Size group position. */
++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
++
++/* USART.CTRLD bit masks and bit positions */
++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */
++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */
++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */
++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */
++
++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */
++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */
++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */
++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */
++
++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */
++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
++
++/* USART.BAUDCTRLA bit masks and bit positions */
++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
++
++/* USART.BAUDCTRLB bit masks and bit positions */
++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
++
++/* USART_BSEL Predefined. */
++/* USART_BSEL Predefined. */
++
++/* SPI - Serial Peripheral Interface */
++/* SPI.CTRL bit masks and bit positions */
++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
++
++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */
++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */
++
++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
++
++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
++
++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
++#define SPI_MODE_gp 2 /* SPI Mode group position. */
++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
++
++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
++
++/* SPI.INTCTRL bit masks and bit positions */
++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */
++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */
++
++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
++
++/* SPI.STATUS bit masks and bit positions */
++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */
++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */
++
++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */
++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */
++
++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */
++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */
++
++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */
++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */
++
++/* SPI.CTRLB bit masks and bit positions */
++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */
++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */
++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */
++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */
++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */
++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */
++
++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */
++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */
++
++/* IRCOM - IR Communication Module */
++/* IRCOM.CTRL bit masks and bit positions */
++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
++
++/* FUSE - Fuses and Lockbits */
++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
++
++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
++
++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
++
++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
++
++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
++
++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
++
++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
++
++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
++
++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
++
++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
++
++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
++
++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
++
++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */
++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */
++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */
++
++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */
++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */
++
++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */
++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */
++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */
++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */
++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */
++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */
++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */
++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */
++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */
++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */
++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */
++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */
++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */
++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */
++
++
++
++// Generic Port Pins
++
++#define PIN0_bm 0x01
++#define PIN0_bp 0
++#define PIN1_bm 0x02
++#define PIN1_bp 1
++#define PIN2_bm 0x04
++#define PIN2_bp 2
++#define PIN3_bm 0x08
++#define PIN3_bp 3
++#define PIN4_bm 0x10
++#define PIN4_bp 4
++#define PIN5_bm 0x20
++#define PIN5_bp 5
++#define PIN6_bm 0x40
++#define PIN6_bp 6
++#define PIN7_bm 0x80
++#define PIN7_bp 7
++
++/* ========== Interrupt Vector Definitions ========== */
++/* Vector 0 is the reset vector */
++
++/* OSC interrupt vectors */
++#define OSC_OSCF_vect_num 1
++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */
++
++/* PORTR interrupt vectors */
++#define PORTR_INT_vect_num 2
++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */
++
++/* EDMA interrupt vectors */
++#define EDMA_CH0_vect_num 3
++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */
++#define EDMA_CH1_vect_num 4
++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */
++#define EDMA_CH2_vect_num 5
++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */
++#define EDMA_CH3_vect_num 6
++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */
++
++/* RTC interrupt vectors */
++#define RTC_OVF_vect_num 7
++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */
++#define RTC_COMP_vect_num 8
++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */
++
++/* PORTC interrupt vectors */
++#define PORTC_INT_vect_num 9
++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */
++
++/* TWIC interrupt vectors */
++#define TWIC_TWIS_vect_num 10
++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */
++#define TWIC_TWIM_vect_num 11
++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */
++
++/* TCC4 interrupt vectors */
++#define TCC4_OVF_vect_num 12
++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */
++#define TCC4_ERR_vect_num 13
++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */
++#define TCC4_CCA_vect_num 14
++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */
++#define TCC4_CCB_vect_num 15
++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */
++#define TCC4_CCC_vect_num 16
++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */
++#define TCC4_CCD_vect_num 17
++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */
++
++/* TCC5 interrupt vectors */
++#define TCC5_OVF_vect_num 18
++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */
++#define TCC5_ERR_vect_num 19
++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */
++#define TCC5_CCA_vect_num 20
++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */
++#define TCC5_CCB_vect_num 21
++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */
++
++/* SPIC interrupt vectors */
++#define SPIC_INT_vect_num 22
++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */
++
++/* USARTC0 interrupt vectors */
++#define USARTC0_RXC_vect_num 23
++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */
++#define USARTC0_DRE_vect_num 24
++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */
++#define USARTC0_TXC_vect_num 25
++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */
++
++/* NVM interrupt vectors */
++#define NVM_EE_vect_num 26
++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */
++#define NVM_SPM_vect_num 27
++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */
++
++/* XCL interrupt vectors */
++#define XCL_UNF_vect_num 28
++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */
++#define XCL_CC_vect_num 29
++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */
++
++/* PORTA interrupt vectors */
++#define PORTA_INT_vect_num 30
++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */
++
++/* ACA interrupt vectors */
++#define ACA_AC0_vect_num 31
++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */
++#define ACA_AC1_vect_num 32
++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */
++#define ACA_ACW_vect_num 33
++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */
++
++/* ADCA interrupt vectors */
++#define ADCA_CH0_vect_num 34
++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */
++
++/* PORTD interrupt vectors */
++#define PORTD_INT_vect_num 35
++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */
++
++/* TCD5 interrupt vectors */
++#define TCD5_OVF_vect_num 36
++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */
++#define TCD5_ERR_vect_num 37
++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */
++#define TCD5_CCA_vect_num 38
++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */
++#define TCD5_CCB_vect_num 39
++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */
++
++/* USARTD0 interrupt vectors */
++#define USARTD0_RXC_vect_num 40
++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */
++#define USARTD0_DRE_vect_num 41
++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */
++#define USARTD0_TXC_vect_num 42
++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */
++
++#define _VECTOR_SIZE 4 /* Size of individual vector. */
++#define _VECTORS_SIZE (43 * _VECTOR_SIZE)
++
++
++/* ========== Constants ========== */
++
++#define PROGMEM_START (0x0000)
++#define PROGMEM_SIZE (10240)
++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
++
++#define APP_SECTION_START (0x0000)
++#define APP_SECTION_SIZE (8192)
++#define APP_SECTION_PAGE_SIZE (128)
++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
++
++#define APPTABLE_SECTION_START (0x1800)
++#define APPTABLE_SECTION_SIZE (2048)
++#define APPTABLE_SECTION_PAGE_SIZE (128)
++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
++
++#define BOOT_SECTION_START (0x2000)
++#define BOOT_SECTION_SIZE (2048)
++#define BOOT_SECTION_PAGE_SIZE (128)
++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
++
++#define DATAMEM_START (0x0000)
++#define DATAMEM_SIZE (9216)
++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
++
++#define IO_START (0x0000)
++#define IO_SIZE (4096)
++#define IO_PAGE_SIZE (0)
++#define IO_END (IO_START + IO_SIZE - 1)
++
++#define MAPPED_EEPROM_START (0x1000)
++#define MAPPED_EEPROM_SIZE (512)
++#define MAPPED_EEPROM_PAGE_SIZE (0)
++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
++
++#define INTERNAL_SRAM_START (0x2000)
++#define INTERNAL_SRAM_SIZE (1024)
++#define INTERNAL_SRAM_PAGE_SIZE (0)
++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
++
++#define EEPROM_START (0x0000)
++#define EEPROM_SIZE (512)
++#define EEPROM_PAGE_SIZE (32)
++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
++
++#define SIGNATURES_START (0x0000)
++#define SIGNATURES_SIZE (3)
++#define SIGNATURES_PAGE_SIZE (0)
++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
++
++#define FUSES_START (0x0000)
++#define FUSES_SIZE (6)
++#define FUSES_PAGE_SIZE (0)
++#define FUSES_END (FUSES_START + FUSES_SIZE - 1)
++
++#define LOCKBITS_START (0x0000)
++#define LOCKBITS_SIZE (1)
++#define LOCKBITS_PAGE_SIZE (0)
++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1)
++
++#define USER_SIGNATURES_START (0x0000)
++#define USER_SIGNATURES_SIZE (128)
++#define USER_SIGNATURES_PAGE_SIZE (128)
++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
++
++#define PROD_SIGNATURES_START (0x0000)
++#define PROD_SIGNATURES_SIZE (52)
++#define PROD_SIGNATURES_PAGE_SIZE (128)
++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
++
++#define FLASHSTART PROGMEM_START
++#define FLASHEND PROGMEM_END
++#define SPM_PAGESIZE 128
++#define RAMSTART INTERNAL_SRAM_START
++#define RAMSIZE INTERNAL_SRAM_SIZE
++#define RAMEND INTERNAL_SRAM_END
++#define E2END EEPROM_END
++#define E2PAGESIZE EEPROM_PAGE_SIZE
++
++
++/* ========== Fuses ========== */
++#define FUSE_MEMORY_SIZE 7
++
++/* Fuse Byte 0 Reserved */
++
++/* Fuse Byte 1 */
++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
++#define FUSE1_DEFAULT (0xFF)
++
++/* Fuse Byte 2 */
++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
++#define FUSE2_DEFAULT (0xFF)
++
++/* Fuse Byte 3 Reserved */
++
++/* Fuse Byte 4 */
++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
++#define FUSE4_DEFAULT (0xFF)
++
++/* Fuse Byte 5 */
++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
++#define FUSE5_DEFAULT (0xFF)
++
++/* Fuse Byte 6 */
++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */
++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */
++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */
++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */
++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */
++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */
++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */
++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */
++#define FUSE6_DEFAULT (0xFF)
++
++/* ========== Lock Bits ========== */
++#define __LOCK_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
++#define __BOOT_LOCK_APPLICATION_BITS_EXIST
++#define __BOOT_LOCK_BOOT_BITS_EXIST
++
++/* ========== Signature ========== */
++#define SIGNATURE_0 0x1E
++#define SIGNATURE_1 0x93
++#define SIGNATURE_2 0x41
++
++
++#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */
++
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