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- added dirty llvm11-support patch, now at least builds with llvm 11
[packages/beignet.git] / beignet-cometlake.patch
CommitLineData
7d3d7cb5
JB		 1Description: Add Comet Lake/Amber Lake/more Coffee Lake support
2
3Minimally tested, I suggest using intel-opencl-icd instead if possible
4
5Author: Ridley Combs
6Bug-Ubuntu: https://launchpad.net/bugs/1905340
7Origin: https://github.com/intel/beignet/pull/20/files
8
9--- a/backend/src/backend/gen_program.cpp
10+++ b/backend/src/backend/gen_program.cpp
11@@ -211,6 +211,10 @@ namespace gbe {
12 ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
13 } else if (IS_COFFEELAKE(deviceID)) {
14 ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
15+ } else if (IS_COMETLAKE(deviceID)) {
16+ ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
17+ } else if (IS_AMBERLAKE(deviceID)) {
18+ ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
19 } else if (IS_GEMINILAKE(deviceID)) {
20 ctx = GBE_NEW(GlkContext, unit, name, deviceID, relaxMath);
21 }
22@@ -331,6 +335,8 @@ namespace gbe {
23 (IS_BROXTON(deviceID) && MATCH_BXT_HEADER(binary)) || \
24 (IS_KABYLAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
25 (IS_COFFEELAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
26+ (IS_COMETLAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
27+ (IS_AMBERLAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \
28 (IS_GEMINILAKE(deviceID) && MATCH_GLK_HEADER(binary)) \
29 )
30
31@@ -441,6 +447,10 @@ namespace gbe {
32 FILL_KBL_HEADER(*binary);
33 }else if(IS_COFFEELAKE(prog->deviceID)){
34 FILL_KBL_HEADER(*binary);
35+ }else if(IS_COMETLAKE(prog->deviceID)){
36+ FILL_KBL_HEADER(*binary);
37+ }else if(IS_AMBERLAKE(prog->deviceID)){
38+ FILL_KBL_HEADER(*binary);
39 }else if(IS_GEMINILAKE(prog->deviceID)){
40 FILL_GLK_HEADER(*binary);
41 }else {
42--- a/src/cl_device_data.h
43+++ b/src/cl_device_data.h
44@@ -376,6 +376,8 @@
45 #define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
46 #define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
47
48+#define PCI_CHIP_COFFEELAKE_H_GT1_1 0x3E9C
49+
50 #define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
51 #define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
52
53@@ -383,6 +385,7 @@
54 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
55 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
56 #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
57+#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E98
58
59 #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E94
60 #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E9B
61@@ -401,6 +404,7 @@
62 (devid == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
63 devid == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
64 devid == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
65+ devid == PCI_CHIP_COFFEELAKE_H_GT1_1 || \
66 devid == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
67 devid == PCI_CHIP_COFFEELAKE_U_GT1_2)
68
69@@ -409,6 +413,7 @@
70 devid == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
71 devid == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
72 devid == PCI_CHIP_COFFEELAKE_S_GT2_4 || \
73+ devid == PCI_CHIP_COFFEELAKE_S_GT2_5 || \
74 devid == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
75 devid == PCI_CHIP_COFFEELAKE_H_GT2_2 || \
76 devid == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
77@@ -424,7 +429,65 @@
78
79 #define IS_COFFEELAKE(devid) (IS_CFL_GT1(devid) || IS_CFL_GT2(devid) || IS_CFL_GT3(devid))
80
81-#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid))
82+#define PCI_CHIP_COMETLAKE_S_GT1_1 0x9BA5
83+#define PCI_CHIP_COMETLAKE_S_GT1_2 0x9BA8
84+
85+#define PCI_CHIP_COMETLAKE_H_GT1_1 0x9BA4
86+#define PCI_CHIP_COMETLAKE_H_GT1_2 0x9BA2
87+
88+#define PCI_CHIP_COMETLAKE_U_GT1_1 0x9B21
89+#define PCI_CHIP_COMETLAKE_U_GT1_2 0x9BAA
90+#define PCI_CHIP_COMETLAKE_U_GT1_3 0x9BAC
91+
92+#define PCI_CHIP_COMETLAKE_S_GT2_1 0x9BC5
93+#define PCI_CHIP_COMETLAKE_S_GT2_2 0x9BC8
94+
95+#define PCI_CHIP_COMETLAKE_H_GT2_1 0x9BC4
96+#define PCI_CHIP_COMETLAKE_H_GT2_2 0x9BC2
97+
98+#define PCI_CHIP_COMETLAKE_W_GT2_1 0x9BC6
99+#define PCI_CHIP_COMETLAKE_W_GT2_2 0x9BE6
100+#define PCI_CHIP_COMETLAKE_W_GT2_3 0x9BF6
101+
102+#define PCI_CHIP_COMETLAKE_U_GT2_1 0x9B41
103+#define PCI_CHIP_COMETLAKE_U_GT2_2 0x9BCA
104+#define PCI_CHIP_COMETLAKE_U_GT2_3 0x9BCC
105+
106+#define IS_CML_GT1(devid) \
107+ (devid == PCI_CHIP_COMETLAKE_S_GT1_1 || \
108+ devid == PCI_CHIP_COMETLAKE_S_GT1_2 || \
109+ devid == PCI_CHIP_COMETLAKE_H_GT1_1 || \
110+ devid == PCI_CHIP_COMETLAKE_H_GT1_2 || \
111+ devid == PCI_CHIP_COMETLAKE_U_GT1_1 || \
112+ devid == PCI_CHIP_COMETLAKE_U_GT1_2 || \
113+ devid == PCI_CHIP_COMETLAKE_U_GT1_3)
114+
115+#define IS_CML_GT2(devid) \
116+ (devid == PCI_CHIP_COMETLAKE_S_GT2_1 || \
117+ devid == PCI_CHIP_COMETLAKE_S_GT2_2 || \
118+ devid == PCI_CHIP_COMETLAKE_H_GT2_1 || \
119+ devid == PCI_CHIP_COMETLAKE_H_GT2_2 || \
120+ devid == PCI_CHIP_COMETLAKE_W_GT2_1 || \
121+ devid == PCI_CHIP_COMETLAKE_W_GT2_2 || \
122+ devid == PCI_CHIP_COMETLAKE_W_GT2_3 || \
123+ devid == PCI_CHIP_COMETLAKE_U_GT2_1 || \
124+ devid == PCI_CHIP_COMETLAKE_U_GT2_2 || \
125+ devid == PCI_CHIP_COMETLAKE_U_GT2_3)
126+
127+#define IS_COMETLAKE(devid) (IS_CML_GT1(devid) || IS_CML_GT2(devid))
128+
129+#define PCI_CHIP_AMBERLAKE_Y_GT2_1 0x591C
130+#define PCI_CHIP_AMBERLAKE_Y_GT2_2 0x87C0
131+#define PCI_CHIP_AMBERLAKE_Y_GT2_3 0x87CA
132+
133+#define IS_AML_GT2(devid) \
134+ (devid == PCI_CHIP_AMBERLAKE_Y_GT2_1 || \
135+ devid == PCI_CHIP_AMBERLAKE_Y_GT2_2 || \
136+ devid == PCI_CHIP_AMBERLAKE_Y_GT2_3)
137+
138+#define IS_AMBERLAKE(devid) (IS_AML_GT2(devid))
139+
140+#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid) || IS_COMETLAKE(devid) || IS_AMBERLAKE(devid))
141
142 #define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120)
143
144--- a/src/cl_device_id.c
145+++ b/src/cl_device_id.c
146@@ -304,6 +304,36 @@ static struct _cl_device_id intel_cfl_gt3_device = {
147 #include "cl_gen9_device.h"
148 };
149
150+static struct _cl_device_id intel_cml_gt1_device = {
151+ .max_compute_unit = 12,
152+ .max_thread_per_unit = 7,
153+ .sub_slice_count = 2,
154+ .max_work_item_sizes = {512, 512, 512},
155+ .max_work_group_size = 256,
156+ .max_clock_frequency = 1000,
157+#include "cl_gen9_device.h"
158+};
159+
160+static struct _cl_device_id intel_cml_gt2_device = {
161+ .max_compute_unit = 24,
162+ .max_thread_per_unit = 7,
163+ .sub_slice_count = 3,
164+ .max_work_item_sizes = {512, 512, 512},
165+ .max_work_group_size = 256,
166+ .max_clock_frequency = 1000,
167+#include "cl_gen9_device.h"
168+};
169+
170+static struct _cl_device_id intel_aml_gt2_device = {
171+ .max_compute_unit = 24,
172+ .max_thread_per_unit = 7,
173+ .sub_slice_count = 3,
174+ .max_work_item_sizes = {512, 512, 512},
175+ .max_work_group_size = 256,
176+ .max_clock_frequency = 1000,
177+#include "cl_gen9_device.h"
178+};
179+
180 LOCAL cl_device_id
181 cl_get_gt_device(cl_device_type device_type)
182 {
183@@ -819,6 +849,8 @@ cl_get_gt_device(cl_device_type device_type)
184 case PCI_CHIP_COFFEELAKE_S_GT1_2:
185 case PCI_CHIP_COFFEELAKE_S_GT1_3:
186 DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT1");
187+ case PCI_CHIP_COFFEELAKE_H_GT1_1:
188+ DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Halo GT1");
189 case PCI_CHIP_COFFEELAKE_U_GT1_1:
190 case PCI_CHIP_COFFEELAKE_U_GT1_2:
191 DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT1");
192@@ -837,6 +869,7 @@ cl_get_gt_device(cl_device_type device_type)
193 case PCI_CHIP_COFFEELAKE_S_GT2_2:
194 case PCI_CHIP_COFFEELAKE_S_GT2_3:
195 case PCI_CHIP_COFFEELAKE_S_GT2_4:
196+ case PCI_CHIP_COFFEELAKE_S_GT2_5:
197 DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT2");
198 case PCI_CHIP_COFFEELAKE_H_GT2_1:
199 case PCI_CHIP_COFFEELAKE_H_GT2_2:
200@@ -873,6 +906,67 @@ cl_get_gt_device(cl_device_type device_type)
201 cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
202 break;
203
204+ case PCI_CHIP_COMETLAKE_S_GT1_1:
205+ case PCI_CHIP_COMETLAKE_S_GT1_2:
206+ DECL_INFO_STRING(cml_gt1_break, intel_cml_gt1_device, name, "Intel(R) UHD Graphics Comet Lake Desktop GT1");
207+ case PCI_CHIP_COMETLAKE_H_GT1_1:
208+ case PCI_CHIP_COMETLAKE_H_GT1_2:
209+ DECL_INFO_STRING(cml_gt1_break, intel_cml_gt1_device, name, "Intel(R) UHD Graphics Comet Lake Halo GT1");
210+ case PCI_CHIP_COMETLAKE_U_GT1_1:
211+ case PCI_CHIP_COMETLAKE_U_GT1_2:
212+ case PCI_CHIP_COMETLAKE_U_GT1_3:
213+ DECL_INFO_STRING(cml_gt1_break, intel_cml_gt1_device, name, "Intel(R) UHD Graphics Comet Lake Mobile GT1");
214+cml_gt1_break:
215+ intel_cml_gt1_device.device_id = device_id;
216+ intel_cml_gt1_device.platform = cl_get_platform_default();
217+ ret = &intel_cml_gt1_device;
218+ cl_intel_platform_get_default_extension(ret);
219+#ifdef ENABLE_FP64
220+ cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
221+#endif
222+ cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
223+ break;
224+
225+ case PCI_CHIP_COMETLAKE_S_GT2_1:
226+ case PCI_CHIP_COMETLAKE_S_GT2_2:
227+ DECL_INFO_STRING(cml_gt2_break, intel_cml_gt2_device, name, "Intel(R) UHD Graphics Comet Lake Desktop GT2");
228+ case PCI_CHIP_COMETLAKE_H_GT2_1:
229+ case PCI_CHIP_COMETLAKE_H_GT2_2:
230+ DECL_INFO_STRING(cml_gt2_break, intel_cml_gt2_device, name, "Intel(R) UHD Graphics Comet Lake Halo GT2");
231+ case PCI_CHIP_COMETLAKE_W_GT2_1:
232+ case PCI_CHIP_COMETLAKE_W_GT2_2:
233+ case PCI_CHIP_COMETLAKE_W_GT2_3:
234+ DECL_INFO_STRING(cml_gt2_break, intel_cml_gt2_device, name, "Intel(R) UHD Graphics Comet Lake Workstation GT2");
235+ case PCI_CHIP_COMETLAKE_U_GT2_1:
236+ case PCI_CHIP_COMETLAKE_U_GT2_2:
237+ case PCI_CHIP_COMETLAKE_U_GT2_3:
238+ DECL_INFO_STRING(cml_gt2_break, intel_cml_gt2_device, name, "Intel(R) UHD Graphics Comet Lake Mobile GT2");
239+cml_gt2_break:
240+ intel_cml_gt2_device.device_id = device_id;
241+ intel_cml_gt2_device.platform = cl_get_platform_default();
242+ ret = &intel_cml_gt2_device;
243+ cl_intel_platform_get_default_extension(ret);
244+#ifdef ENABLE_FP64
245+ cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
246+#endif
247+ cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
248+ break;
249+
250+ case PCI_CHIP_AMBERLAKE_Y_GT2_1:
251+ case PCI_CHIP_AMBERLAKE_Y_GT2_2:
252+ case PCI_CHIP_AMBERLAKE_Y_GT2_3:
253+ DECL_INFO_STRING(aml_gt2_break, intel_aml_gt2_device, name, "Intel(R) UHD Graphics Amber Lake ULX GT2");
254+aml_gt2_break:
255+ intel_aml_gt2_device.device_id = device_id;
256+ intel_aml_gt2_device.platform = cl_get_platform_default();
257+ ret = &intel_aml_gt2_device;
258+ cl_intel_platform_get_default_extension(ret);
259+#ifdef ENABLE_FP64
260+ cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
261+#endif
262+ cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
263+ break;
264+
265 case PCI_CHIP_SANDYBRIDGE_BRIDGE:
266 case PCI_CHIP_SANDYBRIDGE_GT1:
267 case PCI_CHIP_SANDYBRIDGE_GT2:
268@@ -1083,7 +1177,10 @@ LOCAL cl_bool is_gen_device(cl_device_id device) {
269 device == &intel_glk12eu_device ||
270 device == &intel_cfl_gt1_device ||
271 device == &intel_cfl_gt2_device ||
272- device == &intel_cfl_gt3_device;
273+ device == &intel_cfl_gt3_device ||
274+ device == &intel_cml_gt1_device ||
275+ device == &intel_cml_gt2_device ||
276+ device == &intel_aml_gt2_device;
277 }
278
279 LOCAL cl_int
280@@ -1513,7 +1610,8 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
281 || device == &intel_kbl_gt4_device || device == &intel_kbl_gt15_device
282 || device == &intel_glk18eu_device || device == &intel_glk12eu_device
283 || device == &intel_cfl_gt1_device || device == &intel_cfl_gt1_device
284- || device == &intel_cfl_gt3_device) {
285+ || device == &intel_cfl_gt3_device || device == &intel_cml_gt1_device
286+ || device == &intel_cml_gt2_device || device == &intel_aml_gt2_device) {
287 *ver = 9;
288 } else
289 return CL_INVALID_VALUE;
Open source implementation of the OpenCL specification for Intel GPUs
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