* Hardware access:
*/
--#define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
-+#define DEV_NEED_TIMERIRQ_ORIG 0x000001 /* set the timer irq flag in the irq mask */
-+#define DEV_NEED_TIMERIRQ 0x000000 /* work-around for Wake-On-Lan functionality */
- #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
- #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
- #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
+-#define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
++#define DEV_NEED_TIMERIRQ_ORIG 0x0000001 /* set the timer irq flag in the irq mask */
++#define DEV_NEED_TIMERIRQ 0x0000000 /* work-around for Wake-On-Lan functionality */
+ #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
+ #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
+ #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
@@ -4342,7 +4343,7 @@
np->msi_flags |= 0x0001;
}