1 commit 5bfd73cd31ba197a62f549cdbad1a1270b571027
2 Author: Eric Anholt <eric@anholt.net>
3 Date: Fri Feb 27 19:09:49 2009 -0800
5 Only allocate pixmaps aligned for tiling when requested by DRI2 GetBuffers.
7 This saves massive quantities of memory on pre-965 since the DRI2 tiling
8 enable caused the minimum size of any pixmap to be 1MB.
10 diff --git a/src/i830.h b/src/i830.h
11 index a0ae571..cd9c38a 100644
14 @@ -1090,4 +1090,15 @@ extern const int I830CopyROP[16];
15 #define QUIRK_BROKEN_ACPI_LID 0x00000100
16 extern void i830_fixup_devices(ScrnInfoPtr);
19 + * Hints to CreatePixmap to tell the driver how the pixmap is going to be
22 + * Compare to CREATE_PIXMAP_USAGE_* in the server.
25 + INTEL_CREATE_PIXMAP_TILING_X = 0x10000000,
26 + INTEL_CREATE_PIXMAP_TILING_Y,
30 diff --git a/src/i830_dri.c b/src/i830_dri.c
31 index 540bf5e..96c711e 100644
34 @@ -1561,36 +1561,33 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
35 pPixmap = pDepthPixmap;
38 - uint32_t tiling = I915_TILING_NONE;
39 + unsigned int hint = 0;
41 - pPixmap = (*pScreen->CreatePixmap)(pScreen,
45 switch (attachments[i]) {
47 if (SUPPORTS_YTILING(pI830))
48 - tiling = I915_TILING_Y;
49 + hint = INTEL_CREATE_PIXMAP_TILING_Y;
51 - tiling = I915_TILING_X;
52 + hint = INTEL_CREATE_PIXMAP_TILING_X;
54 case DRI2BufferFakeFrontLeft:
55 case DRI2BufferFakeFrontRight:
56 case DRI2BufferBackLeft:
57 case DRI2BufferBackRight:
58 - tiling = I915_TILING_X;
59 + hint = INTEL_CREATE_PIXMAP_TILING_X;
64 (!IS_I965G(pI830) && !pI830->kernel_exec_fencing))
65 - tiling = I915_TILING_NONE;
68 + pPixmap = (*pScreen->CreatePixmap)(pScreen,
74 - if (tiling != I915_TILING_NONE) {
75 - bo = i830_get_pixmap_bo(pPixmap);
76 - drm_intel_bo_set_tiling(bo, &tiling,
77 - intel_get_pixmap_pitch(pPixmap));
81 if (attachments[i] == DRI2BufferDepth)
82 diff --git a/src/i830_exa.c b/src/i830_exa.c
83 index b9d6c64..0a22486 100644
86 @@ -935,29 +935,38 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
90 + uint32_t tiling = I915_TILING_NONE;
92 stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
93 i830->accel_pixmap_pitch_alignment);
95 - /* Use the I915_FENCE_TILING_X even if it may end up being TILING_Y,
96 - * as it just results in larger alignment. Really, we need to use the
97 - * usage hint to tell what the pixmap's going to be.
99 - stride = i830_get_fence_pitch(i830, stride, I915_TILING_X);
100 - /* Round the object up to the size of the fence it will live in
101 - * if necessary. We could potentially make the kernel allocate
102 - * a larger aperture space and just bind the subset of pages in,
103 - * but this is easier and also keeps us out of trouble (as much)
104 - * with drm_intel_bufmgr_check_aperture().
106 - size = i830_get_fence_size(i830, stride * h);
107 + if (usage == INTEL_CREATE_PIXMAP_TILING_X)
108 + tiling = I915_TILING_X;
109 + else if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
110 + tiling = I915_TILING_Y;
112 + if (tiling == I915_TILING_NONE) {
115 + stride = i830_get_fence_pitch(i830, stride, tiling);
116 + /* Round the object up to the size of the fence it will live in
117 + * if necessary. We could potentially make the kernel allocate
118 + * a larger aperture space and just bind the subset of pages in,
119 + * but this is easier and also keeps us out of trouble (as much)
120 + * with drm_intel_bufmgr_check_aperture().
122 + size = i830_get_fence_size(i830, stride * h);
125 bo = drm_intel_bo_alloc_for_render(i830->bufmgr, "pixmap", size, 0);
127 fbDestroyPixmap (pixmap);
132 + if (tiling != I915_TILING_NONE)
133 + drm_intel_bo_set_tiling(bo, &tiling, stride);
135 screen->ModifyPixmapHeader (pixmap, w, h, 0, 0, stride, NULL);
137 i830_uxa_set_pixmap_bo (pixmap, bo);