1 --- linux/drivers/net/wan/Makefile 2003-03-06 14:56:13.000000000 +0100
2 +++ linux/drivers/net/wan/Makefile 2003-03-30 22:37:04.000000000 +0200
5 obj-$(CONFIG_N2) += n2.o
6 obj-$(CONFIG_C101) += c101.o
7 +obj-$(CONFIG_TAHOE9XX) += tahoe9xx.o
8 obj-$(CONFIG_WANXL) += wanxl.o
9 obj-$(CONFIG_PCI200SYN) += pci200syn.o
11 --- linux/drivers/net/wan/tahoe9xx.c 2003-04-07 14:18:45.000000000 +0200
12 +++ linux/drivers/net/wan/tahoe9xx.c 2003-04-07 13:47:45.000000000 +0200
15 + * Tahoe 9xx synchronous serial card driver for Linux
17 + * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl>
18 + * Copyright (C) 2003 Piotr Kaczmarzyk <piotr@tahoe.pl>
20 + * This program is free software; you can redistribute it and/or modify it
21 + * under the terms of version 2 of the GNU General Public License
22 + * as published by the Free Software Foundation.
24 + * For information see http://hq.pm.waw.pl/hdlc/
26 + * Sources of information:
27 + * Hitachi HD64570 SCA User's Manual
28 + * PLX Technology Inc. PCI9052 Data Book
29 + * Dallas Semiconductor DS21554 Datasheet
32 +#include <linux/module.h>
33 +#include <linux/kernel.h>
34 +#include <linux/slab.h>
35 +#include <linux/sched.h>
36 +#include <linux/types.h>
37 +#include <linux/fcntl.h>
38 +#include <linux/in.h>
39 +#include <linux/string.h>
40 +#include <linux/errno.h>
41 +#include <linux/init.h>
42 +#include <linux/ioport.h>
43 +#include <linux/moduleparam.h>
44 +#include <linux/netdevice.h>
45 +#include <linux/hdlc.h>
46 +#include <linux/pci.h>
47 +#include <asm/delay.h>
52 +static const char* version = "Tahoe 9xx driver version: 1.16t";
53 +static const char* devname = "TAHOE9XX";
55 +#define TAHOE9XX_PLX_SIZE 0x80 /* PLX control window size (128b) */
56 +#define TAHOE9XX_SCA_SIZE 0x100 /* SCA window size (256b) */
57 +#define ALL_PAGES_ALWAYS_MAPPED
58 +#define NEED_DETECT_RAM
59 +#define NEED_SCA_MSCI_INTR
60 +#define MAX_TX_BUFFERS 10
62 +#define CLOCK_BASE 9216000
67 +#define DEFAULT_LICR 0x80
69 +#define PCI_VENDOR_ID_TAHOE 0x8246
70 +#define PCI_DEVICE_ID_TAHOE931 0x0931
71 +#define PCI_DEVICE_ID_TAHOE932 0x0932
72 +#define PCI_DEVICE_ID_TAHOE971 0x0971
73 +#define PCI_DEVICE_ID_TAHOE972 0x0972
76 + * PLX PCI9052 local configuration and shared runtime registers.
77 + * This structure can be used to access 9052 registers (memory mapped).
80 + u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
81 + u32 loc_rom_range; /* 10h : Local ROM Range */
82 + u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
83 + u32 loc_rom_base; /* 24h : Local ROM Base */
84 + u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
85 + u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
86 + u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
87 + u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
88 + u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
95 +typedef struct ds21554_s {
96 + u8 vcr1; /* Counter: Violation Error */
98 + u8 crccr1; /* Counter: CRC4 Error */
100 + u8 ebcr1; /* Counter: E-bit Error (FEBE) */
102 + u8 sr1; /* Status: Status Register 1 */
103 + u8 sr2; /* Status: Status Register 2 */
104 + u8 rir; /* Status: Receive Information */
106 + u8 idr; /* Misc: Device Indentification */
107 + u8 rcr1; /* Control: Receive Control 1 */
108 + u8 rcr2; /* Control: Receive Control 2 */
109 + u8 tcr1; /* Control: Transmit Control 1 */
110 + u8 tcr2; /* Control: Transmit Control 2 */
111 + u8 ccr1; /* Control: Common Control 1 */
113 + u8 imr1; /* Interrupt Mask 1 */
114 + u8 imr2; /* Interrupt Mask 2 */
115 + u8 licr; /* Control: Line interface */
117 + u8 ccr2; /* Control: Common Control 2 */
118 + u8 ccr3; /* Control: Common Control 3 */
119 + u8 tsacr; /* Control: Transmit Sa bit */
120 + u8 ccr6; /* Control: Common Control 6 */
121 + u8 ssr; /* Status: Synchronizer Status */
122 + u8 rnaf; /* Receive non-align frame */
123 + u8 taf; /* Transmit align frame */
124 + u8 tnaf; /* Transmit non-align frame */
125 + u8 tcbr1; /* Transmit channel blocking */
129 + u8 tir1; /* Transmit idle */
133 + u8 tidr; /* Transmit idle definition */
134 + u8 rcbr1; /* Receive channel blocking */
138 + u8 raf; /* Receive align frame */
139 + u8 rs1; /* Receive signalling */
155 + u8 ts1; /* Transmit signaling */
171 + u8 tsiaf; /* Transmit Si Bits Align Frame */
172 + u8 tsinaf; /* Transmit Si Bits Non-align Frame */
173 + u8 tra; /* Transmit Remote Alarm Bits */
174 + u8 tsa4; /* Transmit Sa Bits */
179 + u8 rsiaf; /* Receive Si Bits Align Frame */
180 + u8 rsinaf; /* Receive Si Bits Non-Align Frame */
181 + u8 rra; /* Receive Remote Alarm Bits */
182 + u8 rsa4; /* Receive Sa Bits */
187 + u8 tc1; /* Transmit channel */
219 + u8 rc1; /* Receive channel */
251 + u8 tcc1; /* Transmit channel control */
255 + u8 rcc1; /* Receive channel control */
259 + u8 ccr4; /* Control: Common Control 4 */
260 + u8 tds0m; /* Transmit DS0 Monitor */
261 + u8 ccr5; /* Control: Common Control 5 */
262 + u8 rds0m; /* Receive DS0 Monitor */
265 + u8 hcr; /* HDLC Control */
266 + u8 hsr; /* HDLC Status */
267 + u8 himr; /* HDLC Interrupt Mask */
268 + u8 rhir; /* Receive HDLC Information */
269 + u8 rhfr; /* Receive HDLC FIFO */
270 + u8 ibo; /* Interleave Bus Operation */
271 + u8 thir; /* Transmit HDLC Information */
272 + u8 thfr; /* Transmit HDLC FIFO */
273 + u8 rdc1; /* Receive HDLC DS0 Control 1 */
274 + u8 rdc2; /* Receive HDLC DS0 Control 2 */
275 + u8 tdc1; /* Transmit HDLC DS0 Control 1 */
276 + u8 tdc2; /* Transmit HDLC DS0 Control 2 */
280 +typedef struct port_s {
281 + struct net_device *dev;
282 + struct card_s *card;
283 + spinlock_t lock; /* TX lock */
284 + te1_settings settings;
285 + int rxpart; /* partial frame received, next frame invalid*/
286 + unsigned short encoding;
287 + unsigned short parity;
288 + u16 rxin; /* rx ring buffer 'in' pointer */
289 + u16 txin; /* tx ring buffer 'in' and 'last' pointers */
291 + u8 rxs, txs, tmc; /* SCA registers */
292 + u8 phy_node; /* physical port # - 0 or 1 */
293 + u32 dsphys; /* DS21544 memory base (physical) */
294 + ds21554_t* dsbase; /* DS21544 memory base (virtual) */
295 + u8 g703_on; /* Enable/disable G.703 transceiver */
296 + u8 g703_coding; /* G.703 line coding */
297 + u8 g703_idlecode; /* G.703 idle timeslots contents */
300 +typedef struct card_s {
301 + u8* rambase; /* buffer memory base (virtual) */
302 + u8* scabase; /* SCA memory base (virtual) */
303 + plx9052* plxbase; /* PLX registers memory base (virtual) */
304 + u16 rx_ring_buffers; /* number of buffers in a ring */
305 + u16 tx_ring_buffers;
306 + u16 buff_offset; /* offset of first buffer of first channel */
307 + u8 irq; /* interrupt request level */
308 + u8 no_ports; /* number of ports */
309 + char dev_name[10]; /* device name */
313 +#define sca_in(reg, card) readb(card->scabase + (reg))
314 +#define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
315 +#define sca_inw(reg, card) readw(card->scabase + (reg))
316 +#define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
317 +#define sca_inl(reg, card) readl(card->scabase + (reg))
318 +#define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
320 +#define port_to_card(port) (port->card)
321 +#define log_node(port) (port->phy_node)
322 +#define phy_node(port) (port->phy_node)
323 +#define winbase(card) (card->rambase)
324 +#define get_port(card, port) (&card->ports[port])
325 +#define sca_flush(card) (sca_in(IER0, card));
327 +static inline void new_memcpy_toio(char *dest, char *src, int length)
332 + len = length > 64 ? 64 : length; /* 32 */
333 + memcpy_toio(dest, src, len);
342 +#define memcpy_toio new_memcpy_toio
344 +#include "hd6457x.c"
346 +void init_ds21554(port_t *port);
348 +static void t9xx_set_iface(port_t *port)
350 + card_t *card = port->card;
351 + u8 msci = get_msci(port);
352 + u8 rxs = port->rxs & CLK_BRG_MASK;
353 + u8 txs = port->txs & CLK_BRG_MASK;
355 + if (port->dsbase) {
356 + init_ds21554(port);
359 + rxs |= CLK_LINE_RX; /* RXC input */
360 + txs |= CLK_LINE_TX; /* TXC input */
364 + sca_out(rxs, msci + RXS, card);
365 + sca_out(txs, msci + TXS, card);
366 + sca_set_port(port);
371 +static int t9xx_open(struct net_device *dev)
373 + port_t *port = dev_to_port(dev);
375 + int result = hdlc_open(dev);
380 + t9xx_set_iface(port);
381 + sca_flush(port_to_card(port));
387 +static int t9xx_close(struct net_device *dev)
390 + sca_flush(port_to_card(dev_to_port(dev)));
397 +static int t9xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
399 + const size_t size = sizeof(te1_settings);
400 + te1_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.te1;
401 + port_t *port = dev_to_port(dev);
404 + if (cmd == SIOCDEVPRIVATE) {
405 + sca_dump_rings(dev);
409 + if (cmd != SIOCWANDEV)
410 + return hdlc_ioctl(dev, ifr, cmd);
412 + switch(ifr->ifr_settings.type) {
415 + ifr->ifr_settings.type = IF_IFACE_E1;
417 + ifr->ifr_settings.type = IF_IFACE_V35;
418 + if (ifr->ifr_settings.size < size) {
419 + ifr->ifr_settings.size = size; /* data size wanted */
422 + if (copy_to_user(line, &port->settings, size))
428 + if (!capable(CAP_NET_ADMIN))
431 + if (copy_from_user(&new_line, line, size))
434 + if (new_line.clock_type != CLOCK_EXT)
435 + return -EINVAL; /* No such clock setting */
437 + if (new_line.loopback > 3)
440 + memcpy(&port->settings, &new_line, size); /* Update settings */
441 + t9xx_set_iface(port);
442 + sca_flush(port_to_card(port));
446 + return hdlc_ioctl(dev, ifr, cmd);
452 +static void t9xx_pci_remove_one(struct pci_dev *pdev)
455 + card_t *card = pci_get_drvdata(pdev);
457 + if ((pdev->subsystem_device == PCI_DEVICE_ID_TAHOE932) ||
458 + (pdev->subsystem_device == PCI_DEVICE_ID_TAHOE972))
462 + for(i = 0; i < ports; i++)
463 + if (card->ports[i].card) {
464 + struct net_device *dev = port_to_dev(&card->ports[i]);
465 + unregister_hdlc_device(dev);
469 + iounmap(card->rambase);
471 + iounmap(card->scabase);
473 + iounmap(card->plxbase);
475 + pci_release_regions(pdev);
476 + pci_disable_device(pdev);
477 + pci_set_drvdata(pdev, NULL);
478 + if (card->ports[0].dev)
479 + free_netdev(card->ports[0].dev);
480 + if ((ports == 2) && (card->ports[1].dev))
481 + free_netdev(card->ports[1].dev);
485 +static void ds21554_update_licr(port_t *port)
487 + port->dsbase->licr = DEFAULT_LICR | (port->settings.egl << 4) | (port->g703_on == 0);
490 +static void ds21554_update_registers(port_t *port)
492 + ds21554_t *ds = port->dsbase;
494 + if (port->settings.slot_map == 0xffffffff) {
496 + ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2);
499 + ds->ccr2 = 0x80; //84
500 + ds->tir1 = 0; ds->tir2 = 0; ds->tir3 = 0; ds->tir4 = 0;
501 + ds->tcc1 = 0; ds->tcc2 = 0; ds->tcc3 = 0; ds->tcc4 = 0;
502 + ds->rcc1 = 0; ds->rcc2 = 0; ds->rcc3 = 0; ds->rcc4 = 0;
503 + ds->rcbr1 = 0xff; ds->rcbr2 = 0xff;
504 + ds->rcbr3 = 0xff; ds->rcbr4 = 0xff;
505 + ds->tcbr1 = 0xff; ds->tcbr2 = 0xff;
506 + ds->tcbr3 = 0xff; ds->tcbr4 = 0xff;
513 + ds->ccr6 = 0x03; /* elastic buffers reset */
515 + ds->ccr6 = 0x00; /* elastic buffers reset */
517 + ds->ccr5 = 0x60; /* elastic buffers align */
521 + ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2)
522 + | (port->settings.crc4 << 4) | (port->settings.crc4);
524 + ds->ccr2 = 0x94; /* Automatic alarm generation */
526 + /* Receive channels */
527 + ds->rcbr1 = port->settings.slot_map & 0xff;
528 + ds->rcbr2 = (port->settings.slot_map >> 8) & 0xff;
529 + ds->rcbr3 = (port->settings.slot_map >> 16) & 0xff;
530 + ds->rcbr4 = (port->settings.slot_map >> 24) & 0xff;
532 + /* Transmit channels */
533 + ds->tcbr1 = port->settings.slot_map & 0xff;
534 + ds->tcbr2 = (port->settings.slot_map >> 8) & 0xff;
535 + ds->tcbr3 = (port->settings.slot_map >> 16) & 0xff;
536 + ds->tcbr4 = (port->settings.slot_map >> 24) & 0xff;
538 + /* Transmit idle */
539 + /* (remaining timeslots are filled with idle code) */
540 + ds->tir1 = ~port->settings.slot_map & 0xfe; /* Slot 0 is never idle */
541 + ds->tir2 = (~port->settings.slot_map >> 8) & 0xff;
542 + ds->tir3 = (~port->settings.slot_map >> 16) & 0xff;
543 + ds->tir4 = (~port->settings.slot_map >> 24) & 0xff;
544 + ds->rcr2 = 0x06; /* RSYSCLK = 2048, rx elastic store enabled */
545 + ds->ccr3 = 0x82; /* TSYSCLK = 2048, tx elastic store enabled */
547 + ds->ccr6 = 0x07; /* elastic buffers reset */
549 + ds->ccr6 = 0x04; /* elastic buffers reset */
551 + ds->ccr5 = 0x60; /* elastic buffers align */
557 +void init_ds21554(port_t *port)
559 + ds21554_t *ds = port->dsbase;
563 + ds->ccr5 = 0x80; /* Line Interface Reset */
566 + ds->ccr5 = 0xe0; /* Elastic Buffers Reset */
569 + ds->ccr6 = 0x04; /* TCLK from RCLK */
571 + ds21554_update_licr(port);
573 + /* Setup HDB3, CRC4, CAS/CCS, G.802 */
574 + ds21554_update_registers(port);
576 + ds->ccr2 = 0x94; /* Automatic alarm generation */
581 + ds21554_update_registers(port);
583 + ds->tidr = port->g703_idlecode;
585 +// ds->ccr4 |= 0x40;
589 +static int __devinit t9xx_pci_init_one(struct pci_dev *pdev,
590 + const struct pci_device_id *ent)
593 + u8 rev_id, tahoe97x = 0;
597 + u32 ramphys; /* buffer memory base */
598 + u32 scaphys; /* SCA memory base */
599 + u32 plxphys; /* PLX registers memory base */
602 + static int printed_version;
603 + if (!printed_version++)
604 + printk(KERN_INFO "%s\n", version);
607 + i = pci_enable_device(pdev);
611 + i = pci_request_regions(pdev, "Tahoe9xx");
613 + pci_disable_device(pdev);
617 + card = kmalloc(sizeof(card_t), GFP_KERNEL);
618 + if (card == NULL) {
619 + printk(KERN_ERR "%s: unable to allocate memory\n", card->dev_name);
620 + pci_release_regions(pdev);
621 + pci_disable_device(pdev);
624 + memset(card, 0, sizeof(card_t));
625 + pci_set_drvdata(pdev, card);
626 + card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
627 + card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
628 + if (!card->ports[0].dev || !card->ports[1].dev) {
629 + printk(KERN_ERR "tahoe9xx: unable to allocate memory\n");
630 + t9xx_pci_remove_one(pdev);
634 + sprintf(card->dev_name, "Tahoe");
635 + switch (pdev->subsystem_device) {
636 + case PCI_DEVICE_ID_TAHOE931:
637 + strcat(card->dev_name, "931");
638 + card->no_ports = 1;
640 + case PCI_DEVICE_ID_TAHOE932:
641 + strcat(card->dev_name, "932");
642 + card->no_ports = 2;
644 + case PCI_DEVICE_ID_TAHOE971:
645 + strcat(card->dev_name, "971");
647 + card->no_ports = 1;
649 + case PCI_DEVICE_ID_TAHOE972:
650 + strcat(card->dev_name, "972");
652 + card->no_ports = 2;
655 + strcat(card->dev_name, "9xx");
656 + card->no_ports = 0;
660 + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
661 + if (pci_resource_len(pdev, 0) != TAHOE9XX_PLX_SIZE ||
662 + pci_resource_len(pdev, 2) != TAHOE9XX_SCA_SIZE ||
663 + pci_resource_len(pdev, 3) < 16384) {
664 + printk(KERN_ERR "%s: invalid card EEPROM parameters\n", card->dev_name);
665 + t9xx_pci_remove_one(pdev);
669 + plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
670 + card->plxbase = ioremap(plxphys, TAHOE9XX_PLX_SIZE);
672 + scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
673 + card->scabase = ioremap(scaphys, TAHOE9XX_SCA_SIZE);
675 + ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
676 + card->rambase = ioremap(ramphys, pci_resource_len(pdev,3));
679 + for (i=0; i < card->no_ports; i++) {
680 + card->ports[i].dsphys = pci_resource_start(pdev,4+i) & PCI_BASE_ADDRESS_MEM_MASK;
681 + card->ports[i].dsbase = (ds21554_t *)ioremap(card->ports[i].dsphys, pci_resource_len(pdev,4+i));
684 + for (i=0; i < card->no_ports; i++)
685 + card->ports[i].dsbase = (ds21554_t *)0;
688 + if (card->plxbase == NULL ||
689 + card->scabase == NULL ||
690 + card->rambase == NULL) {
691 + printk(KERN_ERR "tahoe9xx: ioremap() failed\n");
692 + t9xx_pci_remove_one(pdev);
696 + p = &card->plxbase->init_ctrl;
697 + writel(readl(p) | 0x40000000, p);
698 + readl(p); /* Flush the write - do not use sca_flush */
701 + writel(readl(p) & ~0x40000000, p);
702 + readl(p); /* Flush the write - do not use sca_flush */
705 + ramsize = sca_detect_ram(card, card->rambase,
706 + pci_resource_len(pdev,3));
708 + /* number of TX + RX buffers for one port - this is dual port card */
709 + i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
710 + card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
711 + card->rx_ring_buffers = i - card->tx_ring_buffers;
713 + card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
714 + card->rx_ring_buffers);
716 + printk(KERN_INFO "%s: %u KB RAM at 0x%x, IRQ%u, using %u TX +"
717 + " %u RX packets rings\n", card->dev_name, ramsize / 1024,
718 + ramphys, pdev->irq,
719 + card->tx_ring_buffers, card->rx_ring_buffers);
721 + for (i=0; i < card->no_ports; i++) {
722 + /* Make sure DS21554 is there */
723 + card->ports[i].dsbase->idr = 0x00;
724 + card->ports[i].dsbase->tc1 = 0xaa;
725 + card->ports[i].dsbase->rc1 = 0x55;
726 + if (((card->ports[i].dsbase->idr & 0xf0) == 0xa0) && (card->ports[i].dsbase->tc1 == 0xaa) && (card->ports[i].dsbase->rc1 == 0x55)) {
727 + printk(KERN_INFO "%s: DS21554 (port %d) detected at 0x%x\n", card->dev_name, i, card->ports[i].dsphys);
728 + /* Clear registers */
729 + memset(card->ports[i].dsbase, 0, 256);
730 + /* Default settings */
731 + card->ports[i].g703_on = 1;
732 + card->ports[i].settings.egl = 0;
733 + card->ports[i].g703_coding = G703_HDB3;
734 + card->ports[i].g703_idlecode = 0x54;
735 + card->ports[i].settings.crc4 = 1;
737 + card->ports[i].settings.slot_map = 0xffffffff;
738 + init_ds21554(&card->ports[i]);
740 + printk(KERN_INFO "%s: DS21554 (port %d) test failed!\n", card->dev_name, i);
744 + if (card->tx_ring_buffers < 1) {
745 + printk(KERN_ERR "%s: RAM test failed\n", card->dev_name);
746 + t9xx_pci_remove_one(pdev);
750 + /* Enable interrupts on the PCI bridge */
751 + p = &card->plxbase->intr_ctrl_stat;
752 + writew(readw(p) | 0x0040, p);
755 + if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) {
756 + printk(KERN_WARNING "%s: could not allocate IRQ%d.\n", card->dev_name,
758 + t9xx_pci_remove_one(pdev);
761 + card->irq = pdev->irq;
765 + for(i = 0; i < card->no_ports; i++) {
766 + port_t *port = &card->ports[i];
767 + struct net_device *dev = port_to_dev(port);
768 + hdlc_device *hdlc = dev_to_hdlc(dev);
769 + port->phy_node = i;
771 + spin_lock_init(&port->lock);
772 + SET_MODULE_OWNER(dev);
773 + dev->irq = card->irq;
774 + dev->mem_start = ramphys;
775 + dev->mem_end = ramphys + ramsize - 1;
776 + dev->tx_queue_len = 50;
777 + dev->do_ioctl = t9xx_ioctl;
778 + dev->open = t9xx_open;
779 + dev->stop = t9xx_close;
780 + hdlc->attach = sca_attach;
781 + hdlc->xmit = sca_xmit;
782 + port->settings.clock_type = CLOCK_EXT;
784 + if(register_hdlc_device(dev)) {
785 + printk(KERN_ERR "%s: unable to register hdlc "
786 + "device\n", card->dev_name);
788 + t9xx_pci_remove_one(pdev);
791 + sca_init_sync_port(port); /* Set up SCA memory */
793 + printk(KERN_INFO "%s: %s node %d\n",
794 + dev->name, card->dev_name, port->phy_node);
803 +static struct pci_device_id t9xx_pci_tbl[] __devinitdata = {
804 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
805 + PCI_VENDOR_ID_TAHOE, PCI_ANY_ID,
810 +static struct pci_driver t9xx_pci_driver = {
812 + id_table: t9xx_pci_tbl,
813 + probe: t9xx_pci_init_one,
814 + remove: t9xx_pci_remove_one,
817 +static int __init t9xx_init_module(void)
820 + printk(KERN_INFO "%s\n", version);
822 + return pci_module_init(&t9xx_pci_driver);
827 +static void __exit t9xx_cleanup_module(void)
829 + pci_unregister_driver(&t9xx_pci_driver);
832 +MODULE_AUTHOR("Piotr Kaczmarzyk <piotr@tahoe.pl>");
833 +MODULE_DESCRIPTION("Tahoe 9xx serial port driver");
834 +MODULE_LICENSE("GPL v2");
835 +MODULE_DEVICE_TABLE(pci, t9xx_pci_tbl);
836 +module_init(t9xx_init_module);
837 +module_exit(t9xx_cleanup_module);
838 --- linux/drivers/net/wan/Kconfig 2003-03-06 14:56:13.000000000 +0100
839 +++ linux/drivers/net/wan/Kconfig 2003-03-30 22:37:04.000000000 +0200
841 comment "X.25/LAPB support is disabled"
842 depends on WAN && HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
845 + tristate "Tahoe 9xx support"
846 + depends on HDLC && PCI
848 + This driver is for Tahoe 931/932/971/972 cards
849 + If you have such a card, say Y or M here and see
850 + <http://www.tahoe.pl/>
852 + If you want to compile the driver as a module ( = code which can be
853 + inserted in and removed from the running kernel whenever you want),
854 + say M here and read <file:Documentation/modules.txt>. The module
855 + will be called tahoe9xx.o.
857 + If unsure, say N here.
860 tristate "Goramo PCI200SYN support"
861 depends on HDLC && PCI
862 --- linux/include/linux/hdlc/ioctl.h 1970-01-01 01:00:00.000000000 +0100
863 +++ linux/include/linux/hdlc/ioctl.h 2003-07-31 14:46:58.000000000 +0200
865 unsigned int clock_type; /* internal, external, TX-internal etc. */
866 unsigned short loopback;
867 unsigned int slot_map;
868 + unsigned short crc4;
869 + unsigned short egl;
870 } te1_settings; /* T1, E1 */