radeonfb.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
   6  *
   7  *
   8  *      ChangeLog:
   9  *      2000-08-03      initial version 0.0.1
  10  *      2000-09-10      more bug fixes, public release 0.0.5
  11  *      2001-02-19      mode bug fixes, 0.0.7
  12  *      2001-07-05      fixed scrolling issues, engine initialization,
  13  *                      and minor mode tweaking, 0.0.9
  14  *      2001-09-07      Radeon VE support, Nick Kurshev
  15  *                      blanking, pan_display, and cmap fixes, 0.1.0
  16  *      2001-10-10      Radeon 7500 and 8500 support, and experimental
  17  *                      flat panel support, 0.1.1
  18  *      2001-11-17      Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
  19  *      2001-11-18      DFP fixes, Kevin Hendricks, 0.1.3
  20  *      2001-11-29      more cmap, backlight fixes, Benjamin Herrenschmidt
  21  *      2002-01-18      DFP panel detection via BIOS, Michael Clark, 0.1.4
  22  *      2002-06-02      console switching, mode set fixes, accel fixes
  23  *      2002-06-03      MTRR support, Peter Horton, 0.1.5
  24  *      2002-09-21      rv250, r300, m9 initial support,
  25  *                      added mirror option, 0.1.6
  26  *
  27  *      Special thanks to ATI DevRel team for their hardware donations.
  28  *
  29  */
  30
  31
  32 #define RADEON_VERSION  "0.1.6"
  33
  34
  35 #include <linux/config.h>
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/errno.h>
  39 #include <linux/string.h>
  40 #include <linux/mm.h>
  41 #include <linux/tty.h>
  42 #include <linux/slab.h>
  43 #include <linux/delay.h>
  44 #include <linux/fb.h>
  45 #include <linux/ioport.h>
  46 #include <linux/init.h>
  47 #include <linux/pci.h>
  48 #include <linux/vmalloc.h>
  49
  50 #include <asm/io.h>
  51 #include <asm/uaccess.h>
  52 #if defined(__powerpc__)
  53 #include <asm/prom.h>
  54 #include <asm/pci-bridge.h>
  55 #include "macmodes.h"
  56
  57 #ifdef CONFIG_NVRAM
  58 #include <linux/nvram.h>
  59 #endif
  60
  61 #ifdef CONFIG_PMAC_BACKLIGHT
  62 #include <asm/backlight.h>
  63 #endif
  64
  65 #ifdef CONFIG_BOOTX_TEXT
  66 #include <asm/btext.h>
  67 #endif
  68
  69 #ifdef CONFIG_ADB_PMU
  70 #include <linux/adb.h>
  71 #include <linux/pmu.h>
  72 #endif
  73
  74 #endif /* __powerpc__ */
  75
  76 #ifdef CONFIG_MTRR
  77 #include <asm/mtrr.h>
  78 #endif
  79
  80 #include <video/radeon.h>
  81 #include <linux/radeonfb.h>
  82
  83 #define DEBUG   1
  84
  85 #if DEBUG
  86 #define RTRACE          printk
  87 #else
  88 #define RTRACE          if(0) printk
  89 #endif
  90
  91 // XXX
  92 #undef CONFIG_PMAC_PBOOK
  93
  94
  95 enum radeon_chips {
  96         RADEON_QD,
  97         RADEON_QE,
  98         RADEON_QF,
  99         RADEON_QG,
 100         RADEON_QY,
 101         RADEON_QZ,
 102         RADEON_LW,
 103         RADEON_LX,
 104         RADEON_LY,
 105         RADEON_LZ,
 106         RADEON_QL,
 107         RADEON_QN,
 108         RADEON_QO,
 109         RADEON_Ql,
 110         RADEON_BB,
 111         RADEON_QW,
 112         RADEON_QX,
 113         RADEON_Id,
 114         RADEON_Ie,
 115         RADEON_If,
 116         RADEON_Ig,
 117         RADEON_Ld,
 118         RADEON_Le,
 119         RADEON_Lf,
 120         RADEON_Lg,
 121         RADEON_ND,
 122         RADEON_NE,
 123         RADEON_NF,
 124         RADEON_NG,
 125         RADEON_QM
 126 };
 127
 128 enum radeon_arch {
 129         RADEON_R100,
 130         RADEON_RV100,
 131         RADEON_R200,
 132         RADEON_RV200,
 133         RADEON_RV250,
 134         RADEON_R300,
 135         RADEON_M6,
 136         RADEON_M7,
 137         RADEON_M9
 138 };
 139
 140 static struct radeon_chip_info {
 141         const char *name;
 142         unsigned char arch;
 143 } radeon_chip_info[] __devinitdata = {
 144         { "QD", RADEON_R100 },
 145         { "QE", RADEON_R100 },
 146         { "QF", RADEON_R100 },
 147         { "QG", RADEON_R100 },
 148         { "VE QY", RADEON_RV100 },
 149         { "VE QZ", RADEON_RV100 },
 150         { "M7 LW", RADEON_M7 },
 151         { "M7 LX", RADEON_M7 },
 152         { "M6 LY", RADEON_M6 },
 153         { "M6 LZ", RADEON_M6 },
 154         { "8500 QL", RADEON_R200 },
 155         { "8500 QN", RADEON_R200 },
 156         { "8500 QO", RADEON_R200 },
 157         { "8500 Ql", RADEON_R200 },
 158         { "8500 BB", RADEON_R200 },
 159         { "7500 QW", RADEON_RV200 },
 160         { "7500 QX", RADEON_RV200 },
 161         { "9000 Id", RADEON_RV250 },
 162         { "9000 Ie", RADEON_RV250 },
 163         { "9000 If", RADEON_RV250 },
 164         { "9000 Ig", RADEON_RV250 },
 165         { "M9 Ld", RADEON_M9 },
 166         { "M9 Le", RADEON_M9 },
 167         { "M9 Lf", RADEON_M9 },
 168         { "M9 Lg", RADEON_M9 },
 169         { "9700 ND", RADEON_R300 },
 170         { "9700 NE", RADEON_R300 },
 171         { "9700 NF", RADEON_R300 },
 172         { "9700 NG", RADEON_R300 },
 173         { "9100 QM", RADEON_R200 }
 174 };
 175
 176
 177 enum radeon_montype
 178 {
 179         MT_NONE,
 180         MT_CRT,         /* CRT */
 181         MT_LCD,         /* LCD */
 182         MT_DFP,         /* DVI */
 183         MT_CTV,         /* composite TV */
 184         MT_STV          /* S-Video out */
 185 };
 186
 187
 188 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
 189         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
 190         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
 191         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
 192         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
 193         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
 194         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
 195         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
 196         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
 197         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
 198         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
 199         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
 200         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
 201         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
 202         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
 203         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
 204         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
 205         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
 206         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
 207         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
 208         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
 209         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
 210         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
 211         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
 212         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
 213         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
 214         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
 215         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
 216         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
 217         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
 218         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
 219         { 0, }
 220 };
 221 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 222
 223
 224 typedef struct {
 225         u16 reg;
 226         u32 val;
 227 } reg_val;
 228
 229
 230 /* these common regs are cleared before mode setting so they do not
 231  * interfere with anything
 232  */
 233 reg_val common_regs[] = {
 234         { OVR_CLR, 0 },
 235         { OVR_WID_LEFT_RIGHT, 0 },
 236         { OVR_WID_TOP_BOTTOM, 0 },
 237         { OV0_SCALE_CNTL, 0 },
 238         { SUBPIC_CNTL, 0 },
 239         { VIPH_CONTROL, 0 },
 240         { I2C_CNTL_1, 0 },
 241         { GEN_INT_CNTL, 0 },
 242         { CAP0_TRIG_CNTL, 0 },
 243 };
 244
 245 reg_val common_regs_m6[] = {
 246         { OVR_CLR,      0 },
 247         { OVR_WID_LEFT_RIGHT,   0 },
 248         { OVR_WID_TOP_BOTTOM,   0 },
 249         { OV0_SCALE_CNTL,   0 },
 250         { SUBPIC_CNTL,      0 },
 251         { GEN_INT_CNTL,     0 },
 252         { CAP0_TRIG_CNTL,   0 }
 253 };
 254
 255 typedef struct {
 256         u8 clock_chip_type;
 257         u8 struct_size;
 258         u8 accelerator_entry;
 259         u8 VGA_entry;
 260         u16 VGA_table_offset;
 261         u16 POST_table_offset;
 262         u16 XCLK;
 263         u16 MCLK;
 264         u8 num_PLL_blocks;
 265         u8 size_PLL_blocks;
 266         u16 PCLK_ref_freq;
 267         u16 PCLK_ref_divider;
 268         u32 PCLK_min_freq;
 269         u32 PCLK_max_freq;
 270         u16 MCLK_ref_freq;
 271         u16 MCLK_ref_divider;
 272         u32 MCLK_min_freq;
 273         u32 MCLK_max_freq;
 274         u16 XCLK_ref_freq;
 275         u16 XCLK_ref_divider;
 276         u32 XCLK_min_freq;
 277         u32 XCLK_max_freq;
 278 } __attribute__ ((packed)) PLL_BLOCK;
 279
 280
 281 struct pll_info {
 282         int ppll_max;
 283         int ppll_min;
 284         int xclk;
 285         int ref_div;
 286         int ref_clk;
 287 };
 288
 289
 290 struct ram_info {
 291         int ml;
 292         int mb;
 293         int trcd;
 294         int trp;
 295         int twr;
 296         int cl;
 297         int tr2w;
 298         int loop_latency;
 299         int rloop;
 300 };
 301
 302
 303 struct radeon_regs {
 304         /* CRTC regs */
 305         u32 crtc_h_total_disp;
 306         u32 crtc_h_sync_strt_wid;
 307         u32 crtc_v_total_disp;
 308         u32 crtc_v_sync_strt_wid;
 309         u32 crtc_pitch;
 310         u32 crtc_gen_cntl;
 311         u32 crtc_ext_cntl;
 312         u32 dac_cntl;
 313
 314         u32 flags;
 315         u32 pix_clock;
 316         int xres, yres;
 317
 318         /* DDA regs */
 319         u32 dda_config;
 320         u32 dda_on_off;
 321
 322         /* PLL regs */
 323         u32 ppll_div_3;
 324         u32 ppll_ref_div;
 325         u32 vclk_ecp_cntl;
 326
 327         /* Flat panel regs */
 328         u32 fp_crtc_h_total_disp;
 329         u32 fp_crtc_v_total_disp;
 330         u32 fp_gen_cntl;
 331         u32 fp_h_sync_strt_wid;
 332         u32 fp_horz_stretch;
 333         u32 fp_panel_cntl;
 334         u32 fp_v_sync_strt_wid;
 335         u32 fp_vert_stretch;
 336         u32 lvds_gen_cntl;
 337         u32 lvds_pll_cntl;
 338         u32 tmds_crc;
 339         u32 tmds_transmitter_cntl;
 340
 341 #if defined(__BIG_ENDIAN)
 342         u32 surface_cntl;
 343 #endif
 344 };
 345
 346
 347 struct radeonfb_info {
 348         struct fb_info info;
 349
 350         struct radeon_regs state;
 351         struct radeon_regs init_state;
 352
 353         char name[32];
 354         char ram_type[12];
 355
 356         unsigned long mmio_base_phys;
 357         unsigned long fb_base_phys;
 358
 359         unsigned long mmio_base;
 360         unsigned long fb_base;
 361
 362         struct pci_dev *pdev;
 363
 364         unsigned char *EDID;
 365         unsigned char *bios_seg;
 366
 367         u32 pseudo_palette[17];
 368         struct { u8 red, green, blue, pad; } palette[256];
 369
 370         int chipset;
 371         unsigned char arch;
 372         int video_ram;
 373         u8 rev;
 374         int pitch, bpp, depth;
 375         int xres, yres, pixclock;
 376         int xres_virtual, yres_virtual;
 377         u32 accel_flags;
 378
 379         int use_default_var;
 380         int got_dfpinfo;
 381
 382         int hasCRTC2;
 383         int crtDisp_type;
 384         int dviDisp_type;
 385
 386         int panel_xres, panel_yres;
 387         int clock;
 388         int hOver_plus, hSync_width, hblank;
 389         int vOver_plus, vSync_width, vblank;
 390         int hAct_high, vAct_high, interlaced;
 391         int synct, misc;
 392
 393         u32 dp_gui_master_cntl;
 394
 395         struct pll_info pll;
 396         int pll_output_freq, post_div, fb_div;
 397
 398         struct ram_info ram;
 399
 400         int mtrr_hdl;
 401
 402 #ifdef CONFIG_PMAC_PBOOK
 403         int pm_reg;
 404         u32 save_regs[64];
 405         u32 mdll, mdll2;
 406 #endif /* CONFIG_PMAC_PBOOK */
 407         int asleep;
 408
 409         struct radeonfb_info *next;
 410 };
 411
 412
 413 static struct fb_var_screeninfo radeonfb_default_var = {
 414         640, 480, 640, 480, 0, 0, 8, 0,
 415         {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
 416         0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
 417         0, FB_VMODE_NONINTERLACED
 418 };
 419
 420 /*
 421  * IO macros
 422  */
 423
 424 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 425 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 426 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 427 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 428
 429 #define OUTPLL(addr,val)        \
 430         do {    \
 431                 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
 432                 OUTREG(CLOCK_CNTL_DATA, val); \
 433         } while(0)
 434
 435 #define OUTPLLP(addr,val,mask)                                          \
 436         do {                                                            \
 437                 unsigned int _tmp = INPLL(addr);                        \
 438                 _tmp &= (mask);                                         \
 439                 _tmp |= (val);                                          \
 440                 OUTPLL(addr, _tmp);                                     \
 441         } while (0)
 442
 443 #define OUTREGP(addr,val,mask)                                          \
 444         do {                                                            \
 445                 unsigned int _tmp = INREG(addr);                        \
 446                 _tmp &= (mask);                                         \
 447                 _tmp |= (val);                                          \
 448                 OUTREG(addr, _tmp);                                     \
 449         } while (0)
 450
 451
 452 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
 453 {
 454         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 455         return (INREG(CLOCK_CNTL_DATA));
 456 }
 457
 458 #define INPLL(addr)             _INPLL(rinfo, addr)
 459
 460 #define PRIMARY_MONITOR(rinfo)  ((rinfo->dviDisp_type != MT_NONE) &&    \
 461                                  (rinfo->dviDisp_type != MT_STV) &&     \
 462                                  (rinfo->dviDisp_type != MT_CTV) ?      \
 463                                  rinfo->dviDisp_type : rinfo->crtDisp_type)
 464
 465 static char *GET_MON_NAME(int type)
 466 {
 467         char *pret = NULL;
 468
 469         switch (type) {
 470                 case MT_NONE:
 471                         pret = "no";
 472                         break;
 473                 case MT_CRT:
 474                         pret = "CRT";
 475                         break;
 476                 case MT_DFP:
 477                         pret = "DFP";
 478                         break;
 479                 case MT_LCD:
 480                         pret = "LCD";
 481                         break;
 482                 case MT_CTV:
 483                         pret = "CTV";
 484                         break;
 485                 case MT_STV:
 486                         pret = "STV";
 487                         break;
 488         }
 489
 490         return pret;
 491 }
 492
 493
 494 /*
 495  * 2D engine routines
 496  */
 497
 498 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
 499 {
 500         int i;
 501
 502         /* initiate flush */
 503         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 504                 ~RB2D_DC_FLUSH_ALL);
 505
 506         for (i=0; i < 2000000; i++) {
 507                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 508                         break;
 509         }
 510 }
 511
 512
 513 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 514 {
 515         int i;
 516
 517         for (i=0; i<2000000; i++)
 518                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 519                         return;
 520 }
 521
 522
 523 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
 524 {
 525         int i;
 526
 527         /* ensure FIFO is empty before waiting for idle */
 528         _radeon_fifo_wait (rinfo, 64);
 529
 530         for (i=0; i<2000000; i++) {
 531                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 532                         radeon_engine_flush (rinfo);
 533                         return;
 534                 }
 535         }
 536 }
 537
 538
 539 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 540 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 541
 542
 543
 544 /*
 545  * helper routines
 546  */
 547
 548 static __inline__ u32 radeon_get_dstbpp(u16 depth)
 549 {
 550         switch (depth) {
 551                 case 8:
 552                         return DST_8BPP;
 553                 case 15:
 554                         return DST_15BPP;
 555                 case 16:
 556                         return DST_16BPP;
 557                 case 32:
 558                         return DST_32BPP;
 559                 default:
 560                         return 0;
 561         }
 562 }
 563
 564
 565 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 566 {
 567         if (var->bits_per_pixel != 16)
 568                 return var->bits_per_pixel;
 569         return (var->green.length == 6) ? 16 : 15;
 570 }
 571
 572
 573 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
 574 {
 575         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 576
 577         radeon_engine_flush (rinfo);
 578
 579         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 580         mclk_cntl = INPLL(MCLK_CNTL);
 581
 582         OUTPLL(MCLK_CNTL, (mclk_cntl |
 583                            FORCEON_MCLKA |
 584                            FORCEON_MCLKB |
 585                            FORCEON_YCLKA |
 586                            FORCEON_YCLKB |
 587                            FORCEON_MC |
 588                            FORCEON_AIC));
 589         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 590
 591         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 592                                 SOFT_RESET_CP |
 593                                 SOFT_RESET_HI |
 594                                 SOFT_RESET_SE |
 595                                 SOFT_RESET_RE |
 596                                 SOFT_RESET_PP |
 597                                 SOFT_RESET_E2 |
 598                                 SOFT_RESET_RB);
 599         INREG(RBBM_SOFT_RESET);
 600         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 601                                 ~(SOFT_RESET_CP |
 602                                   SOFT_RESET_HI |
 603                                   SOFT_RESET_SE |
 604                                   SOFT_RESET_RE |
 605                                   SOFT_RESET_PP |
 606                                   SOFT_RESET_E2 |
 607                                   SOFT_RESET_RB));
 608         INREG(RBBM_SOFT_RESET);
 609
 610         OUTPLL(MCLK_CNTL, mclk_cntl);
 611         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 612         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 613
 614         return;
 615 }
 616
 617 #define radeon_engine_reset()           _radeon_engine_reset(rinfo)
 618
 619
 620 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
 621 {
 622         switch (post_div) {
 623                 case 1:
 624                         return 0x00;
 625                 case 2:
 626                         return 0x01;
 627                 case 3:
 628                         return 0x04;
 629                 case 4:
 630                         return 0x02;
 631                 case 6:
 632                         return 0x06;
 633                 case 8:
 634                         return 0x03;
 635                 case 12:
 636                         return 0x07;
 637                 default:
 638                         return 0x02;
 639         }
 640 }
 641
 642
 643
 644 static __inline__ int round_div(int num, int den)
 645 {
 646         return (num + (den / 2)) / den;
 647 }
 648
 649
 650
 651 static __inline__ int min_bits_req(int val)
 652 {
 653         int bits_req = 0;
 654
 655         if (val == 0)
 656                 bits_req = 1;
 657
 658         while (val) {
 659                 val >>= 1;
 660                 bits_req++;
 661         }
 662
 663         return (bits_req);
 664 }
 665
 666
 667 static __inline__ int _max(int val1, int val2)
 668 {
 669         if (val1 >= val2)
 670                 return val1;
 671         else
 672                 return val2;
 673 }
 674
 675
 676
 677 /*
 678  * globals
 679  */
 680
 681 static char *mode_option __initdata;
 682 static char noaccel = 1;
 683 static char mirror = 0;
 684 static int panel_yres __initdata = 0;
 685 static char force_dfp __initdata = 0;
 686 static struct radeonfb_info *board_list = NULL;
 687 static char nomtrr __initdata = 0;
 688
 689 /*
 690  * prototypes
 691  */
 692
 693 static void radeon_save_state (struct radeonfb_info *rinfo,
 694                                struct radeon_regs *save);
 695 static void radeon_engine_init (struct radeonfb_info *rinfo);
 696 static void radeon_write_mode (struct radeonfb_info *rinfo,
 697                                struct radeon_regs *mode);
 698 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
 699 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
 700 static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
 701 static char *radeon_find_rom(struct radeonfb_info *rinfo);
 702 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
 703 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
 704 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
 705 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
 706 static void radeon_get_EDID(struct radeonfb_info *rinfo);
 707 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
 708 static void radeon_update_default_var(struct radeonfb_info *rinfo);
 709
 710 #ifdef CONFIG_ALL_PPC
 711
 712 static int radeon_read_OF (struct radeonfb_info *rinfo);
 713 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
 714 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
 715
 716 #ifdef CONFIG_PMAC_PBOOK
 717 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
 718 static struct pmu_sleep_notifier radeon_sleep_notifier = {
 719         radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
 720 };
 721 #endif /* CONFIG_PMAC_PBOOK */
 722 #ifdef CONFIG_PMAC_BACKLIGHT
 723 static int radeon_set_backlight_enable(int on, int level, void *data);
 724 static int radeon_set_backlight_level(int level, void *data);
 725 static struct backlight_controller radeon_backlight_controller = {
 726         radeon_set_backlight_enable,
 727         radeon_set_backlight_level
 728 };
 729 #endif /* CONFIG_PMAC_BACKLIGHT */
 730
 731 #endif /* CONFIG_ALL_PPC */
 732
 733
 734 static char *radeon_find_rom(struct radeonfb_info *rinfo)
 735 {
 736 #if defined(__i386__)
 737         u32  segstart;
 738         char *rom_base;
 739         char *rom;
 740         int  stage;
 741         int  i,j;
 742         char aty_rom_sig[] = "761295520";
 743         char *radeon_sig[] = {
 744           "RG6",
 745           "RADEON"
 746         };
 747
 748         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 749
 750                 stage = 1;
 751
 752                 rom_base = (char *)ioremap(segstart, 0x1000);
 753
 754                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
 755                         stage = 2;
 756
 757
 758                 if (stage != 2) {
 759                         iounmap(rom_base);
 760                         continue;
 761                 }
 762
 763                 rom = rom_base;
 764
 765                 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
 766                         if (aty_rom_sig[0] == *rom)
 767                                 if (strncmp(aty_rom_sig, rom,
 768                                                 strlen(aty_rom_sig)) == 0)
 769                                         stage = 3;
 770                         rom++;
 771                 }
 772                 if (stage != 3) {
 773                         iounmap(rom_base);
 774                         continue;
 775                 }
 776                 rom = rom_base;
 777
 778                 for (i = 0; (i < 512) && (stage != 4); i++) {
 779                     for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
 780                         if (radeon_sig[j][0] == *rom)
 781                                 if (strncmp(radeon_sig[j], rom,
 782                                             strlen(radeon_sig[j])) == 0) {
 783                                               stage = 4;
 784                                               break;
 785                                             }
 786                     }
 787                         rom++;
 788                 }
 789                 if (stage != 4) {
 790                         iounmap(rom_base);
 791                         continue;
 792                 }
 793
 794                 return rom_base;
 795         }
 796 #endif
 797         return NULL;
 798 }
 799
 800
 801
 802
 803 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
 804 {
 805         void *bios_header;
 806         void *header_ptr;
 807         u16 bios_header_offset, pll_info_offset;
 808         PLL_BLOCK pll;
 809
 810         if (bios_seg) {
 811                 bios_header = bios_seg + 0x48L;
 812                 header_ptr  = bios_header;
 813
 814                 bios_header_offset = readw(header_ptr);
 815                 bios_header = bios_seg + bios_header_offset;
 816                 bios_header += 0x30;
 817
 818                 header_ptr = bios_header;
 819                 pll_info_offset = readw(header_ptr);
 820                 header_ptr = bios_seg + pll_info_offset;
 821
 822                 memcpy_fromio(&pll, header_ptr, 50);
 823
 824                 rinfo->pll.xclk = (u32)pll.XCLK;
 825                 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
 826                 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
 827                 rinfo->pll.ppll_min = pll.PCLK_min_freq;
 828                 rinfo->pll.ppll_max = pll.PCLK_max_freq;
 829
 830                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
 831                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 832         } else {
 833 #ifdef CONFIG_ALL_PPC
 834                 if (radeon_read_OF(rinfo)) {
 835                         unsigned int tmp, Nx, M, ref_div, xclk;
 836
 837                         tmp = INPLL(M_SPLL_REF_FB_DIV);
 838                         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 839
 840                         Nx = (tmp & 0xff00) >> 8;
 841                         M = (tmp & 0xff);
 842                         xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
 843                                 (2 * M)));
 844
 845                         rinfo->pll.xclk = xclk;
 846                         rinfo->pll.ref_div = ref_div;
 847                         rinfo->pll.ppll_min = 12000;
 848                         rinfo->pll.ppll_max = 35000;
 849
 850                         printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
 851                                 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 852
 853                         return;
 854                 }
 855 #endif
 856                 /* no BIOS or BIOS not found, use defaults */
 857                 switch (rinfo->chipset) {
 858                         case PCI_DEVICE_ID_ATI_RADEON_QW:
 859                         case PCI_DEVICE_ID_ATI_RADEON_QX:
 860                                 rinfo->pll.ppll_max = 35000;
 861                                 rinfo->pll.ppll_min = 12000;
 862                                 rinfo->pll.xclk = 23000;
 863                                 rinfo->pll.ref_div = 12;
 864                                 rinfo->pll.ref_clk = 2700;
 865                                 break;
 866                         case PCI_DEVICE_ID_ATI_RADEON_QL:
 867                         case PCI_DEVICE_ID_ATI_RADEON_QN:
 868                         case PCI_DEVICE_ID_ATI_RADEON_QO:
 869                         case PCI_DEVICE_ID_ATI_RADEON_Ql:
 870                         case PCI_DEVICE_ID_ATI_RADEON_BB:
 871                                 rinfo->pll.ppll_max = 35000;
 872                                 rinfo->pll.ppll_min = 12000;
 873                                 rinfo->pll.xclk = 27500;
 874                                 rinfo->pll.ref_div = 12;
 875                                 rinfo->pll.ref_clk = 2700;
 876                                 break;
 877                         case PCI_DEVICE_ID_ATI_RADEON_Id:
 878                         case PCI_DEVICE_ID_ATI_RADEON_Ie:
 879                         case PCI_DEVICE_ID_ATI_RADEON_If:
 880                         case PCI_DEVICE_ID_ATI_RADEON_Ig:
 881                                 rinfo->pll.ppll_max = 35000;
 882                                 rinfo->pll.ppll_min = 12000;
 883                                 rinfo->pll.xclk = 25000;
 884                                 rinfo->pll.ref_div = 12;
 885                                 rinfo->pll.ref_clk = 2700;
 886                                 break;
 887                         case PCI_DEVICE_ID_ATI_RADEON_ND:
 888                         case PCI_DEVICE_ID_ATI_RADEON_NE:
 889                         case PCI_DEVICE_ID_ATI_RADEON_NF:
 890                         case PCI_DEVICE_ID_ATI_RADEON_NG:
 891                                 rinfo->pll.ppll_max = 40000;
 892                                 rinfo->pll.ppll_min = 20000;
 893                                 rinfo->pll.xclk = 27000;
 894                                 rinfo->pll.ref_div = 12;
 895                                 rinfo->pll.ref_clk = 2700;
 896                                 break;
 897                         case PCI_DEVICE_ID_ATI_RADEON_QD:
 898                         case PCI_DEVICE_ID_ATI_RADEON_QE:
 899                         case PCI_DEVICE_ID_ATI_RADEON_QF:
 900                         case PCI_DEVICE_ID_ATI_RADEON_QG:
 901                         default:
 902                                 rinfo->pll.ppll_max = 35000;
 903                                 rinfo->pll.ppll_min = 12000;
 904                                 rinfo->pll.xclk = 16600;
 905                                 rinfo->pll.ref_div = 67;
 906                                 rinfo->pll.ref_clk = 2700;
 907                                 break;
 908                 }
 909
 910                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
 911                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
 912         }
 913 }
 914
 915
 916 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
 917 {
 918         unsigned int tmp;
 919
 920         if (force_dfp) {
 921                 rinfo->dviDisp_type = MT_DFP;
 922                 return;
 923         }
 924
 925         tmp = INREG(RADEON_BIOS_4_SCRATCH);
 926         printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
 927
 928         if (rinfo->hasCRTC2) {
 929                 /* primary DVI port */
 930                 if (tmp & 0x08)
 931                         rinfo->dviDisp_type = MT_DFP;
 932                 else if (tmp & 0x4)
 933                         rinfo->dviDisp_type = MT_LCD;
 934                 else if (tmp & 0x200)
 935                         rinfo->dviDisp_type = MT_CRT;
 936                 else if (tmp & 0x10)
 937                         rinfo->dviDisp_type = MT_CTV;
 938                 else if (tmp & 0x20)
 939                         rinfo->dviDisp_type = MT_STV;
 940
 941                 /* secondary CRT port */
 942                 if (tmp & 0x2)
 943                         rinfo->crtDisp_type = MT_CRT;
 944                 else if (tmp & 0x800)
 945                         rinfo->crtDisp_type = MT_DFP;
 946                 else if (tmp & 0x400)
 947                         rinfo->crtDisp_type = MT_LCD;
 948                 else if (tmp & 0x1000)
 949                         rinfo->crtDisp_type = MT_CTV;
 950                 else if (tmp & 0x2000)
 951                         rinfo->crtDisp_type = MT_STV;
 952         } else {
 953                 rinfo->dviDisp_type = MT_NONE;
 954
 955                 tmp = INREG(FP_GEN_CNTL);
 956
 957                 if (tmp & FP_EN_TMDS)
 958                         rinfo->crtDisp_type = MT_DFP;
 959                 else
 960                         rinfo->crtDisp_type = MT_CRT;
 961         }
 962 }
 963
 964
 965
 966 static void radeon_get_EDID(struct radeonfb_info *rinfo)
 967 {
 968 #ifdef CONFIG_ALL_PPC
 969         if (!radeon_get_EDID_OF(rinfo))
 970                 RTRACE("radeonfb: could not retrieve EDID from OF\n");
 971 #else
 972         /* XXX use other methods later */
 973 #endif
 974 }
 975
 976
 977 #ifdef CONFIG_ALL_PPC
 978 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
 979 {
 980         struct device_node *dp;
 981         unsigned char *pedid = NULL;
 982         static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
 983         int i;
 984
 985         dp = pci_device_to_OF_node(rinfo->pdev);
 986         while (dp != NULL) {
 987                 for (i = 0; propnames[i] != NULL; ++i) {
 988                         pedid = (unsigned char *)
 989                                 get_property(dp, propnames[i], NULL);
 990                         if (pedid != NULL) {
 991                                 rinfo->EDID = pedid;
 992                                 return 1;
 993                         }
 994                 }
 995                 dp = dp->child;
 996         }
 997         return 0;
 998 }
 999 #endif /* CONFIG_ALL_PPC */
1000
1001
1002 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
1003 {
1004         unsigned char *block = rinfo->EDID;
1005
1006         if (!block)
1007                 return 0;
1008
1009         /* jump to the detailed timing block section */
1010         block += 54;
1011
1012         rinfo->clock = (block[0] + (block[1] << 8));
1013         rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1014         rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1015         rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1016         rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1017         rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1018         rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1019         rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1020         rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1021         rinfo->interlaced = ((block[17] & 0x80) >> 7);
1022         rinfo->synct = ((block[17] & 0x18) >> 3);
1023         rinfo->misc = ((block[17] & 0x06) >> 1);
1024         rinfo->hAct_high = rinfo->vAct_high = 0;
1025         if (rinfo->synct == 3) {
1026                 if (rinfo->misc & 2)
1027                         rinfo->hAct_high = 1;
1028                 if (rinfo->misc & 1)
1029                         rinfo->vAct_high = 1;
1030         }
1031
1032         printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1033                 rinfo->panel_xres, rinfo->panel_yres);
1034
1035         rinfo->got_dfpinfo = 1;
1036
1037         return 1;
1038 }
1039
1040
1041 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1042 {
1043         struct fb_var_screeninfo *var = &radeonfb_default_var;
1044
1045         var->xres = rinfo->panel_xres;
1046         var->yres = rinfo->panel_yres;
1047         var->xres_virtual = rinfo->panel_xres;
1048         var->yres_virtual = rinfo->panel_yres;
1049         var->xoffset = var->yoffset = 0;
1050         var->bits_per_pixel = 8;
1051         var->pixclock = 100000000 / rinfo->clock;
1052         var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1053         var->right_margin = rinfo->hOver_plus;
1054         var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1055         var->lower_margin = rinfo->vOver_plus;
1056         var->hsync_len = rinfo->hSync_width;
1057         var->vsync_len = rinfo->vSync_width;
1058         var->sync = 0;
1059         if (rinfo->synct == 3) {
1060                 if (rinfo->hAct_high)
1061                         var->sync |= FB_SYNC_HOR_HIGH_ACT;
1062                 if (rinfo->vAct_high)
1063                         var->sync |= FB_SYNC_VERT_HIGH_ACT;
1064         }
1065
1066         var->vmode = 0;
1067         if (rinfo->interlaced)
1068                 var->vmode |= FB_VMODE_INTERLACED;
1069
1070         rinfo->use_default_var = 1;
1071 }
1072
1073
1074 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1075 {
1076         char *fpbiosstart, *tmp, *tmp0;
1077         char stmp[30];
1078         int i;
1079
1080         if (!rinfo->bios_seg)
1081                 return 0;
1082
1083         if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1084                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1085                 return 0;
1086         }
1087
1088         if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1089                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1090                 return 0;
1091         }
1092
1093         for(i=0; i<24; i++)
1094                 stmp[i] = readb(tmp+i+1);
1095         stmp[24] = 0;
1096         printk("radeonfb: panel ID string: %s\n", stmp);
1097         rinfo->panel_xres = readw(tmp + 25);
1098         rinfo->panel_yres = readw(tmp + 27);
1099         printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1100                 rinfo->panel_xres, rinfo->panel_yres);
1101
1102         for(i=0; i<20; i++) {
1103                 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1104                 if (tmp0 == 0)
1105                         break;
1106                 if ((readw(tmp0) == rinfo->panel_xres) &&
1107                     (readw(tmp0+2) == rinfo->panel_yres)) {
1108                         rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1109                         rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1110                         rinfo->hSync_width = readb(tmp0+23) * 8;
1111                         rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1112                         rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1113                         rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1114                         rinfo->clock = readw(tmp0+9);
1115
1116                         rinfo->got_dfpinfo = 1;
1117                         return 1;
1118                 }
1119         }
1120
1121         return 0;
1122 }
1123
1124
1125
1126 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1127 {
1128         unsigned int tmp;
1129         unsigned short a, b;
1130
1131         if (radeon_get_dfpinfo_BIOS(rinfo))
1132                 radeon_update_default_var(rinfo);
1133
1134         if (radeon_dfp_parse_EDID(rinfo))
1135                 radeon_update_default_var(rinfo);
1136
1137         if (!rinfo->got_dfpinfo) {
1138                 /*
1139                  * it seems all else has failed now and we
1140                  * resort to probing registers for our DFP info
1141                  */
1142                 if (panel_yres) {
1143                         rinfo->panel_yres = panel_yres;
1144                 } else {
1145                         tmp = INREG(FP_VERT_STRETCH);
1146                         tmp &= 0x00fff000;
1147                         rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1148                 }
1149
1150                 switch (rinfo->panel_yres) {
1151                         case 480:
1152                                 rinfo->panel_xres = 640;
1153                                 break;
1154                         case 600:
1155                                 rinfo->panel_xres = 800;
1156                                 break;
1157                         case 768:
1158 #if defined(__powerpc__)
1159                                 if (rinfo->dviDisp_type == MT_LCD)
1160                                         rinfo->panel_xres = 1152;
1161                                 else
1162 #endif
1163                                 rinfo->panel_xres = 1024;
1164                                 break;
1165                         case 1024:
1166                                 rinfo->panel_xres = 1280;
1167                                 break;
1168                         case 1050:
1169                                 rinfo->panel_xres = 1400;
1170                                 break;
1171                         case 1200:
1172                                 rinfo->panel_xres = 1600;
1173                                 break;
1174                         default:
1175                                 printk("radeonfb: Failed to detect DFP panel size\n");
1176                                 return 0;
1177                 }
1178
1179                 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1180                         rinfo->panel_xres, rinfo->panel_yres);
1181
1182                 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1183                 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1184                 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1185                 rinfo->hblank = (a - b + 1) * 8;
1186
1187                 tmp = INREG(FP_H_SYNC_STRT_WID);
1188                 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1189                                         FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1190                 rinfo->hOver_plus *= 8;
1191                 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1192                                         FP_H_SYNC_WID_SHIFT);
1193                 rinfo->hSync_width *= 8;
1194                 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1195                 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1196                 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1197                 rinfo->vblank = a - b /* + 24 */ ;
1198
1199                 tmp = INREG(FP_V_SYNC_STRT_WID);
1200                 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1201                                         - b + 1;
1202                 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1203                                         FP_V_SYNC_WID_SHIFT);
1204
1205                 return 1;
1206         }
1207
1208         return 1;
1209 }
1210
1211
1212 #ifdef CONFIG_ALL_PPC
1213 static int radeon_read_OF (struct radeonfb_info *rinfo)
1214 {
1215         struct device_node *dp;
1216         unsigned int *xtal;
1217
1218         dp = pci_device_to_OF_node(rinfo->pdev);
1219
1220         xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
1221
1222         rinfo->pll.ref_clk = *xtal / 10;
1223
1224         if (*xtal)
1225                 return 1;
1226         else
1227                 return 0;
1228 }
1229 #endif
1230
1231
1232 static void radeon_engine_init (struct radeonfb_info *rinfo)
1233 {
1234         u32 temp;
1235
1236         /* disable 3D engine */
1237         OUTREG(RB3D_CNTL, 0);
1238
1239         radeon_engine_reset ();
1240
1241         radeon_fifo_wait (1);
1242         OUTREG(RB2D_DSTCACHE_MODE, 0);
1243
1244         /* XXX */
1245         rinfo->pitch = ((rinfo->xres_virtual * (rinfo->bpp / 8) + 0x3f)) >> 6;
1246
1247         radeon_fifo_wait (1);
1248         temp = INREG(DEFAULT_PITCH_OFFSET);
1249         OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1250                                       (rinfo->pitch << 0x16)));
1251
1252         radeon_fifo_wait (1);
1253         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1254
1255         radeon_fifo_wait (1);
1256         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1257                                          DEFAULT_SC_BOTTOM_MAX));
1258
1259         temp = radeon_get_dstbpp(rinfo->depth);
1260         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1261         radeon_fifo_wait (1);
1262         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1263                                     GMC_BRUSH_SOLID_COLOR |
1264                                     GMC_SRC_DATATYPE_COLOR));
1265
1266         radeon_fifo_wait (7);
1267
1268         /* clear line drawing regs */
1269         OUTREG(DST_LINE_START, 0);
1270         OUTREG(DST_LINE_END, 0);
1271
1272         /* set brush color regs */
1273         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1274         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1275
1276         /* set source color regs */
1277         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1278         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1279
1280         /* default write mask */
1281         OUTREG(DP_WRITE_MSK, 0xffffffff);
1282
1283         radeon_engine_idle ();
1284 }
1285
1286
1287 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1288 {
1289         struct fb_info *info = &rinfo->info;
1290         struct fb_var_screeninfo var;
1291
1292         var = radeonfb_default_var;
1293         if ((radeon_init_disp_var(rinfo, &var)) < 0)
1294                 return -1;
1295
1296         rinfo->depth = var_to_depth(&var);
1297         rinfo->bpp = var.bits_per_pixel;
1298
1299         info->var = var;
1300         fb_alloc_cmap(&info->cmap, 256, 0);
1301
1302         var.activate = FB_ACTIVATE_NOW;
1303         return 0;
1304 }
1305
1306
1307 static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1308                                  struct fb_var_screeninfo *var)
1309 {
1310 #ifndef MODULE
1311         if (mode_option)
1312                 fb_find_mode (var, &rinfo->info, mode_option,
1313                               NULL, 0, NULL, 8);
1314         else
1315 #endif
1316         if (rinfo->use_default_var)
1317                 /* We will use the modified default far */
1318                 *var = radeonfb_default_var;
1319         else
1320
1321                 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1322                               NULL, 0, NULL, 0);
1323
1324         if (noaccel)
1325                 var->accel_flags &= ~FB_ACCELF_TEXT;
1326         else
1327                 var->accel_flags |= FB_ACCELF_TEXT;
1328
1329         return 0;
1330 }
1331
1332
1333 static int radeon_do_maximize(struct radeonfb_info *rinfo,
1334                                 struct fb_var_screeninfo *var,
1335                                 struct fb_var_screeninfo *v,
1336                                 int nom, int den)
1337 {
1338         static struct {
1339                 int xres, yres;
1340         } modes[] = {
1341                 {1600, 1280},
1342                 {1280, 1024},
1343                 {1024, 768},
1344                 {800, 600},
1345                 {640, 480},
1346                 {-1, -1}
1347         };
1348         int i;
1349
1350         /* use highest possible virtual resolution */
1351         if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1352                 printk("radeonfb: using max available virtual resolution\n");
1353                 for (i=0; modes[i].xres != -1; i++) {
1354                         if (modes[i].xres * nom / den * modes[i].yres <
1355                             rinfo->video_ram / 2)
1356                                 break;
1357                 }
1358                 if (modes[i].xres == -1) {
1359                         printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1360                         return -EINVAL;
1361                 }
1362                 v->xres_virtual = modes[i].xres;
1363                 v->yres_virtual = modes[i].yres;
1364
1365                 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1366                         v->xres_virtual, v->yres_virtual);
1367         } else if (v->xres_virtual == -1) {
1368                 v->xres_virtual = (rinfo->video_ram * den /
1369                                 (nom * v->yres_virtual * 2)) & ~15;
1370         } else if (v->yres_virtual == -1) {
1371                 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1372                 v->yres_virtual = rinfo->video_ram * den /
1373                         (nom * v->xres_virtual *2);
1374         } else {
1375                 if (v->xres_virtual * nom / den * v->yres_virtual >
1376                         rinfo->video_ram) {
1377                         return -EINVAL;
1378                 }
1379         }
1380
1381         if (v->xres_virtual * nom / den >= 8192) {
1382                 v->xres_virtual = 8192 * den / nom - 16;
1383         }
1384
1385         if (v->xres_virtual < v->xres)
1386                 return -EINVAL;
1387
1388         if (v->yres_virtual < v->yres)
1389                 return -EINVAL;
1390
1391         return 0;
1392 }
1393
1394
1395 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1396 {
1397         struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1398         struct fb_var_screeninfo v;
1399         int nom, den;
1400
1401         memcpy (&v, var, sizeof (v));
1402
1403         switch (v.bits_per_pixel) {
1404                 case 0 ... 8:
1405                         v.bits_per_pixel = 8;
1406                         break;
1407                 case 9 ... 16:
1408                         v.bits_per_pixel = 16;
1409                         break;
1410                 case 17 ... 24:
1411 #if 0 /* Doesn't seem to work */
1412                         v.bits_per_pixel = 24;
1413                         break;
1414 #endif
1415                         return -EINVAL;
1416                 case 25 ... 32:
1417                         v.bits_per_pixel = 32;
1418                         break;
1419                 default:
1420                         return -EINVAL;
1421         }
1422
1423         switch (var_to_depth(&v)) {
1424                 case 8:
1425                         nom = den = 1;
1426                         v.red.offset = v.green.offset = v.blue.offset = 0;
1427                         v.red.length = v.green.length = v.blue.length = 8;
1428                         v.transp.offset = v.transp.length = 0;
1429                         break;
1430                 case 15:
1431                         nom = 2;
1432                         den = 1;
1433                         v.red.offset = 10;
1434                         v.green.offset = 5;
1435                         v.red.offset = 0;
1436                         v.red.length = v.green.length = v.blue.length = 5;
1437                         v.transp.offset = v.transp.length = 0;
1438                         break;
1439                 case 16:
1440                         nom = 2;
1441                         den = 1;
1442                         v.red.offset = 11;
1443                         v.green.offset = 5;
1444                         v.blue.offset = 0;
1445                         v.red.length = 5;
1446                         v.green.length = 6;
1447                         v.blue.length = 5;
1448                         v.transp.offset = v.transp.length = 0;
1449                         break;
1450                 case 24:
1451                         nom = 4;
1452                         den = 1;
1453                         v.red.offset = 16;
1454                         v.green.offset = 8;
1455                         v.blue.offset = 0;
1456                         v.red.length = v.blue.length = v.green.length = 8;
1457                         v.transp.offset = v.transp.length = 0;
1458                         break;
1459                 case 32:
1460                         nom = 4;
1461                         den = 1;
1462                         v.red.offset = 16;
1463                         v.green.offset = 8;
1464                         v.blue.offset = 0;
1465                         v.red.length = v.blue.length = v.green.length = 8;
1466                         v.transp.offset = 24;
1467                         v.transp.length = 8;
1468                         break;
1469                 default:
1470                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1471                                 var->xres, var->yres, var->bits_per_pixel);
1472                         return -EINVAL;
1473         }
1474
1475         if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1476                 return -EINVAL;
1477
1478         if (v.xoffset < 0)
1479                 v.xoffset = 0;
1480         if (v.yoffset < 0)
1481                 v.yoffset = 0;
1482
1483         if (v.xoffset > v.xres_virtual - v.xres)
1484                 v.xoffset = v.xres_virtual - v.xres - 1;
1485
1486         if (v.yoffset > v.yres_virtual - v.yres)
1487                 v.yoffset = v.yres_virtual - v.yres - 1;
1488
1489         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1490                           v.transp.offset = v.transp.length =
1491                           v.transp.msb_right = 0;
1492
1493         if (noaccel)
1494                 v.accel_flags = 0;
1495
1496         memcpy(var, &v, sizeof(v));
1497
1498         return 0;
1499 }
1500
1501
1502 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1503                                  struct fb_info *info)
1504 {
1505         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1506
1507         if ((var->xoffset + var->xres > var->xres_virtual)
1508             || (var->yoffset + var->yres > var->yres_virtual))
1509                return -EINVAL;
1510
1511         if (rinfo->asleep)
1512                 return 0;
1513
1514         OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1515                              * var->bits_per_pixel / 8) & ~7);
1516         return 0;
1517 }
1518
1519
1520 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1521                            unsigned long arg, struct fb_info *info)
1522 {
1523         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1524         unsigned int tmp;
1525         u32 value = 0;
1526         int rc;
1527
1528         switch (cmd) {
1529                 /*
1530                  * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1531                  */
1532                 case FBIO_RADEON_SET_MIRROR:
1533                         switch (rinfo->arch) {
1534                                 case RADEON_R100:
1535                                 case RADEON_RV100:
1536                                 case RADEON_R200:
1537                                 case RADEON_RV200:
1538                                 case RADEON_RV250:
1539                                 case RADEON_R300:
1540                                         return -EINVAL;
1541                                 default:
1542                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1543                                         break;
1544                         }
1545
1546                         rc = get_user(value, (__u32*)arg);
1547
1548                         if (rc)
1549                                 return rc;
1550
1551                         if (value & 0x01) {
1552                                 tmp = INREG(LVDS_GEN_CNTL);
1553
1554                                 tmp |= (LVDS_ON | LVDS_BLON);
1555                         } else {
1556                                 tmp = INREG(LVDS_GEN_CNTL);
1557
1558                                 tmp &= ~(LVDS_ON | LVDS_BLON);
1559                         }
1560
1561                         OUTREG(LVDS_GEN_CNTL, tmp);
1562
1563                         if (value & 0x02) {
1564                                 tmp = INREG(CRTC_EXT_CNTL);
1565                                 tmp |= CRTC_CRT_ON;
1566
1567                                 mirror = 1;
1568                         } else {
1569                                 tmp = INREG(CRTC_EXT_CNTL);
1570                                 tmp &= ~CRTC_CRT_ON;
1571
1572                                 mirror = 0;
1573                         }
1574
1575                         OUTREG(CRTC_EXT_CNTL, tmp);
1576
1577                         break;
1578                 case FBIO_RADEON_GET_MIRROR:
1579                         switch (rinfo->arch) {
1580                                 case RADEON_R100:
1581                                 case RADEON_RV100:
1582                                 case RADEON_R200:
1583                                 case RADEON_RV200:
1584                                 case RADEON_RV250:
1585                                 case RADEON_R300:
1586                                         return -EINVAL;
1587                                 default:
1588                                         /* RADEON M6, RADEON_M7, RADEON_M9 */
1589                                         break;
1590                         }
1591
1592                         tmp = INREG(LVDS_GEN_CNTL);
1593                         if ((LVDS_ON | LVDS_BLON) & tmp)
1594                                 value |= 0x01;
1595
1596                         tmp = INREG(CRTC_EXT_CNTL);
1597                         if (CRTC_CRT_ON & tmp)
1598                                 value |= 0x02;
1599
1600                         return put_user(value, (__u32*)arg);
1601                 default:
1602                         return -EINVAL;
1603         }
1604
1605         return -EINVAL;
1606 }
1607
1608
1609 static int radeonfb_blank (int blank, struct fb_info *info)
1610 {
1611         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1612         u32 val = INREG(CRTC_EXT_CNTL);
1613         u32 val2 = INREG(LVDS_GEN_CNTL);
1614
1615         if (rinfo->asleep)
1616                 return 0;
1617
1618 #ifdef CONFIG_PMAC_BACKLIGHT
1619         if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1620                 set_backlight_enable(!blank);
1621                 return 0;
1622         }
1623 #endif
1624
1625         /* reset it */
1626         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1627                  CRTC_VSYNC_DIS);
1628         val2 &= ~(LVDS_DISPLAY_DIS);
1629
1630         switch (blank) {
1631                 case VESA_NO_BLANKING:
1632                         break;
1633                 case VESA_VSYNC_SUSPEND:
1634                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1635                         break;
1636                 case VESA_HSYNC_SUSPEND:
1637                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1638                         break;
1639                 case VESA_POWERDOWN:
1640                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1641                                 CRTC_HSYNC_DIS);
1642                         val2 |= (LVDS_DISPLAY_DIS);
1643                         break;
1644         }
1645
1646         switch (rinfo->dviDisp_type) {
1647                 case MT_LCD:
1648                         OUTREG(LVDS_GEN_CNTL, val2);
1649                         break;
1650                 case MT_CRT:
1651                 default:
1652                         OUTREG(CRTC_EXT_CNTL, val);
1653                         break;
1654         }
1655
1656         return 0;
1657 }
1658
1659
1660 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1661                              unsigned blue, unsigned transp, struct fb_info *info)
1662 {
1663         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1664         u32 pindex, vclk_cntl;
1665         unsigned int i;
1666
1667         if (regno > 255)
1668                 return 1;
1669
1670         red >>= 8;
1671         green >>= 8;
1672         blue >>= 8;
1673         rinfo->palette[regno].red = red;
1674         rinfo->palette[regno].green = green;
1675         rinfo->palette[regno].blue = blue;
1676
1677         /* default */
1678         pindex = regno;
1679
1680         if (!rinfo->asleep) {
1681                 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1682                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1683
1684                 if (rinfo->bpp == 16) {
1685                         pindex = regno * 8;
1686
1687                         if (rinfo->depth == 16 && regno > 63)
1688                                 return 1;
1689                         if (rinfo->depth == 15 && regno > 31)
1690                                 return 1;
1691
1692                         /* For 565, the green component is mixed one order below */
1693                         if (rinfo->depth == 16) {
1694                                 OUTREG(PALETTE_INDEX, pindex>>1);
1695                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1696                                         (green << 8) | (rinfo->palette[regno>>1].blue));
1697                                 green = rinfo->palette[regno<<1].green;
1698                         }
1699                 }
1700
1701                 if (rinfo->depth != 16 || regno < 32) {
1702                         OUTREG(PALETTE_INDEX, pindex);
1703                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1704                 }
1705
1706                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1707         }
1708         if (regno < 16) {
1709                 switch (rinfo->depth) {
1710                 case 15:
1711                         ((u16 *) (info->pseudo_palette))[regno] =
1712                             (regno << 10) | (regno << 5) | regno;
1713                         break;
1714                 case 16:
1715                         ((u16 *) (info->pseudo_palette))[regno] =
1716                             (regno << 11) | (regno << 6) | regno;
1717                         break;
1718                 case 24:
1719                         ((u32 *) (info->pseudo_palette))[regno] =
1720                             (regno << 16) | (regno << 8) | regno;
1721                         break;
1722                 case 32:
1723                         i = (regno << 8) | regno;
1724                         ((u32 *) (info->pseudo_palette))[regno] =
1725                             (i << 16) | i;
1726                         break;
1727                 }
1728         }
1729         return 0;
1730 }
1731
1732
1733
1734 static void radeon_save_state (struct radeonfb_info *rinfo,
1735                                struct radeon_regs *save)
1736 {
1737         /* CRTC regs */
1738         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1739         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1740         save->dac_cntl = INREG(DAC_CNTL);
1741         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1742         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1743         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1744         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1745         save->crtc_pitch = INREG(CRTC_PITCH);
1746 #if defined(__BIG_ENDIAN)
1747         save->surface_cntl = INREG(SURFACE_CNTL);
1748 #endif
1749
1750         /* FP regs */
1751         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1752         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1753         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1754         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1755         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1756         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1757         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1758         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1759         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1760         save->tmds_crc = INREG(TMDS_CRC);
1761         save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1762         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1763 }
1764
1765
1766
1767 static int radeonfb_set_par (struct fb_info *info)
1768 {
1769         struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1770         struct fb_var_screeninfo *mode = &info->var;
1771         struct radeon_regs newmode;
1772         int hTotal, vTotal, hSyncStart, hSyncEnd,
1773             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1774         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1775         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1776         u32 dotClock = 1000000000 / mode->pixclock,
1777             sync, h_sync_pol, v_sync_pol;
1778         int freq = dotClock / 10;  /* x 100 */
1779         int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1780         int useable_precision, roff, ron;
1781         int min_bits, format = 0;
1782         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1783         int primary_mon = PRIMARY_MONITOR(rinfo);
1784         int depth = var_to_depth(mode);
1785
1786         rinfo->xres = mode->xres;
1787         rinfo->yres = mode->yres;
1788         rinfo->xres_virtual = mode->xres_virtual;
1789         rinfo->yres_virtual = mode->yres_virtual;
1790         rinfo->pixclock = mode->pixclock;
1791
1792         hSyncStart = mode->xres + mode->right_margin;
1793         hSyncEnd = hSyncStart + mode->hsync_len;
1794         hTotal = hSyncEnd + mode->left_margin;
1795
1796         vSyncStart = mode->yres + mode->lower_margin;
1797         vSyncEnd = vSyncStart + mode->vsync_len;
1798         vTotal = vSyncEnd + mode->upper_margin;
1799
1800         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1801                 if (rinfo->panel_xres < mode->xres)
1802                         rinfo->xres = mode->xres = rinfo->panel_xres;
1803                 if (rinfo->panel_yres < mode->yres)
1804                         rinfo->yres = mode->yres = rinfo->panel_yres;
1805
1806                 hTotal = mode->xres + rinfo->hblank;
1807                 hSyncStart = mode->xres + rinfo->hOver_plus;
1808                 hSyncEnd = hSyncStart + rinfo->hSync_width;
1809
1810                 vTotal = mode->yres + rinfo->vblank;
1811                 vSyncStart = mode->yres + rinfo->vOver_plus;
1812                 vSyncEnd = vSyncStart + rinfo->vSync_width;
1813         }
1814
1815         sync = mode->sync;
1816         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1817         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1818
1819         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1820                 hSyncStart, hSyncEnd, hTotal);
1821         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1822                 vSyncStart, vSyncEnd, vTotal);
1823
1824         hsync_wid = (hSyncEnd - hSyncStart) / 8;
1825         vsync_wid = vSyncEnd - vSyncStart;
1826         if (hsync_wid == 0)
1827                 hsync_wid = 1;
1828         else if (hsync_wid > 0x3f)      /* max */
1829                 hsync_wid = 0x3f;
1830
1831         if (vsync_wid == 0)
1832                 vsync_wid = 1;
1833         else if (vsync_wid > 0x1f)      /* max */
1834                 vsync_wid = 0x1f;
1835
1836         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1837         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1838
1839         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1840
1841         format = radeon_get_dstbpp(depth);
1842         bytpp = mode->bits_per_pixel >> 3;
1843
1844         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1845                 hsync_fudge = hsync_fudge_fp[format-1];
1846         else
1847                 hsync_fudge = hsync_adj_tab[format-1];
1848
1849         hsync_start = hSyncStart - 8 + hsync_fudge;
1850
1851         newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1852                                 (format << 8);
1853
1854         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1855                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1856                 if (mirror)
1857                         newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1858
1859                 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1860                                            CRTC_INTERLACE_EN);
1861         } else {
1862                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1863                                         CRTC_CRT_ON;
1864         }
1865
1866         newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1867                            DAC_8BIT_EN;
1868
1869         newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1870                                      (((mode->xres / 8) - 1) << 16));
1871
1872         newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1873                                         (hsync_wid << 16) | (h_sync_pol << 23));
1874
1875         newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1876                                     ((mode->yres - 1) << 16);
1877
1878         newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1879                                          (vsync_wid << 16) | (v_sync_pol  << 23));
1880
1881         newmode.crtc_pitch = (mode->xres_virtual >> 3);
1882         newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1883
1884 #if defined(__BIG_ENDIAN)
1885         /*
1886          * It looks like recent chips have a problem with SURFACE_CNTL,
1887          * setting SURF_TRANSLATION_DIS completely disables the
1888          * swapper as well, so we leave it unset now.
1889          */
1890         newmode.surface_cntl = 0;
1891
1892         /* Setup swapping on both apertures, though we currently
1893          * only use aperture 0, enabling swapper on aperture 1
1894          * won't harm
1895          */
1896         switch (mode->bits_per_pixel) {
1897                 case 16:
1898                         newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1899                         newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1900                         break;
1901                 case 24:
1902                 case 32:
1903                         newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1904                         newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1905                         break;
1906         }
1907 #endif
1908
1909         rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1910                         & ~(0x3f)) / 64;
1911
1912         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1913                 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1914         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1915                 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1916
1917         newmode.xres = mode->xres;
1918         newmode.yres = mode->yres;
1919
1920         rinfo->bpp = mode->bits_per_pixel;
1921         rinfo->depth = depth;
1922
1923         if (freq > rinfo->pll.ppll_max)
1924                 freq = rinfo->pll.ppll_max;
1925         if (freq*12 < rinfo->pll.ppll_min)
1926                 freq = rinfo->pll.ppll_min / 12;
1927
1928         {
1929                 struct {
1930                         int divider;
1931                         int bitvalue;
1932                 } *post_div,
1933                   post_divs[] = {
1934                         { 1,  0 },
1935                         { 2,  1 },
1936                         { 4,  2 },
1937                         { 8,  3 },
1938                         { 3,  4 },
1939                         { 16, 5 },
1940                         { 6,  6 },
1941                         { 12, 7 },
1942                         { 0,  0 },
1943                 };
1944
1945                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1946                         rinfo->pll_output_freq = post_div->divider * freq;
1947                         if (rinfo->pll_output_freq >= rinfo->pll.ppll_min  &&
1948                             rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1949                                 break;
1950                 }
1951
1952                 rinfo->post_div = post_div->divider;
1953                 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1954                                           rinfo->pll.ref_clk);
1955                 newmode.ppll_ref_div = rinfo->pll.ref_div;
1956                 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1957         }
1958         newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1959
1960 #ifdef CONFIG_ALL_PPC
1961         /* Gross hack for iBook with M7 until I find out a proper fix */
1962         if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1963                 newmode.ppll_div_3 = 0x000600ad;
1964 #endif /* CONFIG_ALL_PPC */
1965
1966         RTRACE("post div = 0x%x\n", rinfo->post_div);
1967         RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1968         RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1969
1970         /* DDA */
1971         vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1972                               rinfo->pll.ref_div * rinfo->post_div);
1973         xclk_freq = rinfo->pll.xclk;
1974
1975         xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1976
1977         min_bits = min_bits_req(xclk_per_trans);
1978         useable_precision = min_bits + 1;
1979
1980         xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1981                                            vclk_freq * mode->bits_per_pixel);
1982
1983         ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1984                2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1985                xclk_per_trans) << (11 - useable_precision);
1986         roff = xclk_per_trans_precise * (32 - 4);
1987
1988         RTRACE("ron = %d, roff = %d\n", ron, roff);
1989         RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
1990
1991         if ((ron + rinfo->ram.rloop) >= roff) {
1992                 printk("radeonfb: error ron out of range\n");
1993                 return -EINVAL;
1994         }
1995
1996         newmode.dda_config = (xclk_per_trans_precise |
1997                               (useable_precision << 16) |
1998                               (rinfo->ram.rloop << 20));
1999         newmode.dda_on_off = (ron << 16) | roff;
2000
2001         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2002                 unsigned int hRatio, vRatio;
2003
2004                 /* We force the pixel clock to be always enabled. Allowing it
2005                  * to be power managed during blanking would save power, but has
2006                  * nasty interactions with the 2D engine & sleep code that haven't
2007                  * been solved yet. --BenH
2008                  */
2009                 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2010
2011                 if (mode->xres > rinfo->panel_xres)
2012                         mode->xres = rinfo->panel_xres;
2013                 if (mode->yres > rinfo->panel_yres)
2014                         mode->yres = rinfo->panel_yres;
2015
2016                 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2017                                            << HORZ_PANEL_SHIFT);
2018                 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2019                                            << VERT_PANEL_SHIFT);
2020
2021                 if (mode->xres != rinfo->panel_xres) {
2022                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2023                                            rinfo->panel_xres);
2024                         newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2025                                                    (newmode.fp_horz_stretch &
2026                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2027                                                      HORZ_AUTO_RATIO_INC)));
2028                         newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2029                                                     HORZ_STRETCH_ENABLE);
2030                 }
2031                 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2032
2033                 if (mode->yres != rinfo->panel_yres) {
2034                         vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2035                                            rinfo->panel_yres);
2036                         newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2037                                                    (newmode.fp_vert_stretch &
2038                                                    (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2039                         newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2040                                                     VERT_STRETCH_ENABLE);
2041                 }
2042                 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2043
2044                 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2045                                        ~(FP_SEL_CRTC2 |
2046                                          FP_RMX_HVSYNC_CONTROL_EN |
2047                                          FP_DFP_SYNC_SEL |
2048                                          FP_CRT_SYNC_SEL |
2049                                          FP_CRTC_LOCK_8DOT |
2050                                          FP_USE_SHADOW_EN |
2051                                          FP_CRTC_USE_SHADOW_VEND |
2052                                          FP_CRT_SYNC_ALT));
2053
2054                 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2055                                         FP_CRTC_DONT_SHADOW_HEND);
2056
2057                 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2058                 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2059                 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2060                 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2061
2062                 if (primary_mon == MT_LCD) {
2063                         newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2064                         newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2065                 } else {
2066                         /* DFP */
2067                         newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2068                         newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2069                                                          ICHCSEL | TMDS_PLL_EN) &
2070                                                          ~(TMDS_PLLRST);
2071                         newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2072                 }
2073
2074                 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2075                                 (((mode->xres / 8) - 1) << 16));
2076                 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2077                                 ((mode->yres - 1) << 16);
2078                 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2079                                 (hsync_wid << 16) | (h_sync_pol << 23));
2080                 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2081                                 (vsync_wid << 16) | (v_sync_pol  << 23));
2082         }
2083
2084         /* do it! */
2085         if (!rinfo->asleep) {
2086                 radeon_write_mode (rinfo, &newmode);
2087                 /* (re)initialize the engine */
2088                 if (!noaccel)
2089                         radeon_engine_init (rinfo);
2090
2091         }
2092         /* Update fix */
2093         info->fix.line_length = rinfo->pitch*64;
2094         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2095
2096 #ifdef CONFIG_BOOTX_TEXT
2097         /* Update debug text engine */
2098         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2099                              rinfo->depth, rinfo->pitch*64);
2100 #endif
2101
2102         return 0;
2103 }
2104
2105
2106 static void radeon_write_mode (struct radeonfb_info *rinfo,
2107                                struct radeon_regs *mode)
2108 {
2109         int i;
2110         int primary_mon = PRIMARY_MONITOR(rinfo);
2111
2112         radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2113
2114
2115         if (rinfo->arch == RADEON_M6) {
2116                 for (i=0; i<8; i++)
2117                         OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2118         } else {
2119                 for (i=0; i<9; i++)
2120                         OUTREG(common_regs[i].reg, common_regs[i].val);
2121         }
2122
2123         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2124         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2125                 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2126         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2127         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2128         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2129         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2130         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2131         OUTREG(CRTC_OFFSET, 0);
2132         OUTREG(CRTC_OFFSET_CNTL, 0);
2133         OUTREG(CRTC_PITCH, mode->crtc_pitch);
2134
2135 #if defined(__BIG_ENDIAN)
2136         OUTREG(SURFACE_CNTL, mode->surface_cntl);
2137 #endif
2138
2139         while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2140                PPLL_DIV_SEL_MASK) {
2141                 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2142         }
2143
2144         OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2145
2146         while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2147                (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2148                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2149         }
2150
2151         while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2152                (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2153                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2154         }
2155
2156         while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2157                (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2158                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2159         }
2160
2161         OUTPLL(HTOTAL_CNTL, 0);
2162
2163         OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2164
2165 //      OUTREG(DDA_CONFIG, mode->dda_config);
2166 //      OUTREG(DDA_ON_OFF, mode->dda_on_off);
2167
2168         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2169                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2170                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2171                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2172                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2173                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2174                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2175                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2176                 OUTREG(TMDS_CRC, mode->tmds_crc);
2177                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2178
2179                 if (primary_mon == MT_LCD) {
2180                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
2181
2182                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2183                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2184
2185                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2186                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2187                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2188                         } else {
2189                                 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2190                                         udelay(1000);
2191                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2192                                 } else {
2193                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2194                                                LVDS_BLON);
2195                                         udelay(1000);
2196                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2197                                 }
2198                         }
2199                 }
2200         }
2201
2202         radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2203
2204         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2205
2206         return;
2207 }
2208
2209 static struct fb_ops radeonfb_ops = {
2210         .owner                  = THIS_MODULE,
2211         .fb_check_var           = radeonfb_check_var,
2212         .fb_set_par             = radeonfb_set_par,
2213         .fb_setcolreg           = radeonfb_setcolreg,
2214         .fb_pan_display         = radeonfb_pan_display,
2215         .fb_blank               = radeonfb_blank,
2216         .fb_ioctl               = radeonfb_ioctl,
2217 #if 0
2218         .fb_fillrect    = radeonfb_fillrect,
2219         .fb_copyarea    = radeonfb_copyarea,
2220         .fb_imageblit   = radeonfb_imageblit,
2221         .fb_rasterimg   = radeonfb_rasterimg,
2222 #else
2223         .fb_fillrect    = cfb_fillrect,
2224         .fb_copyarea    = cfb_copyarea,
2225         .fb_imageblit   = cfb_imageblit,
2226 #endif
2227         .fb_cursor      = soft_cursor,
2228 };
2229
2230
2231 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2232 {
2233         struct fb_info *info;
2234
2235         info = &rinfo->info;
2236
2237         info->currcon = -1;
2238         info->par = rinfo;
2239         info->pseudo_palette = rinfo->pseudo_palette;
2240         info->node = NODEV;
2241         info->flags = FBINFO_FLAG_DEFAULT;
2242         info->fbops = &radeonfb_ops;
2243         info->display_fg = NULL;
2244         info->screen_base = (char *)rinfo->fb_base;
2245
2246         /* Fill fix common fields */
2247         strncpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2248         info->fix.id[sizeof(info->fix.id) - 1] = '\0';
2249         info->fix.smem_start = rinfo->fb_base_phys;
2250         info->fix.smem_len = rinfo->video_ram;
2251         info->fix.type = FB_TYPE_PACKED_PIXELS;
2252         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2253         info->fix.xpanstep = 8;
2254         info->fix.ypanstep = 1;
2255         info->fix.ywrapstep = 0;
2256         info->fix.type_aux = 0;
2257         info->fix.mmio_start = rinfo->mmio_base_phys;
2258         info->fix.mmio_len = RADEON_REGSIZE;
2259         if (noaccel)
2260                 info->fix.accel = FB_ACCEL_NONE;
2261         else
2262                 info->fix.accel = FB_ACCEL_ATI_RADEON;
2263
2264         if (radeon_init_disp (rinfo) < 0)
2265                 return -1;
2266
2267         return 0;
2268 }
2269
2270
2271 #ifdef CONFIG_PMAC_BACKLIGHT
2272
2273 /* TODO: Dbl check these tables, we don't go up to full ON backlight
2274  * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2275  * having some more official numbers from ATI
2276  */
2277 static int backlight_conv_m6[] = {
2278         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2279         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2280 };
2281 static int backlight_conv_m7[] = {
2282         0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2283         0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2284 };
2285
2286 #define BACKLIGHT_LVDS_OFF
2287 #undef BACKLIGHT_DAC_OFF
2288
2289 /* We turn off the LCD completely instead of just dimming the backlight.
2290  * This provides some greater power saving and the display is useless
2291  * without backlight anyway.
2292  */
2293
2294 static int radeon_set_backlight_enable(int on, int level, void *data)
2295 {
2296         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2297         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2298         int* conv_table;
2299
2300         /* Pardon me for that hack... maybe some day we can figure
2301          * out in what direction backlight should work on a given
2302          * panel ?
2303          */
2304         if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2305                 && !machine_is_compatible("PowerBook4,3"))
2306                 conv_table = backlight_conv_m7;
2307         else
2308                 conv_table = backlight_conv_m6;
2309
2310         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2311         if (on && (level > BACKLIGHT_OFF)) {
2312                 lvds_gen_cntl |= LVDS_DIGON;
2313                 if (!lvds_gen_cntl & LVDS_ON) {
2314                         lvds_gen_cntl &= ~LVDS_BLON;
2315                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2316                         (void)INREG(LVDS_GEN_CNTL);
2317                         mdelay(10);
2318                         lvds_gen_cntl |= LVDS_BLON;
2319                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2320                 }
2321                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2322                 lvds_gen_cntl |= (conv_table[level] <<
2323                                   LVDS_BL_MOD_LEVEL_SHIFT);
2324                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2325                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2326         } else {
2327                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2328                 lvds_gen_cntl |= (conv_table[0] <<
2329                                   LVDS_BL_MOD_LEVEL_SHIFT);
2330                 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2331                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2332                 udelay(10);
2333                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2334         }
2335
2336         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2337         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2338         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2339
2340         return 0;
2341 }
2342
2343 static int radeon_set_backlight_level(int level, void *data)
2344 {
2345         return radeon_set_backlight_enable(1, level, data);
2346 }
2347 #endif /* CONFIG_PMAC_BACKLIGHT */
2348
2349
2350 #ifdef CONFIG_PMAC_PBOOK
2351
2352 static u32 dbg_clk;
2353
2354 /*
2355  * Radeon M6 Power Management code. This code currently only supports
2356  * the mobile chips, it's based from some informations provided by ATI
2357  * along with hours of tracing of MacOS drivers
2358  */
2359
2360 static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2361 {
2362         rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2363         rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2364         rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2365         rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2366         rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2367         rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2368         rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2369         rinfo->save_regs[7] = INPLL(MCLK_MISC);
2370         rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2371
2372         rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2373         rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2374         rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2375         rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2376         rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2377         rinfo->save_regs[14] = INREG(BUS_CNTL1);
2378         rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2379         rinfo->save_regs[16] = INREG(AGP_CNTL);
2380         rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2381         rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2382         rinfo->save_regs[19] = INREG(GPIOPAD_A);
2383         rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2384         rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2385         rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2386         rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2387         rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2388         rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2389         rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2390         rinfo->save_regs[27] = INREG(GPIO_MONID);
2391         rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2392
2393         rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2394         rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2395         rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2396         rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2397         rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2398 }
2399
2400 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2401 {
2402         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2403
2404         OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2405         OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2406         OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2407         OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2408         OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2409         OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2410         OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2411         OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2412
2413         OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2414         OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2415         OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2416         OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2417         OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2418         OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2419         OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2420         OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2421         OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2422         OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2423
2424         // wait VBL before that one  ?
2425         OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2426
2427         OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2428         OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2429         OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2430         OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2431         OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2432         OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2433         OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2434         OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2435         OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2436         OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2437 }
2438
2439 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2440 {
2441         OUTREG(GPIOPAD_MASK, 0x0001ffff);
2442         OUTREG(GPIOPAD_EN, 0x00000400);
2443         OUTREG(GPIOPAD_A, 0x00000000);
2444         OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2445         OUTREG(ZV_LCDPAD_EN, 0x00000000);
2446         OUTREG(ZV_LCDPAD_A, 0x00000000);
2447         OUTREG(GPIO_VGA_DDC, 0x00030000);
2448         OUTREG(GPIO_DVI_DDC, 0x00000000);
2449         OUTREG(GPIO_MONID, 0x00030000);
2450         OUTREG(GPIO_CRT2_DDC, 0x00000000);
2451 }
2452
2453 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2454 {
2455 //
2456 //      u32 reg;
2457 //
2458 //      OUTPLL(P2PLL_REF_DIV, 0x0c);
2459 //
2460 //      .../... figure out what macos does here
2461 }
2462
2463 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2464 {
2465         u32 reg;
2466
2467         reg  = INREG(BUS_CNTL1);
2468         reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2469         reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2470         OUTREG(BUS_CNTL1, reg);
2471
2472         reg  = INPLL(PLL_PWRMGT_CNTL);
2473         reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2474                 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2475         reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2476         reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2477         OUTPLL(PLL_PWRMGT_CNTL, reg);
2478
2479 //      reg  = INPLL(TV_PLL_CNTL1);
2480 //      reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2481 //      OUTPLL(TV_PLL_CNTL1, reg);
2482
2483         reg  = INREG(TV_DAC_CNTL);
2484         reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2485         reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2486                 TV_DAC_CNTL_BDACPD |
2487                 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2488         OUTREG(TV_DAC_CNTL, reg);
2489
2490         reg  = INREG(TMDS_TRANSMITTER_CNTL);
2491         reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2492         OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2493
2494 //      lvds_pll_cntl  = regr32(g, LVDS_PLL_CNTL);
2495 //      lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2496 //      lvds_pll_cntl |=  LVDS_PLL_CNTL__LVDS_PLL_RESET;
2497 //      regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2498
2499         reg = INREG(DAC_CNTL);
2500         reg &= ~DAC_CMP_EN;
2501         OUTREG(DAC_CNTL, reg);
2502
2503         reg = INREG(DAC_CNTL2);
2504         reg &= ~DAC2_CMP_EN;
2505         OUTREG(DAC_CNTL2, reg);
2506
2507         reg  = INREG(TV_DAC_CNTL);
2508         reg &= ~TV_DAC_CNTL_DETECT;
2509         OUTREG(TV_DAC_CNTL, reg);
2510 }
2511
2512 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2513 {
2514         /* This code is disabled. It does what is in the pm_init
2515          * function of the MacOS driver code ATI sent me. However,
2516          * it doesn't fix my sleep problem, and is causing other issues
2517          * on wakeup (bascially the machine dying when switching consoles
2518          * I haven't had time to investigate this yet
2519          */
2520 #if 0
2521         u32 disp_misc_cntl;
2522         u32 disp_pwr_man;
2523         u32 temp;
2524
2525         // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2526         // TCLK and TEST_MODE to 0
2527         temp = INPLL(CLK_PWRMGT_CNTL);
2528         OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2529
2530         // Turn on Power Management
2531         temp = INPLL(CLK_PWRMGT_CNTL);
2532         OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2533
2534         // Turn off display clock if using mobile chips
2535         temp = INPLL(CLK_PWRMGT_CNTL);
2536         OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2537
2538         // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2539         temp = INPLL(VCLK_ECP_CNTL);
2540         OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2541
2542         // Force ECP_FORCE_ON to 1
2543         temp = INPLL(VCLK_ECP_CNTL);
2544         OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2545
2546         // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2547         temp = INPLL(PIXCLKS_CNTL);
2548         OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2549
2550         // Forcing SCLK_CNTL to ON
2551         OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2552
2553         // Set PM control over XTALIN pad
2554         temp = INPLL(CLK_PIN_CNTL);
2555         OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2556
2557         // Force MCLK and YCLK and MC as dynamic
2558         temp = INPLL(MCLK_CNTL);
2559         OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2560
2561         // PLL_TURNOFF
2562         temp = INPLL(PLL_PWRMGT_CNTL);
2563         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2564
2565         // set MOBILE_SU to 1 if M6 or DDR64 is detected
2566         temp = INPLL(PLL_PWRMGT_CNTL);
2567         OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2568
2569         // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2570 //      temp = INPLL(PLL_PWRMGT_CNTL);
2571 //      OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2572         temp = INPLL(PLL_PWRMGT_CNTL);
2573         OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2574
2575         // set DISP_MISC_CNTL register
2576         disp_misc_cntl = INREG(DISP_MISC_CNTL);
2577         disp_misc_cntl &= ~(    DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2578                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2579                                 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2580                                 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2581                                 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2582                                 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2583                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2584                                 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2585                                 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2586                                 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2587                                 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2588                                 DISP_MISC_CNTL_SOFT_RESET_TV);
2589         OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2590
2591         // set DISP_PWR_MAN register
2592         disp_pwr_man = INREG(DISP_PWR_MAN);
2593         // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2594         disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2595                     DISP_PWR_MAN_TV_ENABLE_RST |
2596  //                 DISP_PWR_MAN_AUTO_PWRUP_EN |
2597                     DISP_PWR_MAN_DISP_D3_GRPH_RST |
2598                     DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2599                     DISP_PWR_MAN_DISP_D3_OV0_RST |
2600                     DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2601                     DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2602                     DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2603         disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2604                     DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2605                     DISP_PWR_MAN_DISP_D3_RST |
2606                     DISP_PWR_MAN_DISP_D3_REG_RST);
2607         OUTREG(DISP_PWR_MAN, disp_pwr_man);
2608
2609         // clau - 10.24.2000
2610         // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2611         // - add in setting for AGP_CNTL  b7:0 = 0x20
2612         // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2613
2614         // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2615         // requres -mobile flag
2616         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2617         OUTREG(BUS_CNTL1,  INREG(BUS_CNTL1) | 0x80000000);
2618         OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2619         OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2620
2621         // yulee - 12.12.2000
2622         // A12 only
2623         // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2624         // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2625         // only on mobile platform
2626         OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2627
2628         // yulee -12.12.2000
2629         // AGPCLK_VALID@BUS_CNTL1 = 1
2630         // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2631         // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2632         // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2633         // only on mobile platform
2634         OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2635         OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2636         OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2637
2638         mdelay(100);
2639 #endif
2640
2641         /* Disable CRTCs */
2642         OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2643         OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2644         (void)INREG(CRTC2_GEN_CNTL);
2645         mdelay(17);
2646 }
2647
2648 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2649 {
2650         u16 pwr_cmd;
2651
2652         if (!rinfo->pm_reg)
2653                 return;
2654
2655         /* Set the chip into appropriate suspend mode (we use D2,
2656          * D3 would require a compete re-initialization of the chip,
2657          * including PCI config registers, clocks, AGP conf, ...)
2658          */
2659         if (suspend) {
2660                 /* According to ATI, we should program V2CLK here, I have
2661                  * to verify what's up exactly
2662                  */
2663                 /* Save some registers */
2664                 radeon_pm_save_regs(rinfo);
2665
2666                 /* Check that on M7 too, might work might not. M7 may also
2667                  * need explicit enabling of PM
2668                  */
2669                 if (rinfo->arch == RADEON_M6) {
2670                         /* Program V2CLK */
2671                         radeon_pm_program_v2clk(rinfo);
2672
2673                         /* Disable IO PADs */
2674                         radeon_pm_disable_iopad(rinfo);
2675
2676                         /* Set low current */
2677                         radeon_pm_low_current(rinfo);
2678
2679                         /* Prepare chip for power management */
2680                         radeon_pm_setup_for_suspend(rinfo);
2681
2682                         /* Reset the MDLL */
2683                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2684                         (void)INPLL(MDLL_RDCKA);
2685                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2686                         (void)INPLL(MDLL_RDCKA);
2687                 }
2688
2689                 /* Switch PCI power managment to D2. */
2690                 for (;;) {
2691                         pci_read_config_word(
2692                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2693                                 &pwr_cmd);
2694                         if (pwr_cmd & 2)
2695                                 break;
2696                         pci_write_config_word(
2697                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2698                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2699                         mdelay(500);
2700                 }
2701         } else {
2702                 /* Switch back PCI powermanagment to D0 */
2703                 mdelay(200);
2704                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2705                 mdelay(500);
2706
2707                 dbg_clk = INPLL(1);
2708
2709                 /* Do we need that on M7 ? */
2710                 if (rinfo->arch == RADEON_M6) {
2711                         /* Restore the MDLL */
2712                         OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2713                         (void)INPLL(MDLL_CKO);
2714                 }
2715
2716                 /* Restore some registers */
2717                 radeon_pm_restore_regs(rinfo);
2718         }
2719 }
2720
2721 /*
2722  * Save the contents of the framebuffer when we go to sleep,
2723  * and restore it when we wake up again.
2724  */
2725
2726 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2727 {
2728         struct radeonfb_info *rinfo;
2729
2730         for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2731                 struct fb_fix_screeninfo fix;
2732                 int nb;
2733                 struct display *disp;
2734
2735                 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2736
2737                 switch (rinfo->arch) {
2738                         case RADEON_M6:
2739                         case RADEON_M7:
2740                         case RADEON_M9:
2741                                 break;
2742                         default:
2743                                 return PBOOK_SLEEP_REFUSE;
2744                 }
2745
2746                 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2747                 nb = fb_display[fg_console].var.yres * fix.line_length;
2748
2749                 switch (when) {
2750                         case PBOOK_SLEEP_NOW:
2751                                 acquire_console_sem();
2752                                 disp->dispsw = &fbcon_dummy;
2753
2754                                 if (!noaccel) {
2755                                         /* Make sure engine is reset */
2756                                         radeon_engine_reset();
2757                                         radeon_engine_idle();
2758                                 }
2759
2760                                 /* Blank display and LCD */
2761                                 radeonfb_blank(VESA_POWERDOWN+1,
2762                                                (struct fb_info *)rinfo);
2763
2764                                 /* Sleep */
2765                                 rinfo->asleep = 1;
2766                                 radeon_set_suspend(rinfo, 1);
2767                                 release_console_sem();
2768
2769                                 break;
2770                         case PBOOK_WAKE:
2771                                 acquire_console_sem();
2772                                 /* Wakeup */
2773                                 radeon_set_suspend(rinfo, 0);
2774
2775                                 if (!noaccel)
2776                                         radeon_engine_init(rinfo);
2777                                 rinfo->asleep = 0;
2778                                 radeon_set_dispsw(rinfo, disp);
2779                                 radeon_load_video_mode(rinfo, &disp->var);
2780                                 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2781                                                 (struct fb_info *)rinfo);
2782
2783                                 radeonfb_blank(0, (struct fb_info *)rinfo);
2784                                 release_console_sem();
2785                                 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2786                                 break;
2787                 }
2788         }
2789
2790         return PBOOK_SLEEP_OK;
2791 }
2792
2793 #endif /* CONFIG_PMAC_PBOOK */
2794
2795 static int radeonfb_pci_register (struct pci_dev *pdev,
2796                                   const struct pci_device_id *ent)
2797 {
2798         struct radeonfb_info *rinfo;
2799         struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2800         u32 tmp;
2801
2802         RTRACE("radeonfb_pci_register BEGIN\n");
2803
2804         /* Enable device in PCI config */
2805         if (pci_enable_device(pdev) != 0) {
2806                 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2807                 return -ENODEV;
2808         }
2809
2810         rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2811         if (!rinfo) {
2812                 printk ("radeonfb: could not allocate memory\n");
2813                 return -ENODEV;
2814         }
2815
2816         memset (rinfo, 0, sizeof (struct radeonfb_info));
2817         //info = &rinfo->info;
2818         rinfo->pdev = pdev;
2819         strcpy(rinfo->name, rci->name);
2820         rinfo->arch = rci->arch;
2821
2822         /* Set base addrs */
2823         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2824         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2825
2826         /* request the mem regions */
2827         if (!request_mem_region (rinfo->fb_base_phys,
2828                                  pci_resource_len(pdev, 0), "radeonfb")) {
2829                 printk ("radeonfb: cannot reserve FB region\n");
2830                 kfree (rinfo);
2831                 return -ENODEV;
2832         }
2833
2834         if (!request_mem_region (rinfo->mmio_base_phys,
2835                                  pci_resource_len(pdev, 2), "radeonfb")) {
2836                 printk ("radeonfb: cannot reserve MMIO region\n");
2837                 release_mem_region (rinfo->fb_base_phys,
2838                                     pci_resource_len(pdev, 0));
2839                 kfree (rinfo);
2840                 return -ENODEV;
2841         }
2842
2843         /* map the regions */
2844         rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
2845                                                     RADEON_REGSIZE);
2846         if (!rinfo->mmio_base) {
2847                 printk ("radeonfb: cannot map MMIO\n");
2848                 release_mem_region (rinfo->mmio_base_phys,
2849                                     pci_resource_len(pdev, 2));
2850                 release_mem_region (rinfo->fb_base_phys,
2851                                     pci_resource_len(pdev, 0));
2852                 kfree (rinfo);
2853                 return -ENODEV;
2854         }
2855
2856         rinfo->chipset = pdev->device;
2857
2858         switch (rinfo->arch) {
2859                 case RADEON_R100:
2860                         rinfo->hasCRTC2 = 0;
2861                         break;
2862                 default:
2863                         /* all the rest have it */
2864                         rinfo->hasCRTC2 = 1;
2865                         break;
2866         }
2867 #if 0
2868         if (rinfo->arch == RADEON_M7) {
2869                 /*
2870                  * Noticed some errors in accel with M7, will have to work these out...
2871                  */
2872                 noaccel = 1;
2873         }
2874 #endif
2875         if (mirror)
2876                 printk("radeonfb: mirroring display to CRT\n");
2877
2878         /* framebuffer size */
2879         tmp = INREG(CONFIG_MEMSIZE);
2880
2881         /* mem size is bits [28:0], mask off the rest */
2882         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2883
2884         /* ram type */
2885         tmp = INREG(MEM_SDRAM_MODE_REG);
2886         switch ((MEM_CFG_TYPE & tmp) >> 30) {
2887                 case 0:
2888                         /* SDR SGRAM (2:1) */
2889                         strcpy(rinfo->ram_type, "SDR SGRAM");
2890                         rinfo->ram.ml = 4;
2891                         rinfo->ram.mb = 4;
2892                         rinfo->ram.trcd = 1;
2893                         rinfo->ram.trp = 2;
2894                         rinfo->ram.twr = 1;
2895                         rinfo->ram.cl = 2;
2896                         rinfo->ram.loop_latency = 16;
2897                         rinfo->ram.rloop = 16;
2898
2899                         break;
2900                 case 1:
2901                         /* DDR SGRAM */
2902                         strcpy(rinfo->ram_type, "DDR SGRAM");
2903                         rinfo->ram.ml = 4;
2904                         rinfo->ram.mb = 4;
2905                         rinfo->ram.trcd = 3;
2906                         rinfo->ram.trp = 3;
2907                         rinfo->ram.twr = 2;
2908                         rinfo->ram.cl = 3;
2909                         rinfo->ram.tr2w = 1;
2910                         rinfo->ram.loop_latency = 16;
2911                         rinfo->ram.rloop = 16;
2912
2913                         break;
2914                 default:
2915                         /* 64-bit SDR SGRAM */
2916                         strcpy(rinfo->ram_type, "SDR SGRAM 64");
2917                         rinfo->ram.ml = 4;
2918                         rinfo->ram.mb = 8;
2919                         rinfo->ram.trcd = 3;
2920                         rinfo->ram.trp = 3;
2921                         rinfo->ram.twr = 1;
2922                         rinfo->ram.cl = 3;
2923                         rinfo->ram.tr2w = 1;
2924                         rinfo->ram.loop_latency = 17;
2925                         rinfo->ram.rloop = 17;
2926
2927                         break;
2928         }
2929
2930         rinfo->bios_seg = radeon_find_rom(rinfo);
2931         radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2932
2933         /*
2934          * Hack to get around some busted production M6's
2935          * reporting no ram
2936          */
2937         if (rinfo->video_ram == 0) {
2938                 switch (pdev->device) {
2939                         case PCI_DEVICE_ID_ATI_RADEON_LY:
2940                         case PCI_DEVICE_ID_ATI_RADEON_LZ:
2941                                 rinfo->video_ram = 8192 * 1024;
2942                                 break;
2943                         default:
2944                                 break;
2945                 }
2946         }
2947
2948
2949         RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2950
2951 #if !defined(__powerpc__)
2952         radeon_get_moninfo(rinfo);
2953 #else
2954         switch (pdev->device) {
2955                 case PCI_DEVICE_ID_ATI_RADEON_LW:
2956                 case PCI_DEVICE_ID_ATI_RADEON_LX:
2957                 case PCI_DEVICE_ID_ATI_RADEON_LY:
2958                 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2959                         rinfo->dviDisp_type = MT_LCD;
2960                         break;
2961                 default:
2962                         radeon_get_moninfo(rinfo);
2963                         break;
2964         }
2965 #endif
2966
2967         radeon_get_EDID(rinfo);
2968
2969         if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2970             (rinfo->crtDisp_type == MT_DFP)) {
2971                 if (!radeon_get_dfpinfo(rinfo)) {
2972                         iounmap ((void*)rinfo->mmio_base);
2973                         release_mem_region (rinfo->mmio_base_phys,
2974                                             pci_resource_len(pdev, 2));
2975                         release_mem_region (rinfo->fb_base_phys,
2976                                             pci_resource_len(pdev, 0));
2977                         kfree (rinfo);
2978                         return -ENODEV;
2979                 }
2980         }
2981
2982         rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
2983                                                   rinfo->video_ram);
2984         if (!rinfo->fb_base) {
2985                 printk ("radeonfb: cannot map FB\n");
2986                 iounmap ((void*)rinfo->mmio_base);
2987                 release_mem_region (rinfo->mmio_base_phys,
2988                                     pci_resource_len(pdev, 2));
2989                 release_mem_region (rinfo->fb_base_phys,
2990                                     pci_resource_len(pdev, 0));
2991                 kfree (rinfo);
2992                 return -ENODEV;
2993         }
2994
2995         /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
2996          * driver setup here.
2997          *
2998          * On PPC, OF based cards setup the internal memory
2999          * mapping in strange ways. We change it so that the
3000          * framebuffer is mapped at 0 and given half of the card's
3001          * address space (2Gb). AGP is mapped high (0xe0000000) and
3002          * can use up to 512Mb. Once DRI is fully implemented, we
3003          * will have to setup the PCI remapper to remap the agp_special_page
3004          * memory page somewhere between those regions so that the card
3005          * use a normal PCI bus master cycle to access the ring read ptr.
3006          * --BenH.
3007          */
3008 #ifdef CONFIG_ALL_PPC
3009         if (rinfo->hasCRTC2)
3010                 OUTREG(CRTC2_GEN_CNTL,
3011                         (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
3012         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
3013         OUTREG(MC_FB_LOCATION, 0x7fff0000);
3014         OUTREG(MC_AGP_LOCATION, 0xffffe000);
3015         OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3016         if (rinfo->hasCRTC2)
3017                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3018         OUTREG(SRC_OFFSET, 0x00000000);
3019         OUTREG(DST_OFFSET, 0x00000000);
3020         mdelay(10);
3021         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3022 #endif /* CONFIG_ALL_PPC */
3023
3024         /* save current mode regs before we switch into the new one
3025          * so we can restore this upon __exit
3026          */
3027         radeon_save_state (rinfo, &rinfo->init_state);
3028
3029         if (!noaccel) {
3030                 /* initialize the engine */
3031                 radeon_engine_init (rinfo);
3032         }
3033
3034         /* set all the vital stuff */
3035         radeon_set_fbinfo (rinfo);
3036
3037         pci_set_drvdata(pdev, rinfo);
3038         rinfo->next = board_list;
3039         board_list = rinfo;
3040
3041         if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3042                 printk ("radeonfb: could not register framebuffer\n");
3043                 iounmap ((void*)rinfo->fb_base);
3044                 iounmap ((void*)rinfo->mmio_base);
3045                 release_mem_region (rinfo->mmio_base_phys,
3046                                     pci_resource_len(pdev, 2));
3047                 release_mem_region (rinfo->fb_base_phys,
3048                                     pci_resource_len(pdev, 0));
3049                 kfree (rinfo);
3050                 return -ENODEV;
3051         }
3052
3053 #ifdef CONFIG_MTRR
3054         rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3055                                                  rinfo->video_ram,
3056                                                  MTRR_TYPE_WRCOMB, 1);
3057 #endif
3058
3059 #ifdef CONFIG_PMAC_BACKLIGHT
3060         if (rinfo->dviDisp_type == MT_LCD)
3061                 register_backlight_controller(&radeon_backlight_controller,
3062                                               rinfo, "ati");
3063 #endif
3064
3065 #ifdef CONFIG_PMAC_PBOOK
3066         if (rinfo->dviDisp_type == MT_LCD) {
3067                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3068                 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3069         }
3070 #endif
3071
3072         printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3073                 (rinfo->video_ram/(1024*1024)));
3074
3075         if (rinfo->hasCRTC2) {
3076                 printk("radeonfb: DVI port %s monitor connected\n",
3077                         GET_MON_NAME(rinfo->dviDisp_type));
3078                 printk("radeonfb: CRT port %s monitor connected\n",
3079                         GET_MON_NAME(rinfo->crtDisp_type));
3080         } else {
3081                 printk("radeonfb: CRT port %s monitor connected\n",
3082                         GET_MON_NAME(rinfo->crtDisp_type));
3083         }
3084
3085         RTRACE("radeonfb_pci_register END\n");
3086
3087         return 0;
3088 }
3089
3090
3091
3092 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3093 {
3094         struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3095
3096         if (!rinfo)
3097                 return;
3098
3099         /* restore original state
3100          *
3101          * Doesn't quite work yet, possibly because of the PPC hacking
3102          * I do on startup, disable for now. --BenH
3103          */
3104         radeon_write_mode (rinfo, &rinfo->init_state);
3105
3106 #ifdef CONFIG_MTRR
3107         if (rinfo->mtrr_hdl >= 0)
3108                 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3109 #endif
3110
3111         unregister_framebuffer ((struct fb_info *) rinfo);
3112
3113         iounmap ((void*)rinfo->mmio_base);
3114         iounmap ((void*)rinfo->fb_base);
3115
3116         release_mem_region (rinfo->mmio_base_phys,
3117                             pci_resource_len(pdev, 2));
3118         release_mem_region (rinfo->fb_base_phys,
3119                             pci_resource_len(pdev, 0));
3120
3121         kfree (rinfo);
3122 }
3123
3124
3125 static struct pci_driver radeonfb_driver = {
3126         .name           = "radeonfb",
3127         .id_table       = radeonfb_pci_table,
3128         .probe          = radeonfb_pci_register,
3129         .remove         = __devexit_p(radeonfb_pci_unregister),
3130 };
3131
3132
3133 int __init radeonfb_init (void)
3134 {
3135         return pci_module_init (&radeonfb_driver);
3136 }
3137
3138
3139 void __exit radeonfb_exit (void)
3140 {
3141         pci_unregister_driver (&radeonfb_driver);
3142 }
3143
3144
3145 int __init radeonfb_setup (char *options)
3146 {
3147         char *this_opt;
3148
3149         if (!options || !*options)
3150                 return 0;
3151
3152         while ((this_opt = strsep (&options, ",")) != NULL) {
3153                 if (!*this_opt)
3154                         continue;
3155                 if (!strncmp(this_opt, "noaccel", 7)) {
3156                         noaccel = 1;
3157                 } else if (!strncmp(this_opt, "mirror", 6)) {
3158                         mirror = 1;
3159                 } else if (!strncmp(this_opt, "dfp", 3)) {
3160                         force_dfp = 1;
3161                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3162                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3163                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3164                         nomtrr = 1;
3165                 } else
3166                         mode_option = this_opt;
3167         }
3168
3169         return 0;
3170 }
3171
3172 #ifdef MODULE
3173 module_init(radeonfb_init);
3174 module_exit(radeonfb_exit);
3175 #endif
3176
3177
3178 MODULE_AUTHOR("Ani Joshi");
3179 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3180 MODULE_LICENSE("GPL");