linux-2.4.20-nforce2.patch

   1 diff --unified --recursive --new-file linux/drivers/char/agp/agp.h linux-2.4.21-pr7/drivers/char/agp/agp.h
   2 --- linux/drivers/char/agp/agp.h        2003-04-13 22:25:59.000000000 +0200
   3 +++ linux-2.4.21-pr7/drivers/char/agp/agp.h     2003-05-06 20:56:58.000000000 +0200
   4 @@ -271,6 +271,9 @@
   5  #ifndef PCI_DEVICE_ID_AL_M1671_0
   6  #define PCI_DEVICE_ID_AL_M1671_0       0x1671
   7  #endif
   8 +#ifndef PCI_DEVICE_ID_NV_NFORCE2_0
   9 +#define PCI_DEVICE_ID_NV_NFORCE2_0     0x01e0
  10 +#endif
  11
  12  /* intel register */
  13  #define INTEL_APBASE    0x10
  14 @@ -412,6 +415,17 @@
  15  #define SVWRKS_POSTFLUSH  0x14
  16  #define SVWRKS_DIRFLUSH   0x0c
  17
  18 +/* NVidia registers */
  19 +#define NVIDIA_0_APBASE                0x10
  20 +#define NVIDIA_0_APSIZE                0x80
  21 +#define NVIDIA_1_WBC           0xf0
  22 +#define NVIDIA_2_GARTCTRL      0xd0
  23 +#define NVIDIA_2_APBASE                0xd8
  24 +#define NVIDIA_2_APLIMIT       0xdc
  25 +#define NVIDIA_2_ATTBASE(i)    (0xe0 + (i) * 4)
  26 +#define NVIDIA_3_APBASE                0x50
  27 +#define NVIDIA_3_APLIMIT       0x54
  28 +
  29  /* HP ZX1 SBA registers */
  30  #define HP_ZX1_CTRL            0x200
  31  #define HP_ZX1_IBASE           0x300
  32 diff --unified --recursive --new-file linux/drivers/char/agp/agpgart_be.c linux-2.4.21-pr7/drivers/char/agp/agpgart_be.c
  33 --- linux/drivers/char/agp/agpgart_be.c 2003-04-13 22:25:59.000000000 +0200
  34 +++ linux-2.4.21-pr7/drivers/char/agp/agpgart_be.c      2003-05-06 20:56:58.000000000 +0200
  35 @@ -3418,7 +3418,7 @@
  36  } serverworks_private;
  37
  38  static int serverworks_create_page_map(serverworks_page_map *page_map)
  39 -{
  40 +{
  41         int i;
  42         int err = 0;
  43
  44 @@ -4003,6 +4003,256 @@
  45
  46  #endif /* CONFIG_AGP_SWORKS */
  47
  48 +#ifdef CONFIG_AGP_NV
  49 +
  50 +static aper_size_info_8 nvidia_generic_sizes[5] =
  51 +{
  52 +       {512, 131072, 7, 0},
  53 +       {256, 65536, 6, 8},
  54 +       {128, 32768, 5, 12},
  55 +       {64, 16384, 4, 14},
  56 +       /* The 32M mode still requires a 64k gatt */
  57 +       {32, 16384, 4, 15}
  58 +};
  59 +
  60 +static gatt_mask nvidia_generic_masks[] =
  61 +{
  62 +       {0x00000001, 0}
  63 +};
  64 +
  65 +static struct _nvidia_private {
  66 +       struct pci_dev *dev_1;
  67 +       struct pci_dev *dev_2;
  68 +       struct pci_dev *dev_3;
  69 +       volatile u32 *aperture;
  70 +       int num_active_entries;
  71 +       off_t pg_offset;
  72 +       u32 wbc_mask;
  73 +} nvidia_private;
  74 +
  75 +static int nvidia_fetch_size(void)
  76 +{
  77 +       int i;
  78 +       u8 size_value;
  79 +       aper_size_info_8 *values;
  80 +
  81 +       pci_read_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE, &size_value);
  82 +       size_value &= 0x0f;
  83 +       values = A_SIZE_8(agp_bridge.aperture_sizes);
  84 +
  85 +       for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
  86 +               if (size_value == values[i].size_value) {
  87 +                       agp_bridge.previous_size =
  88 +                               agp_bridge.current_size = (void *) (values + i);
  89 +                       agp_bridge.aperture_size_idx = i;
  90 +                       return values[i].size;
  91 +               }
  92 +       }
  93 +
  94 +       return 0;
  95 +}
  96 +
  97 +static int nvidia_configure(void)
  98 +{
  99 +       int i, num_dirs;
 100 +       u32 apbase, aplimit;
 101 +       aper_size_info_8 *current_size;
 102 +       u32 temp;
 103 +
 104 +       current_size = A_SIZE_8(agp_bridge.current_size);
 105 +
 106 +       /* aperture size */
 107 +       pci_write_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE,
 108 +               current_size->size_value);
 109 +
 110 +    /* address to map to */
 111 +       pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APBASE, &apbase);
 112 +       apbase &= PCI_BASE_ADDRESS_MEM_MASK;
 113 +       agp_bridge.gart_bus_addr = apbase;
 114 +       aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
 115 +       pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
 116 +       pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
 117 +       pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
 118 +       pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
 119 +
 120 +       /* directory size is 64k */
 121 +       num_dirs = current_size->size / 64;
 122 +       nvidia_private.num_active_entries = current_size->num_entries;
 123 +       nvidia_private.pg_offset = 0;
 124 +       if (num_dirs == 0) {
 125 +               num_dirs = 1;
 126 +               nvidia_private.num_active_entries /= (64 / current_size->size);
 127 +               nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
 128 +                       ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
 129 +       }
 130 +
 131 +       /* attbase */
 132 +       for(i = 0; i < 8; i++) {
 133 +               pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
 134 +                       (agp_bridge.gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
 135 +       }
 136 +
 137 +       /* gtlb control */
 138 +       pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
 139 +       pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
 140 +
 141 +       /* gart control */
 142 +       pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, &temp);
 143 +       pci_write_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, temp | 0x100);
 144 +
 145 +       /* map aperture */
 146 +       nvidia_private.aperture =
 147 +               (volatile u32 *) ioremap(apbase, 33 * PAGE_SIZE);
 148 +
 149 +       return 0;
 150 +}
 151 +
 152 +static void nvidia_cleanup(void)
 153 +{
 154 +       aper_size_info_8 *previous_size;
 155 +       u32 temp;
 156 +
 157 +       /* gart control */
 158 +       pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, &temp);
 159 +       pci_write_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, temp & ~(0x100));
 160 +
 161 +       /* gtlb control */
 162 +       pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
 163 +       pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
 164 +
 165 +       /* unmap aperture */
 166 +       iounmap((void *) nvidia_private.aperture);
 167 +
 168 +       /* restore previous aperture size */
 169 +       previous_size = A_SIZE_8(agp_bridge.previous_size);
 170 +       pci_write_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE,
 171 +               previous_size->size_value);
 172 +}
 173 +
 174 +static void nvidia_tlbflush(agp_memory * mem)
 175 +{
 176 +       unsigned long end;
 177 +       u32 wbc_reg, temp;
 178 +       int i;
 179 +
 180 +       /* flush chipset */
 181 +       if (nvidia_private.wbc_mask) {
 182 +               pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
 183 +               wbc_reg |= nvidia_private.wbc_mask;
 184 +               pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
 185 +
 186 +               end = jiffies + 3*HZ;
 187 +               do {
 188 +                       pci_read_config_dword(nvidia_private.dev_1,
 189 +                                       NVIDIA_1_WBC, &wbc_reg);
 190 +                       if ((signed)(end - jiffies) <= 0) {
 191 +                               printk(KERN_ERR
 192 +                                   "TLB flush took more than 3 seconds.\n");
 193 +                       }
 194 +               } while (wbc_reg & nvidia_private.wbc_mask);
 195 +       }
 196 +
 197 +       /* flush TLB entries */
 198 +       for(i = 0; i < 32 + 1; i++)
 199 +               temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
 200 +       for(i = 0; i < 32 + 1; i++)
 201 +               temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
 202 +}
 203 +
 204 +static unsigned long nvidia_mask_memory(unsigned long addr, int type)
 205 +{
 206 +       /* Memory type is ignored */
 207 +       return addr | agp_bridge.masks[0].mask;
 208 +}
 209 +
 210 +#if 0
 211 +extern int agp_memory_reserved;
 212 +
 213 +static int nvidia_insert_memory(agp_memory * mem, off_t pg_start, int type)
 214 +{
 215 +       int i, j;
 216 +
 217 +       if ((type != 0) || (mem->type != 0))
 218 +               return -EINVAL;
 219 +
 220 +       if ((pg_start + mem->page_count) >
 221 +               (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
 222 +               return -EINVAL;
 223 +
 224 +       for(j = pg_start; j < (pg_start + mem->page_count); j++) {
 225 +               if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[nvidia_private.pg_offset + j]))
 226 +                       return -EBUSY;
 227 +       }
 228 +
 229 +       if (mem->is_flushed == FALSE) {
 230 +               global_cache_flush();
 231 +               mem->is_flushed = TRUE;
 232 +       }
 233 +       for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
 234 +               agp_bridge->gatt_table[nvidia_private.pg_offset + j] = mem->memory[i];
 235 +
 236 +       agp_bridge->tlb_flush(mem);
 237 +       return 0;
 238 +}
 239 +
 240 +static int nvidia_remove_memory(agp_memory * mem, off_t pg_start, int type)
 241 +{
 242 +       int i;
 243 +
 244 +       if ((type != 0) || (mem->type != 0))
 245 +               return -EINVAL;
 246 +
 247 +       for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 248 +               agp_bridge->gatt_table[nvidia_private.pg_offset + i] =
 249 +                   (unsigned long) agp_bridge->scratch_page;
 250 +       }
 251 +
 252 +       agp_bridge->tlb_flush(mem);
 253 +       return 0;
 254 +}
 255 +#endif
 256 +
 257 +static int __init nvidia_generic_setup (struct pci_dev *pdev)
 258 +{
 259 +       nvidia_private.dev_1 =
 260 +               pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
 261 +       nvidia_private.dev_2 =
 262 +               pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
 263 +       nvidia_private.dev_3 =
 264 +               pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
 265 +       nvidia_private.wbc_mask = 0x80000000;
 266 +       agp_bridge.masks = nvidia_generic_masks;
 267 +       agp_bridge.aperture_sizes = (void *) nvidia_generic_sizes;
 268 +       agp_bridge.size_type = U8_APER_SIZE;
 269 +       agp_bridge.num_aperture_sizes = 5;
 270 +       agp_bridge.needs_scratch_page = FALSE;
 271 +       agp_bridge.configure = nvidia_configure;
 272 +       agp_bridge.fetch_size = nvidia_fetch_size;
 273 +       agp_bridge.cleanup = nvidia_cleanup;
 274 +       agp_bridge.tlb_flush = nvidia_tlbflush;
 275 +       agp_bridge.mask_memory = nvidia_mask_memory;
 276 +       agp_bridge.agp_enable = agp_generic_agp_enable;
 277 +       agp_bridge.cache_flush = global_cache_flush;
 278 +       agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
 279 +       agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
 280 +       agp_bridge.insert_memory = agp_generic_insert_memory;
 281 +       agp_bridge.remove_memory = agp_generic_remove_memory;
 282 +       agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
 283 +       agp_bridge.free_by_type = agp_generic_free_by_type;
 284 +       agp_bridge.agp_alloc_page = agp_generic_alloc_page;
 285 +       agp_bridge.agp_destroy_page = agp_generic_destroy_page;
 286 +       agp_bridge.suspend = agp_generic_suspend;
 287 +       agp_bridge.resume = agp_generic_resume;
 288 +       agp_bridge.cant_use_aperture = 0;
 289 +       agp_bridge.dev_private_data = &nvidia_private;
 290 +
 291 +       return 0;
 292 +
 293 +       (void) pdev; /* unused */
 294 +}
 295 +
 296 +#endif /* CONFIG_AGP_NV */
 297 +
 298  #ifdef CONFIG_AGP_HP_ZX1
 299
 300  #ifndef log2
 301 @@ -4702,6 +4952,15 @@
 302                 via_generic_setup },
 303  #endif /* CONFIG_AGP_VIA */
 304
 305 +#ifdef CONFIG_AGP_NV
 306 +       { PCI_DEVICE_ID_NV_NFORCE2_0,
 307 +               PCI_VENDOR_ID_NVIDIA,
 308 +                NV_NFORCE_2,
 309 +               "Nvidia",
 310 +               "Nforce2",
 311 +               nvidia_generic_setup },
 312 +#endif /* CONFIG_AGP_NV */
 313 +
 314  #ifdef CONFIG_AGP_HP_ZX1
 315         { PCI_DEVICE_ID_HP_ZX1_LBA,
 316                 PCI_VENDOR_ID_HP,
 317 diff -ur --exclude-from=non-source.list linux/drivers/char/Config.in linux-2.4.21-pre7/drivers/char/Config.in
 318 --- linux/drivers/char/Config.in 2002-12-12 04:06:44.000000000 -0500
 319 +++ linux-2.4.21-pr7/drivers/char/Config.in  2002-12-26 20:59:47.000000000 -0
 320 500
 321 @@ -265,6 +265,7 @@
 322     bool '  Generic SiS support' CONFIG_AGP_SIS
 323     bool '  ALI chipset support' CONFIG_AGP_ALI
 324     bool '  Serverworks LE/HE support' CONFIG_AGP_SWORKS
 325 +   bool '  Nvidia Nforce2 support' CONFIG_AGP_NV
 326     if [ "$CONFIG_IA64" = "y" ]; then
 327        bool '  HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
 328     fi
 329 diff -ur --exclude-from=non-source.list  linux/drivers/include/linux/agp_backend.h linux-2.4.21-pr7/include/linux/agp_backend.h
 330 --- linux/drivers/include/linux/agp_backend.h    2002-12-28 01:24
 331 :46.000000000 -0500
 332 +++ linux-2.4.21-pr7/include/linux/agp_backend.h     2002-12-28 01:40:43.000000000 -0500
 333 @@ -79,6 +79,7 @@
 334         SVWRKS_GENERIC,
 335         HP_ZX1,
 336         APPLE_UNINORTH,
 337 +        NV_NFORCE_2,
 338  };
 339
 340  typedef struct _agp_version {