1 --- linux/include/asm-i386/xor.h-o Sat Dec 23 08:13:50 2000
2 +++ linux/include/asm-i386/xor.h Mon Jan 8 16:33:26 2001
4 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
7 +#include <linux/config.h>
10 * High-speed RAID5 checksumming functions utilizing MMX instructions.
11 * Copyright (C) 1998 Ingo Molnar.
16 +#if defined(CONFIG_X86_FXSR) || defined(CONFIG_X86_RUNTIME_FXSR)
19 * Cache avoiding checksumming functions utilizing KNI instructions
20 * Copyright (C) 1999 Zach Brown (with obvious credit due Ingo)
27 + xor_speed(&xor_block_pIII_sse);
30 +/* We force the use of the SSE xor block because it can write around L2.
31 + We may also be able to load into the L1 only depending on how the cpu
32 + deals with a load to a line that is being prefetched. */
33 +#define XOR_SELECT_TEMPLATE(FASTEST) \
34 + (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
38 +/* Don't try any SSE2 when FXSR is not enabled, because OSFXSR will not be set
41 +#define XOR_SELECT_TEMPLATE(FASTEST) (FASTEST)
45 /* Also try the generic routines. */
46 #include <asm-generic/xor.h>
50 xor_speed(&xor_block_8regs); \
51 xor_speed(&xor_block_32regs); \
53 - xor_speed(&xor_block_pIII_sse); \
55 if (md_cpu_has_mmx()) { \
56 xor_speed(&xor_block_pII_mmx); \
57 xor_speed(&xor_block_p5_mmx); \
61 -/* We force the use of the SSE xor block because it can write around L2.
62 - We may also be able to load into the L1 only depending on how the cpu
63 - deals with a load to a line that is being prefetched. */
64 -#define XOR_SELECT_TEMPLATE(FASTEST) \
65 - (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)