1 Fix cache detection and detect trace cache.
2 Author: Dave Jones <davej@codemonkey.org.uk>
4 diff -urpN --exclude-from=/home/davej/.exclude linux-2.4.20-pre8/arch/i386/kernel/setup.c linux-2.4.20-pre8-leakfix/arch/i386/kernel/setup.c
5 --- linux-2.4.20-pre8/arch/i386/kernel/setup.c 2002-09-26 15:29:12.000000000 +0100
6 +++ linux-2.4.20-pre8-leakfix/arch/i386/kernel/setup.c 2002-09-30 23:03:04.000000000 +0100
7 @@ -1266,15 +1266,6 @@ static void __init display_cacheinfo(str
11 - /* Intel PIII Tualatin. This comes in two flavours.
12 - * One has 256kb of cache, the other 512. We have no way
13 - * to determine which, so we use a boottime override
14 - * for the 512kb model, and assume 256 otherwise.
16 - if ((c->x86_vendor == X86_VENDOR_INTEL) && (c->x86 == 6) &&
17 - (c->x86_model == 11) && (l2size == 0))
20 /* VIA C3 CPUs (670-68F) need further shifting. */
21 if (c->x86_vendor == X86_VENDOR_CENTAUR && (c->x86 == 6) &&
22 ((c->x86_model == 7) || (c->x86_model == 8))) {
23 @@ -2190,6 +2181,7 @@ extern void trap_init_f00f_bug(void);
31 @@ -2209,6 +2201,8 @@ static struct _cache_table cache_table[]
32 { 0x23, LVL_3, 1024 },
33 { 0x25, LVL_3, 2048 },
34 { 0x29, LVL_3, 4096 },
35 + { 0x39, LVL_2, 128 },
36 + { 0x3C, LVL_2, 256 },
40 @@ -2217,11 +2211,15 @@ static struct _cache_table cache_table[]
41 { 0x66, LVL_1_DATA, 8 },
42 { 0x67, LVL_1_DATA, 16 },
43 { 0x68, LVL_1_DATA, 32 },
44 + { 0x70, LVL_TRACE, 12 },
45 + { 0x71, LVL_TRACE, 16 },
46 + { 0x72, LVL_TRACE, 32 },
50 { 0x7C, LVL_2, 1024 },
52 + { 0x83, LVL_2, 512 },
53 { 0x84, LVL_2, 1024 },
54 { 0x85, LVL_2, 2048 },
56 @@ -2229,7 +2237,7 @@ static struct _cache_table cache_table[]
58 static void __init init_intel(struct cpuinfo_x86 *c)
60 - unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
61 + unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
63 #ifndef CONFIG_X86_F00F_WORKS_OK
64 static int f00f_workaround_enabled = 0;
65 @@ -2289,8 +2287,10 @@ static void __init init_intel(struct cpu
67 l3 += cache_table[k].size;
70 + trace += cache_table[k].size;
77 @@ -2298,9 +2298,25 @@ static void __init init_intel(struct cpu
82 - printk(KERN_INFO "CPU: L1 I cache: %dK, L1 D cache: %dK\n",
85 + /* Intel PIII Tualatin. This comes in two flavours.
86 + * One has 256kb of cache, the other 512. We have no way
87 + * to determine which, so we use a boottime override
88 + * for the 512kb model, and assume 256 otherwise.
90 + if ((c->x86 == 6) && (c->x86_model == 11) && (l2 == 0))
92 + /* Allow user to override all this if necessary. */
93 + if (cachesize_override != -1)
94 + l2 = cachesize_override;
97 + printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
99 + printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
101 + printk(", L1 D cache: %dK\n", l1d);
104 printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);