1 From e6a71160cc145e18ab45195abf89884112e02dfb Mon Sep 17 00:00:00 2001
2 From: Kees Cook <keescook@chromium.org>
3 Date: Wed, 18 Jan 2023 12:21:35 -0800
4 Subject: gcc-plugins: Reorganize gimple includes for GCC 13
6 The gimple-iterator.h header must be included before gimple-fold.h
7 starting with GCC 13. Reorganize gimple headers to work for all GCC
10 Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
11 Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
12 Link: https://lore.kernel.org/all/20230113173033.4380-1-palmer@rivosinc.com/
13 Cc: linux-hardening@vger.kernel.org
14 Signed-off-by: Kees Cook <keescook@chromium.org>
16 scripts/gcc-plugins/gcc-common.h | 4 ++--
17 1 file changed, 2 insertions(+), 2 deletions(-)
19 diff --git a/scripts/gcc-plugins/gcc-common.h b/scripts/gcc-plugins/gcc-common.h
20 index 9a1895747b153..84c730da36dd3 100644
21 --- a/scripts/gcc-plugins/gcc-common.h
22 +++ b/scripts/gcc-plugins/gcc-common.h
25 #include "stor-layout.h"
26 #include "internal-fn.h"
28 #include "gimple-expr.h"
29 +#include "gimple-iterator.h"
30 #include "gimple-fold.h"
32 #include "tree-ssa-alias.h"
39 #if BUILDING_GCC_VERSION >= 4009
40 #include "tree-ssa-operands.h"
41 #include "tree-phinodes.h"
43 -#include "gimple-iterator.h"
44 #include "gimple-ssa.h"
45 #include "ssa-iterators.h"
50 From f07788079f515ca4a681c5f595bdad19cfbd7b1d Mon Sep 17 00:00:00 2001
51 From: Arnd Bergmann <arnd@arndb.de>
52 Date: Sat, 3 Dec 2022 11:54:25 +0100
53 Subject: ata: ahci: fix enum constants for gcc-13
55 gcc-13 slightly changes the type of constant expressions that are defined
56 in an enum, which triggers a compile time sanity check in libata:
58 linux/drivers/ata/libahci.c: In function 'ahci_led_store':
59 linux/include/linux/compiler_types.h:357:45: error: call to '__compiletime_assert_302' declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long)
60 357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
62 The new behavior is that sizeof() returns the same value for the
63 constant as it does for the enum type, which is generally more sensible
66 The problem in libata is that it contains a single enum definition for
67 lots of unrelated constants, some of which are large positive (unsigned)
68 integers like 0xffffffff, while others like (1<<31) are interpreted as
69 negative integers, and this forces the enum type to become 64 bit wide
70 even though most constants would still fit into a signed 32-bit 'int'.
72 Fix this by changing the entire enum definition to use BIT(x) in place
73 of (1<<x), which results in all values being seen as 'unsigned' and
74 fitting into an unsigned 32-bit type.
76 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107917
77 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107405
78 Reported-by: Luis Machado <luis.machado@arm.com>
79 Cc: linux-ide@vger.kernel.org
80 Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>
81 Cc: stable@vger.kernel.org
82 Cc: Randy Dunlap <rdunlap@infradead.org>
83 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
84 Tested-by: Luis Machado <luis.machado@arm.com>
85 Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
87 drivers/ata/ahci.h | 245 +++++++++++++++++++++++++++--------------------------
88 1 file changed, 123 insertions(+), 122 deletions(-)
90 (limited to 'drivers/ata')
92 diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
93 index da7ee8bec165a..4cec725cf30a2 100644
94 --- a/drivers/ata/ahci.h
95 +++ b/drivers/ata/ahci.h
97 #include <linux/libata.h>
98 #include <linux/phy/phy.h>
99 #include <linux/regulator/consumer.h>
100 +#include <linux/bits.h>
102 /* Enclosure Management Control */
103 #define EM_CTRL_MSG_TYPE 0x000f0000
104 @@ -53,12 +54,12 @@ enum {
105 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
107 (AHCI_RX_FIS_SZ * 16),
108 - AHCI_IRQ_ON_SG = (1 << 31),
109 - AHCI_CMD_ATAPI = (1 << 5),
110 - AHCI_CMD_WRITE = (1 << 6),
111 - AHCI_CMD_PREFETCH = (1 << 7),
112 - AHCI_CMD_RESET = (1 << 8),
113 - AHCI_CMD_CLR_BUSY = (1 << 10),
114 + AHCI_IRQ_ON_SG = BIT(31),
115 + AHCI_CMD_ATAPI = BIT(5),
116 + AHCI_CMD_WRITE = BIT(6),
117 + AHCI_CMD_PREFETCH = BIT(7),
118 + AHCI_CMD_RESET = BIT(8),
119 + AHCI_CMD_CLR_BUSY = BIT(10),
121 RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
122 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
123 @@ -76,37 +77,37 @@ enum {
124 HOST_CAP2 = 0x24, /* host capabilities, extended */
127 - HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 - HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 - HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
130 - HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
131 + HOST_RESET = BIT(0), /* reset controller; self-clear */
132 + HOST_IRQ_EN = BIT(1), /* global IRQ enable */
133 + HOST_MRSM = BIT(2), /* MSI Revert to Single Message */
134 + HOST_AHCI_EN = BIT(31), /* AHCI enabled */
137 - HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
138 - HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
139 - HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
140 - HOST_CAP_PART = (1 << 13), /* Partial state capable */
141 - HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
142 - HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
143 - HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
144 - HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
145 - HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
146 - HOST_CAP_CLO = (1 << 24), /* Command List Override support */
147 - HOST_CAP_LED = (1 << 25), /* Supports activity LED */
148 - HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
149 - HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
150 - HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
151 - HOST_CAP_SNTF = (1 << 29), /* SNotification register */
152 - HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
153 - HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
154 + HOST_CAP_SXS = BIT(5), /* Supports External SATA */
155 + HOST_CAP_EMS = BIT(6), /* Enclosure Management support */
156 + HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */
157 + HOST_CAP_PART = BIT(13), /* Partial state capable */
158 + HOST_CAP_SSC = BIT(14), /* Slumber state capable */
159 + HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */
160 + HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
161 + HOST_CAP_PMP = BIT(17), /* Port Multiplier support */
162 + HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */
163 + HOST_CAP_CLO = BIT(24), /* Command List Override support */
164 + HOST_CAP_LED = BIT(25), /* Supports activity LED */
165 + HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */
166 + HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
167 + HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */
168 + HOST_CAP_SNTF = BIT(29), /* SNotification register */
169 + HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */
170 + HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */
173 - HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
174 - HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
175 - HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
176 - HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
177 - HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
178 - HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
179 + HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */
180 + HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */
181 + HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */
182 + HOST_CAP2_SDS = BIT(3), /* Support device sleep */
183 + HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */
184 + HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */
186 /* registers for each SATA port */
187 PORT_LST_ADDR = 0x00, /* command list DMA addr */
188 @@ -128,24 +129,24 @@ enum {
189 PORT_DEVSLP = 0x44, /* device sleep */
191 /* PORT_IRQ_{STAT,MASK} bits */
192 - PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
193 - PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
194 - PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
195 - PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
196 - PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
197 - PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
198 - PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
199 - PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
201 - PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
202 - PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
203 - PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
204 - PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
205 - PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
206 - PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
207 - PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
208 - PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
209 - PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
210 + PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */
211 + PORT_IRQ_TF_ERR = BIT(30), /* task file error */
212 + PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */
213 + PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */
214 + PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */
215 + PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */
216 + PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */
217 + PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */
219 + PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */
220 + PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */
221 + PORT_IRQ_CONNECT = BIT(6), /* port connect change status */
222 + PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */
223 + PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */
224 + PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */
225 + PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */
226 + PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */
227 + PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */
229 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
231 @@ -161,25 +162,25 @@ enum {
232 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
235 - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
236 - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
237 - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
238 - PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
239 - PORT_CMD_ESP = (1 << 21), /* External Sata Port */
240 - PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
241 - PORT_CMD_PMP = (1 << 17), /* PMP attached */
242 - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
243 - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
244 - PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
245 - PORT_CMD_CLO = (1 << 3), /* Command list override */
246 - PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
247 - PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
248 - PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
250 - PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
251 - PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
252 - PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
253 - PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
254 + PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */
255 + PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */
256 + PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */
257 + PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */
258 + PORT_CMD_ESP = BIT(21), /* External Sata Port */
259 + PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */
260 + PORT_CMD_PMP = BIT(17), /* PMP attached */
261 + PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */
262 + PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */
263 + PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */
264 + PORT_CMD_CLO = BIT(3), /* Command list override */
265 + PORT_CMD_POWER_ON = BIT(2), /* Power up device */
266 + PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */
267 + PORT_CMD_START = BIT(0), /* Enable port DMA engine */
269 + PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */
270 + PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */
271 + PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */
272 + PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */
275 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
276 @@ -192,9 +193,9 @@ enum {
277 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
278 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
279 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
280 - PORT_FBS_SDE = (1 << 2), /* FBS single device error */
281 - PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
282 - PORT_FBS_EN = (1 << 0), /* Enable FBS */
283 + PORT_FBS_SDE = BIT(2), /* FBS single device error */
284 + PORT_FBS_DEC = BIT(1), /* FBS device error clear */
285 + PORT_FBS_EN = BIT(0), /* Enable FBS */
287 /* PORT_DEVSLP bits */
288 PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
289 @@ -202,44 +203,44 @@ enum {
290 PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
291 PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
292 PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
293 - PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
294 - PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
295 + PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */
296 + PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */
298 /* hpriv->flags bits */
300 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
302 - AHCI_HFLAG_NO_NCQ = (1 << 0),
303 - AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
304 - AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
305 - AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
306 - AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
307 - AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
308 - AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
309 - AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
310 - AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
311 - AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
312 - AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
314 - AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
315 - AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
316 - AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
317 - AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
318 - port start (wait until
319 - error-handling stage) */
320 - AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
321 - AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
322 + AHCI_HFLAG_NO_NCQ = BIT(0),
323 + AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */
324 + AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */
325 + AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */
326 + AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */
327 + AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */
328 + AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */
329 + AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */
330 + AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */
331 + AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */
332 + AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as
334 + AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */
335 + AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */
336 + AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */
337 + AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on
338 + port start (wait until
339 + error-handling stage) */
340 + AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */
341 + AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */
343 #ifdef CONFIG_PCI_MSI
344 - AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
345 + AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */
347 /* compile out MSI infrastructure */
348 AHCI_HFLAG_MULTI_MSI = 0,
350 - AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
351 - AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
352 - AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
354 + AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */
355 + AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */
356 + AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read
361 @@ -261,22 +262,22 @@ enum {
365 - EM_CTL_RST = (1 << 9), /* Reset */
366 - EM_CTL_TM = (1 << 8), /* Transmit Message */
367 - EM_CTL_MR = (1 << 0), /* Message Received */
368 - EM_CTL_ALHD = (1 << 26), /* Activity LED */
369 - EM_CTL_XMT = (1 << 25), /* Transmit Only */
370 - EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
371 - EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
372 - EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
373 - EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
374 - EM_CTL_LED = (1 << 16), /* LED messages supported */
375 + EM_CTL_RST = BIT(9), /* Reset */
376 + EM_CTL_TM = BIT(8), /* Transmit Message */
377 + EM_CTL_MR = BIT(0), /* Message Received */
378 + EM_CTL_ALHD = BIT(26), /* Activity LED */
379 + EM_CTL_XMT = BIT(25), /* Transmit Only */
380 + EM_CTL_SMB = BIT(24), /* Single Message Buffer */
381 + EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */
382 + EM_CTL_SES = BIT(18), /* SES-2 messages supported */
383 + EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */
384 + EM_CTL_LED = BIT(16), /* LED messages supported */
386 /* em message type */
387 - EM_MSG_TYPE_LED = (1 << 0), /* LED */
388 - EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
389 - EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
390 - EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
391 + EM_MSG_TYPE_LED = BIT(0), /* LED */
392 + EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */
393 + EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */
394 + EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */
397 struct ahci_cmd_hdr {
401 From 5a6b64adc18d9adfb497a529ff004d59b6df151f Mon Sep 17 00:00:00 2001
402 From: Sam James <sam@gentoo.org>
403 Date: Wed, 1 Feb 2023 23:00:09 +0000
404 Subject: gcc-plugins: drop -std=gnu++11 to fix GCC 13 build
406 The latest GCC 13 snapshot (13.0.1 20230129) gives the following:
408 cc1: error: cannot load plugin ./scripts/gcc-plugins/randomize_layout_plugin.so
409 :./scripts/gcc-plugins/randomize_layout_plugin.so: undefined symbol: tree_code_type
412 This ends up being because of https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=b0241ce6e37031
413 upstream in GCC which changes the visibility of some types used by the kernel's
414 plugin infrastructure like tree_code_type.
416 After discussion with the GCC folks, we found that the kernel needs to be building
417 plugins with the same flags used to build GCC - and GCC defaults to gnu++17
418 right now. The minimum GCC version needed to build the kernel is GCC 5.1
419 and GCC 5.1 already defaults to gnu++14 anyway, so just drop the flag, as
420 all GCCs that could be used to build GCC already default to an acceptable
421 version which was >= the version we forced via flags until now.
423 Bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108634
424 Signed-off-by: Sam James <sam@gentoo.org>
425 Signed-off-by: Kees Cook <keescook@chromium.org>
426 Link: https://lore.kernel.org/r/20230201230009.2252783-1-sam@gentoo.org
428 scripts/gcc-plugins/Makefile | 2 +-
429 1 file changed, 1 insertion(+), 1 deletion(-)
431 diff --git a/scripts/gcc-plugins/Makefile b/scripts/gcc-plugins/Makefile
432 index b34d11e226366..320afd3cf8e82 100644
433 --- a/scripts/gcc-plugins/Makefile
434 +++ b/scripts/gcc-plugins/Makefile
436 export HOST_EXTRACFLAGS
438 HOSTLIBS := hostcxxlibs
439 - HOST_EXTRACXXFLAGS += -I$(GCC_PLUGINS_DIR)/include -I$(src) -std=gnu++98 -fno-rtti
440 + HOST_EXTRACXXFLAGS += -I$(GCC_PLUGINS_DIR)/include -I$(src) -fno-rtti
441 HOST_EXTRACXXFLAGS += -fno-exceptions -fasynchronous-unwind-tables -ggdb
442 HOST_EXTRACXXFLAGS += -Wno-narrowing -Wno-unused-variable
443 HOST_EXTRACXXFLAGS += -Wno-format-diag