1 --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h.fix Mon Jul 2 19:46:04 2001
2 +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h Mon Jan 21 08:18:14 2002
5 if(!(pS3->PCIRetry)) { \
7 - while(inb(GP_STAT) & (0x0100 >> (v))); \
8 + while(mmio_INB_GP_STAT() & (0x0100 >> (v))); \
11 #define CMD_REG_WIDTH 0x200 /* select 32bit command register */
12 --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c.fix Sun Oct 28 12:33:44 2001
13 +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c Mon Jan 21 08:22:08 2002
16 static void S3Sync(ScrnInfoPtr pScrn)
18 + S3Ptr pS3 = S3PTR(pScrn);
23 static void S3SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y,
27 S3Ptr pS3 = S3PTR(pScrn);
31 SET_CURPT((short)x, (short)y);
34 int err, int len, int octant)
37 S3Ptr pS3 = S3PTR(pScrn);
43 --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c.fix Mon Jul 2 19:46:04 2001
44 +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c Mon Jan 21 08:18:14 2002
47 static void S3_Sync(ScrnInfoPtr pScrn)
49 + S3Ptr pS3 = S3PTR(pScrn);
52 --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c.fix Thu Dec 27 07:24:19 2001
53 +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c Mon Jan 21 08:18:14 2002
54 @@ -1569,7 +1569,20 @@
58 - outw(SUBSYS_CNTL, 0x8000 | 0x1000);
60 +* XXX: resetting the Trio64V2/GX causes trouble with the SGRAM memory bus
61 +* (gets out of sync? same as setting CR88_6) which I don't know to fix,
62 +* so better not reset that chip and cross fingers...
63 +* This happens at least for some IBM Netfinity boxes (e.g. 7000M10) with 1MB SGRAM.
65 + if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) {
66 + outb(vgaCRIndex, 0x36);
67 + tmp = inb(vgaCRReg);
68 + if ((tmp & 0x0c) != 0x04) /* no SGRAM */
69 + outw(SUBSYS_CNTL, 0x8000 | 0x1000);
71 + else /* do normal reset for S3 chip... */
72 + outw(SUBSYS_CNTL, 0x8000 | 0x1000);
73 outw(SUBSYS_CNTL, 0x4000 | 0x1000);
76 @@ -1603,6 +1616,12 @@
79 SET_SCISSORS(0, 0, pS3->s3ScissR, pS3->s3ScissB);
80 + if(pS3->s3Bpp > 2) {
82 + SET_MULT_MISC(0x200);
87 outb(vgaCRIndex, 0x6f);
89 --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h.fix Mon Jul 2 19:46:04 2001
90 +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h Mon Jan 21 08:18:14 2002
96 + * mmio reads from GP_STAT
98 +#if !defined(__alpha__)
99 +#define mmio_INB_GP_STAT() (*(((volatile unsigned char*)pS3->MMIOBase)+GP_STAT) & 0xff)
100 +#define mmio_INW_GP_STAT() (*(((volatile unsigned short*)pS3->MMIOBase)+GP_STAT/2))
102 +#define mmio_INB_GP_STAT() inb(GP_STAT)
103 +#define mmio_INW_GP_STAT() inw(GP_STAT)
106 #define WaitIdle() do { \
108 - while(inw(GP_STAT) & GPBUSY); \
109 + if (pS3->S3NewMMIO) \
110 + while(mmio_INW_GP_STAT() & GPBUSY); \
112 + while(inw(GP_STAT) & GPBUSY); \
118 #define CMD_REG_WIDTH 0x0000
120 -#define WaitQueue(n) do { \
121 +#define WaitQueue(n) do { \
123 - while(inb(GP_STAT) & (0x0100 >> (n))); \
124 + if (pS3->S3NewMMIO) \
125 + while(mmio_INB_GP_STAT() & (0x0100 >> (n))); \
127 + while(inb(GP_STAT) & (0x0100 >> (n))); \
130 #define WaitQueue16_32(n16,n32) \