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65af7ff3 1diff -Nur --exclude '*.orig' linux-2.6.8.1.org/drivers/scsi/iteraid.c linux-2.6.8.1/drivers/scsi/iteraid.c
2--- linux-2.6.8.1.org/drivers/scsi/iteraid.c 1970-01-01 01:00:00.000000000 +0100
3+++ linux-2.6.8.1/drivers/scsi/iteraid.c 2004-05-11 14:46:12.000000000 +0200
4@@ -0,0 +1,5844 @@
5+/*
6+ * linux/drivers/scsi/iteraid.c
7+ *
8+ * (C) Copyright 2002-2004 ITE Tech, inc.
9+ *
10+ * Nov 11, 2002 Mark Lu file created.
11+ *
12+ * ITE IT8212 RAID controller device driver for Linux.
13+ *
14+ * This program is free software; you can redistribute it and/or modify it
15+ * under the terms of the GNU General Public License as published by the
16+ * Free Software Foundation; either version 2, or (at your option) any
17+ * later version.
18+ *
19+ * This program is distributed in the hope that it will be useful, but
20+ * WITHOUT ANY WARRANTY; without even the implied warranty of
21+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22+ * General Public License for more details.
23+ *
24+ * Revision 0.0 2002/12/05 15:12:12 root
25+ * Empty function bodies; detect() works.
26+ *
27+ * Revision 0.1 2002/12/17 19:21:37 root
28+ * First "dma thing doesn't work" version.
29+ *
30+ * Revision 0.3 2002/12/23 17:12:09 root
31+ * Rewrite the dma routines. Reference the ide-dma.c.
32+ *
33+ * Revision 0.4 2002/12/26 10:19:29 root
34+ * The dma read/write works, using some ways to prove it. But there is a
35+ * problem about the "unknown partition table". The fdisk is ok, but
36+ * after writing the created partitions, it still shows the "unknown
37+ * partition table" and i can't access the created partitions.
38+ *
39+ * Revision 0.5 2003/01/07 21:49:30 root
40+ * The problem of "unknown partition table" has been solved.
41+ * We must "ENABLE CLUSTERING". There is still a another problem about
42+ * the SCATTER/GATHER.
43+ *
44+ * Revision 0.6 2003/01/10 17:45:32 root
45+ * The SCATTER/GATHER problem has been solved. Now verify the read/write
46+ * function and make sure each RAID configurations are workable. If testing
47+ * is OK, then it will be a version 1.0.....
48+ *
49+ * Revision 1.0 2003/01/16 17:45:32 root
50+ * First release version.
51+ *
52+ * FixME 1:
53+ * In RedHat 7.3, if using SG_ALL, the SCSI will timeout. It looks like
54+ * an command is requested but the interrupt is not been asserted. So
55+ * try to add a watchdog timer to monitor the interrupts. But this kind
56+ * of situration will not happen in Mandrake 9.0 and also when using
57+ * SG_NONE in RedHat 7.3.
58+ *
59+ * FixME 2:
60+ * Module load problem in RedHat 7.3.
61+ *
62+ * Fixed: Compile in the graphic mode (GNOME or KDE) will fix the
63+ * module load problem.
64+ *
65+ * Revision 1.1 2003/02/10 10:32:21 root
66+ * Compile in the graphic mode (GNOME or KDE) will fix the
67+ * module load problem.
68+ *
69+ * Revision 1.2 2003/02/18 14:10:35 root
70+ * Fix the interrupt service routine for share irq problem.
71+ *
72+ * ATAPI support ---> schedule is three weeks. (2003/02/28)
73+ *
74+ * Revision 1.3 2003/02/27
75+ * First relase ATAPI version. But there will be an error if no disc in the
76+ * CD-ROM. Because the commands like TEST_UNIT_READY and READ_CAPACITY will
77+ * get the error response. This situration in WINDOWS will be then send the
78+ * REQUEST SENSE command to the device but in Linux, it will never get
79+ * REQUEST SENSE command. So can we send by ourself???
80+ *
81+ * 2003/03/05 root
82+ *
83+ * Note 1:
84+ * According to "The Linux SCSI Generic (sg) HOWTO", the device will respond
85+ * with a single byte value call the 'scsi_status'. GOOD is the scsi status
86+ * indicating everything has gone well. The most common other status is
87+ * CHECK CONDITION. In this latter case, the SCSI mid layer issues a REQUEST
88+ * SENSE SCSI command. The response of the REQUEST SENSE is 18 bytes or more
89+ * in length and is called the "sense buffer". It will indicate why the original
90+ * command may not have been executed. It is important to realize that a CHECK
91+ * CONDITION may very in severity from informative (e.g. command needed to be
92+ * retried before succeeding) to fatal (e.g. 'medium error' which often
93+ * indicates it is time to replace the disk).
94+ *
95+ * Note 2:
96+ * When using the ATAPI BIOS, we also do not need to set up the timimg in linux
97+ * driver. But it is necessary to write the timing routine in win system,
98+ * cause it has a s1, s2, s3 mode and devices wake up from these modes need to
99+ * be initialized again and do not pass through the BIOS.
100+ *
101+ * Note 3:
102+ * The 48-bit support and AP for RAID in linux will the next job.
103+ *
104+ * Revision 1.31 2003/03/14 09:40:35 root
105+ * Fix an error when no disc is on the CD-ROM and the audio cd is ready to play.
106+ *
107+ * 2003/04/08 root
108+ * The ioctl code sklection is finished. But there is a problem about
109+ * "Bad address" when copy_from_user() is called.
110+ *
111+ * Fixed: Use kmalloc() and kfree() to allocate the buffer instead of automatic
112+ * variables (use stack). The stack size is limited in kernel space.
113+ *
114+ * Revision 1.32 2003/04/14 18:20:23 root
115+ * Complete the IOCTLs code.
116+ *
117+ * The IOCTLs are listed below
118+ * ===========================
119+ *
120+ * (1) ITE_IOC_GET_IDENTIFY_DATA
121+ *
122+ * Return virtual drive 512 bytes identification data.
123+ *
124+ * (2) ITE_IOC_GET_PHY_DISK_STATUS
125+ *
126+ * Developer can decide to return 4 physical disk information in
127+ * 512 bytes (data structure should be defined) or 512 bytes
128+ * identification data of the physical disk specified by AP.
129+ *
130+ * (3) ITE_IOC_CREATE_DISK_ARRAY
131+ *
132+ * Create a new array and erase (or keep) boot sector.
133+ *
134+ * (4) ITE_IOC_REBUILD_START
135+ *
136+ * AP nees to specify target/source drive, starting LBA and length.
137+ *
138+ * (5) ITE_IOC_GET_REBUILD_STATUS
139+ *
140+ * Return rebuild percentage or last LBA No.
141+ *
142+ * (6) ITE_IOC_RESET_ADAPTER
143+ *
144+ * Reset the controller.
145+ *
146+ * Revision 1.33 2003/04/15 11:10:08 root
147+ * The 48-bit support.
148+ *
149+ * Revision 1.34 2003/04/20 13:20:38 root
150+ * Change some values in iteraid.h, so it will not hang in Red Hat Linux
151+ * and improve the performance.
152+ *
153+ * can_queue: 1 --------------------> can_queue: 124
154+ * sg_tablesize: SG_NONE -----------> sg_tablesize: 16
155+ * cmd_per_lun: 128 ----------------> cmd_per_lun: 1
156+ * use_clustering: ENABLE_CLUSTER --> use_clustering: DISABLE_CLUSTER
157+ *
158+ * 2003/04/25 root
159+ * The code will hang on Gigabyte's motherboard when the sourth bridge is
160+ * sis 962L and 963.
161+ *
162+ * Revision 1.35 2003/04/28 10:06:20 root
163+ * Fixed: Do not enable interrupt again when send each command in
164+ * IdeSendCommand() routine.
165+ *
166+ * 2003/05/20 root
167+ * Linux SCSI error handling code should be changed to new one.
168+ *
169+ * The shortcomings of the existing code.
170+ *
171+ * 1. The old error handling code is an imperfect state machine. It
172+ * would occasionally get stuck in loops whereby the bus would be reset
173+ * over and over again, where the problem would never be resolved and
174+ * control of the machine would never return to the user.
175+ *
176+ * Reference the http://www.andante.org/scsi.html
177+ *
178+ * The kernel after 2.5 or 2.6 will not use the old error handling codes.
179+ *
180+ * In iteraid.h
181+ *
182+ * #define ITERAID \
183+ * { \
184+ * proc_name: "it8212", \
185+ * proc_info: iteraid_proc_info, \
186+ * . \
187+ * . \
188+ * eh_about_handler: iteraid_about_eh, \ --> New added
189+ * eh_device_reset_handler: NULL \ --> New added
190+ * eh_bus_reset_handler: NULL \ --> New added
191+ * eh_host_reset_handler: iteraid_reset_eh \ --> New added
192+ * use_new_eh_code: 0 --> 1 \
193+ * }
194+ *
195+ * 2003/06/23 root 17:30:41
196+ * TODO: Error code still use the old method.
197+ *
198+ * Revision 1.36 2003/06/23 19:52:31 root
199+ * Fixed: Use the new error handling code.
200+ *
201+ * Revision 1.40 2003/07/25 10:00:00 root
202+ * Released version 1.40 by Mark Lu.
203+ *
204+ * Revision 1.41 2003/08/06 13:55:17 root
205+ * Added support for clean shutdown notification/feature table.
206+ *
207+ * Revision 1.42 2003/08/21 11:38:57 root
208+ * Problem: When linux was installed onto IT8212 controller with two disks,
209+ * configured as RAID 1 (P0S0), the hot swap will hang the system.
210+ * Solve: Use the AtapiResetController() instead of only IT8212ResetAdapter().
211+ *
212+ * Revision 1.43 2003/12/24 23:19:07 root
213+ * Fixed: Fixed a compile error at line 5815. Just move up the variable
214+ * rebuild_info of type PRAID_REBUILD_INFO with other variables.
215+ *
216+ * Revision 1.44 2004/03/16 13:12:35 root
217+ * Fixed: (1) The crash problem when using "rmmod" to remove the iteraid module.
218+ * (2) Support two IT8212 cards or chips.
219+ * (3) A bug when accessing the slave disk more than 137G.
220+ * Thanks for Martine Purschke kindly help to find this bug and
221+ * fix it.
222+ * (4) can_queue: 12 --------------------> can_queue: 1
223+ * (5) Change the Transparent(Bypass) mode initial PCI registers setting.
224+ * (6) Change IDE I/O, control and dma base address from USHORT to ULONG,
225+ * so that the non x86 platform, like MIPS, will load the correct
226+ * address.
227+ * (7) Add GPL license in iteraid.h.
228+ *
229+ * Revision 1.45 2004/05/07 11:07:16 root
230+ * Fixed : (1) 64-bit support.
231+ * (2) In IT8212SetBestTransferMode() there are a number of arrays,
232+ * all of which are defined read/write and assigned on the stack.
233+ * Now put them in a R/O segment, by replacing e.g. "UCHAR
234+ * udmaTiming" with "static const UCHAR udmaTiming".
235+ */
236+
237+#include <linux/module.h>
238+
239+MODULE_AUTHOR ("ITE Tech,Inc.");
240+MODULE_DESCRIPTION ("ITE IT8212 RAID Controller Linux Driver");
241+
242+#include <linux/kernel.h>
243+#include <linux/pci.h>
244+#include <linux/time.h>
245+#include <linux/proc_fs.h>
246+#include <linux/sched.h>
247+#include <linux/ioport.h>
248+#include <linux/blkdev.h>
249+#include <linux/hdreg.h>
250+#include <linux/string.h>
251+#include <linux/smp.h>
252+#include <linux/delay.h>
253+#include <linux/reboot.h>
254+#include <linux/spinlock.h>
255+#include <linux/interrupt.h>
256+
257+#include <asm/errno.h>
258+#include <asm/io.h>
259+#include <asm/irq.h>
260+#include <asm/uaccess.h>
261+
262+#include "scsi.h"
263+#include "hosts.h"
264+
265+#include "iteraid.h"
266+
267+MODULE_LICENSE("GPL");
268+
269+#define MARK_DEBUG_DUMP_MEM 0 /* 1=Enable dump memory content */
270+#define MARK_DEBUG_BYPASS_MODE 0 /* 1=Enable use bypass mode */
271+#define MARK_DUMP_CREATE_INFO 0 /* 1=Dump raid create info */
272+#define MARK_SET_BEST_TRANSFER 0 /* 0=BIOS set best trans mode */
273+
274+#define PRD_BYTES 8 /* PRD table size */
275+#define PRD_ENTRIES (PAGE_SIZE / (2 * PRD_BYTES))
276+
277+struct Scsi_Host * ite_vhost = 0; /* SCSI virtual host */
278+Scsi_Cmnd * it8212_req_last = 0; /* SRB request list */
279+
280+unsigned int NumAdapters = 0; /* Adapters number */
281+PITE_ADAPTER ite_adapters[2]; /* How many adapters support */
282+
283+/************************************************************************
284+ * Notifier blockto get a notify on system shutdown/halt/reboot.
285+ ************************************************************************/
286+static int ite_halt(struct notifier_block *nb, ulong event, void *buf);
287+struct notifier_block ite_notifier =
288+{
289+ ite_halt, NULL, 0
290+};
291+
292+static struct semaphore mimd_entry_mtx;
293+
294+static spinlock_t queue_request_lock = SPIN_LOCK_UNLOCKED;
295+static spinlock_t io_request_lock = SPIN_LOCK_UNLOCKED;
296+
297+static int driver_ver = 145; /* Current driver version */
298+static int ite_major = 0; /* itedev chardev major number */
299+
300+/************************************************************************
301+ * The File Operations structure for the ioctl interface of the driver.
302+ ************************************************************************/
303+static struct file_operations itedev_fops =
304+{
305+ .owner = THIS_MODULE,
306+ .ioctl = itedev_ioctl_entry,
307+ .open = itedev_open,
308+ .release = itedev_close
309+};
310+
311+#if (MARK_DEBUG_DUMP_MEM)
312+/************************************************************************
313+ * Dump buffer.
314+ ************************************************************************/
315+static void
316+HexDump(unsigned char *buf, int length)
317+{
318+
319+ unsigned int i = 0;
320+ unsigned int j = 0;
321+
322+ printk("\n");
323+ for (i = 0; i < length; i += 16)
324+ {
325+ printk("%04X ", i);
326+ for (j = i; (j < i + 8) && (j < length); j++)
327+ {
328+ printk(" %02X", buf[j]);
329+ }
330+ if (j == i + 8) printk("-");
331+ for (j = i + 8; (j < i + 16) && (j < length); j++)
332+ {
333+ printk("%02X ", buf[j]);
334+ }
335+ printk("\n");
336+ }
337+
338+} /* end HexDump */
339+#endif
340+
341+/************************************************************************
342+ * This routine maps ATAPI and IDE errors to specific SRB statuses.
343+ ************************************************************************/
344+u8
345+MapError(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
346+{
347+
348+ u8 errorByte;
349+ u8 srbStatus;
350+ u8 scsiStatus;
351+
352+ /*
353+ * Read the error register.
354+ */
355+ errorByte = inb(pChan->io_ports[IDE_ERROR_OFFSET]);
356+ printk("MapError: error register is %x\n", errorByte);
357+
358+ /*
359+ * If this is ATAPI error.
360+ */
361+ if (pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_ATAPI_DEVICE)
362+ {
363+ switch (errorByte >> 4)
364+ {
365+ case SCSI_SENSE_NO_SENSE:
366+ printk("ATAPI: no sense information\n");
367+ scsiStatus = SCSISTAT_CHECK_CONDITION;
368+ srbStatus = SRB_STATUS_ERROR;
369+ break;
370+
371+ case SCSI_SENSE_RECOVERED_ERROR:
372+ printk("ATAPI: recovered error\n");
373+ scsiStatus = 0;
374+ srbStatus = SRB_STATUS_SUCCESS;
375+ break;
376+
377+ case SCSI_SENSE_NOT_READY:
378+ printk("ATAPI: device not ready\n");
379+ scsiStatus = SCSISTAT_CHECK_CONDITION;
380+ srbStatus = SRB_STATUS_ERROR;
381+ break;
382+
383+ case SCSI_SENSE_MEDIUM_ERROR:
384+ printk("ATAPI: media error\n");
385+ scsiStatus = SCSISTAT_CHECK_CONDITION;
386+ srbStatus = SRB_STATUS_ERROR;
387+ break;
388+
389+ case SCSI_SENSE_HARDWARE_ERROR:
390+ printk("ATAPI: hardware error\n");
391+ scsiStatus = SCSISTAT_CHECK_CONDITION;
392+ srbStatus = SRB_STATUS_ERROR;
393+ break;
394+
395+ case SCSI_SENSE_ILLEGAL_REQUEST:
396+ printk("ATAPI: illegal request\n");
397+ scsiStatus = SCSISTAT_CHECK_CONDITION;
398+ srbStatus = SRB_STATUS_ERROR;
399+ break;
400+
401+ case SCSI_SENSE_UNIT_ATTENTION:
402+ printk("ATAPI: unit attention\n");
403+ scsiStatus = SCSISTAT_CHECK_CONDITION;
404+ srbStatus = SRB_STATUS_ERROR;
405+ break;
406+
407+ case SCSI_SENSE_DATA_PROTECT:
408+ printk("ATAPI: data protect\n");
409+ scsiStatus = SCSISTAT_CHECK_CONDITION;
410+ srbStatus = SRB_STATUS_ERROR;
411+ break;
412+
413+ case SCSI_SENSE_BLANK_CHECK:
414+ printk("ATAPI: blank check\n");
415+ scsiStatus = SCSISTAT_CHECK_CONDITION;
416+ srbStatus = SRB_STATUS_ERROR;
417+ break;
418+
419+ case SCSI_SENSE_ABORTED_COMMAND:
420+ printk("ATAPI: command Aborted\n");
421+ scsiStatus = SCSISTAT_CHECK_CONDITION;
422+ srbStatus = SRB_STATUS_ERROR;
423+ break;
424+
425+ default:
426+ printk("ATAPI: invalid sense information\n");
427+ scsiStatus = 0;
428+ srbStatus = SRB_STATUS_ERROR;
429+ break;
430+ }
431+ }
432+ /*
433+ * If this is IDE error.
434+ */
435+ else
436+ {
437+ scsiStatus = 0;
438+ srbStatus = SRB_STATUS_ERROR;
439+
440+ /*
441+ * Save errorByte, to be used by SCSIOP_REQUEST_SENSE.
442+ */
443+ pChan->ReturningMediaStatus = errorByte;
444+
445+ if (errorByte & IDE_ERROR_MEDIA_CHANGE_REQ)
446+ {
447+ printk("IDE: media change\n");
448+ scsiStatus = SCSISTAT_CHECK_CONDITION;
449+ srbStatus = SRB_STATUS_ERROR;
450+ }
451+ else if (errorByte & IDE_ERROR_COMMAND_ABORTED)
452+ {
453+ printk("IDE: command abort\n");
454+ srbStatus = SRB_STATUS_ABORTED;
455+ scsiStatus = SCSISTAT_CHECK_CONDITION;
456+
457+ if (Srb->SenseInfoBuffer)
458+ {
459+ PSENSE_DATA senseBuffer = (PSENSE_DATA)Srb->SenseInfoBuffer;
460+
461+ senseBuffer->ErrorCode = 0x70;
462+ senseBuffer->Valid = 1;
463+ senseBuffer->AdditionalSenseLength = 0xB;
464+ senseBuffer->SenseKey = SCSI_SENSE_ABORTED_COMMAND;
465+ senseBuffer->AdditionalSenseCode = 0;
466+ senseBuffer->AdditionalSenseCodeQualifier = 0;
467+
468+ srbStatus |= SRB_STATUS_AUTOSENSE_VALID;
469+ }
470+ /*
471+ * pChan->ErrorCount++;
472+ */
473+ }
474+ else if (errorByte & IDE_ERROR_END_OF_MEDIA)
475+ {
476+ printk("IDE: end of media\n");
477+
478+ scsiStatus = SCSISTAT_CHECK_CONDITION;
479+ srbStatus = SRB_STATUS_ERROR;
480+
481+ if (!(pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_MEDIA_STATUS_ENABLED))
482+ {
483+ /*
484+ * pChan->ErrorCount++;
485+ */
486+ }
487+ }
488+ else if (errorByte & IDE_ERROR_ILLEGAL_LENGTH)
489+ {
490+ printk("IDE: illegal length\n");
491+ srbStatus = SRB_STATUS_INVALID_REQUEST;
492+ }
493+ else if (errorByte & IDE_ERROR_BAD_BLOCK)
494+ {
495+ printk("IDE: bad block\n");
496+
497+ srbStatus = SRB_STATUS_ERROR;
498+ scsiStatus = SCSISTAT_CHECK_CONDITION;
499+
500+ if (Srb->SenseInfoBuffer)
501+ {
502+ PSENSE_DATA senseBuffer = (PSENSE_DATA)Srb->SenseInfoBuffer;
503+
504+ senseBuffer->ErrorCode = 0x70;
505+ senseBuffer->Valid = 1;
506+ senseBuffer->AdditionalSenseLength = 0xB;
507+ senseBuffer->SenseKey = SCSI_SENSE_MEDIUM_ERROR;
508+ senseBuffer->AdditionalSenseCode = 0;
509+ senseBuffer->AdditionalSenseCodeQualifier = 0;
510+
511+ srbStatus |= SRB_STATUS_AUTOSENSE_VALID;
512+ }
513+ }
514+ else if (errorByte & IDE_ERROR_ID_NOT_FOUND)
515+ {
516+ printk("IDE: id not found\n");
517+
518+ srbStatus = SRB_STATUS_ERROR;
519+ scsiStatus = SCSISTAT_CHECK_CONDITION;
520+
521+ if (Srb->SenseInfoBuffer)
522+ {
523+ PSENSE_DATA senseBuffer = (PSENSE_DATA)Srb->SenseInfoBuffer;
524+
525+ senseBuffer->ErrorCode = 0x70;
526+ senseBuffer->Valid = 1;
527+ senseBuffer->AdditionalSenseLength = 0xB;
528+ senseBuffer->SenseKey = SCSI_SENSE_MEDIUM_ERROR;
529+ senseBuffer->AdditionalSenseCode = 0;
530+ senseBuffer->AdditionalSenseCodeQualifier = 0;
531+
532+ srbStatus |= SRB_STATUS_AUTOSENSE_VALID;
533+ }
534+ /*
535+ * pChan->ErrorCount++;
536+ */
537+ }
538+ else if (errorByte & IDE_ERROR_MEDIA_CHANGE)
539+ {
540+ printk("IDE: media change\n");
541+
542+ scsiStatus = SCSISTAT_CHECK_CONDITION;
543+ srbStatus = SRB_STATUS_ERROR;
544+
545+ if (Srb->SenseInfoBuffer)
546+ {
547+ PSENSE_DATA senseBuffer = (PSENSE_DATA)Srb->SenseInfoBuffer;
548+
549+ senseBuffer->ErrorCode = 0x70;
550+ senseBuffer->Valid = 1;
551+ senseBuffer->AdditionalSenseLength = 0xD;
552+ senseBuffer->SenseKey = SCSI_SENSE_UNIT_ATTENTION;
553+ senseBuffer->AdditionalSenseCode = SCSI_ADSENSE_MEDIUM_CHANGED;
554+ senseBuffer->AdditionalSenseCodeQualifier = 0;
555+
556+ srbStatus |= SRB_STATUS_AUTOSENSE_VALID;
557+ }
558+ }
559+ else if (errorByte & IDE_ERROR_DATA_ERROR)
560+ {
561+ printk("IDE: data error\n");
562+
563+ scsiStatus = SCSISTAT_CHECK_CONDITION;
564+ srbStatus = SRB_STATUS_ERROR;
565+
566+ if (!(pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_MEDIA_STATUS_ENABLED))
567+ {
568+ /*
569+ * pChan->ErrorCount++;
570+ */
571+ }
572+
573+ /*
574+ * Build sense buffer.
575+ */
576+ if (Srb->SenseInfoBuffer)
577+ {
578+ PSENSE_DATA senseBuffer = (PSENSE_DATA)Srb->SenseInfoBuffer;
579+
580+ senseBuffer->ErrorCode = 0x70;
581+ senseBuffer->Valid = 1;
582+ senseBuffer->AdditionalSenseLength = 0xB;
583+ senseBuffer->SenseKey = SCSI_SENSE_MEDIUM_ERROR;
584+ senseBuffer->AdditionalSenseCode = 0;
585+ senseBuffer->AdditionalSenseCodeQualifier = 0;
586+
587+ srbStatus |= SRB_STATUS_AUTOSENSE_VALID;
588+ }
589+ }
590+ }
591+
592+ /*
593+ * Set SCSI status to indicate a check condition.
594+ */
595+ Srb->ScsiStatus = scsiStatus;
596+
597+ return srbStatus;
598+
599+} /* end MapError */
600+
601+/************************************************************************
602+ * Just get the higest bit value.
603+ ************************************************************************/
604+static u8
605+RaidGetHighestBit(u8 Number)
606+{
607+
608+ char bit;
609+
610+ for (bit = 7; bit >= 0; bit--)
611+ {
612+ if (Number & (1 << bit)) return bit;
613+ }
614+
615+ return 0xFF;
616+
617+} /* end RaidGetHighestBit */
618+
619+/************************************************************************
620+ * Reset IDE controller or ATAPI device.
621+ ************************************************************************/
622+static void
623+AtapiResetController(PITE_ADAPTER pAdap, PChannel pChan)
624+{
625+
626+ u8 resetResult;
627+ u8 status;
628+ u8 i;
629+ unsigned long dma_base;
630+ SCSI_REQUEST_BLOCK srb;
631+ printk("AtapiResetController enter\n");
632+
633+ dma_base = pChan->dma_base;
634+ resetResult = FALSE;
635+
636+ /*
637+ * Check and see if we are processing an internal srb.
638+ */
639+ if (pChan->OriginalSrb)
640+ {
641+ pChan->CurrentSrb = pChan->OriginalSrb;
642+ pChan->OriginalSrb = NULL;
643+ }
644+
645+ /*
646+ * To avoid unexpected interrupts occurs during reset procedure.
647+ *
648+ * 1. Stop bus master operation.
649+ */
650+ outb(0, dma_base);
651+
652+ for (i = 0; i < 2; i++)
653+ {
654+ outb((u8)((i << 4) | 0xA0), pChan->io_ports[ATAPI_SELECT_OFFSET]);
655+
656+ /*
657+ * 2. Clear interrupts if there is any.
658+ */
659+ GetBaseStatus(pChan, status);
660+
661+ /*
662+ * 3. Disable interrupts.
663+ */
664+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[ATAPI_CONTROL_OFFSET]);
665+
666+ /*
667+ * 4. Clear interrupts again.
668+ */
669+ GetBaseStatus(pChan, status);
670+ }
671+
672+ /*
673+ * Check if request is in progress.
674+ */
675+ if (pChan->CurrentSrb)
676+ {
677+ /*
678+ * Complete outstanding request with SRB_STATUS_BUS_RESET.
679+ */
680+ srb.SrbStatus = SRB_STATUS_BUS_RESET;
681+
682+ /*
683+ * Clear request tracking fields.
684+ */
685+ pChan->CurrentSrb = NULL;
686+ pChan->WordsLeft = 0;
687+ pChan->DataBuffer = NULL;
688+
689+ /*
690+ * Indicate ready for next request.
691+ */
692+ TaskDone(pChan, &srb);
693+ }
694+
695+ /*
696+ * Clear expecting interrupt flag.
697+ */
698+ pChan->ExpectingInterrupt = FALSE;
699+ pChan->RDP = FALSE;
700+
701+ resetResult = IT8212ResetAdapter(pAdap);
702+
703+ /*
704+ * Set transfer modes after resetting the adapter.
705+ */
706+
707+ /*
708+ * Reenable interrupts.
709+ */
710+ for (i = 0; i < 4; i++)
711+ {
712+ outb((u8)(((i & 1) << 4) | 0xA0), pChan->io_ports[ATAPI_SELECT_OFFSET]);
713+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[ATAPI_CONTROL_OFFSET]);
714+ }
715+
716+ printk("AtapiResetController exit\n");
717+
718+} /* end AtapiResetController */
719+
720+/************************************************************************
721+ * IDE start read/write transfer.
722+ ************************************************************************/
723+void
724+IdeStartTransfer
725+(
726+ PChannel pChan,
727+ PSCSI_REQUEST_BLOCK Srb,
728+ u32 startingSector,
729+ u32 SectorNumber
730+)
731+{
732+
733+ u8 DiskId;
734+ u8 drvSelect;
735+ u8 bmClearStat;
736+ unsigned long dma_base;
737+ dprintk("IdeStartTransfer enter\n");
738+
739+ DiskId = (u8) Srb->TargetId;
740+ dma_base = pChan->dma_base;
741+
742+ /*
743+ * 48-bit support.
744+ */
745+ if ((startingSector + SectorNumber) > 0x0FFFFFFF)
746+ {
747+ /*
748+ * Select drive and set LBA mode.
749+ */
750+ outb((u8) (((DiskId & 0x1) << 4) | 0xA0 | 0x40),
751+ pChan->io_ports[IDE_SELECT_OFFSET]);
752+
753+ /*
754+ * Sector count register.
755+ */
756+ outb((u8) (SectorNumber >> 8), pChan->io_ports[IDE_NSECTOR_OFFSET]);
757+ outb((u8) SectorNumber, pChan->io_ports[IDE_NSECTOR_OFFSET]);
758+
759+ /*
760+ * LBA low register.
761+ */
762+ outb((u8) (startingSector >> 24), pChan->io_ports[IDE_LOCYL_OFFSET]);
763+ outb((u8) startingSector, pChan->io_ports[IDE_LOCYL_OFFSET]);
764+
765+ /*
766+ * LBA mid register.
767+ */
768+ outb((u8) 0, pChan->io_ports[IDE_MIDCYL_OFFSET]);
769+ outb((u8) (startingSector >> 8), pChan->io_ports[IDE_MIDCYL_OFFSET]);
770+
771+ /*
772+ * LBA high register.
773+ */
774+ outb((u8) 0, pChan->io_ports[IDE_HCYL_OFFSET]);
775+ outb((u8) (startingSector >> 16), pChan->io_ports[IDE_HCYL_OFFSET]);
776+
777+ /*
778+ * Start the IDE read/write DMA command.
779+ */
780+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
781+ {
782+ outb(IDE_COMMAND_READ_DMA_EXT, pChan->io_ports[IDE_COMMAND_OFFSET]);
783+ }
784+ else if (Srb->SrbFlags & SRB_FLAGS_DATA_OUT)
785+ {
786+ outb(IDE_COMMAND_WRITE_DMA_EXT, pChan->io_ports[IDE_COMMAND_OFFSET]);
787+ }
788+ }
789+ /*
790+ * 28-bit addressing.
791+ */
792+ else
793+ {
794+ /*
795+ * Select drive and set LBA mode.
796+ */
797+ drvSelect = (u8) (startingSector >> 24);
798+ drvSelect = drvSelect | (((u8) DiskId & 0x1) << 4) | 0x40 | 0xA0;
799+
800+ outb(drvSelect, pChan->io_ports[IDE_SELECT_OFFSET]);
801+ outb((u8) SectorNumber, pChan->io_ports[IDE_NSECTOR_OFFSET]);
802+ outb((u8) startingSector, pChan->io_ports[IDE_LOCYL_OFFSET]);
803+ outb((u8)(startingSector >> 8), pChan->io_ports[IDE_MIDCYL_OFFSET]);
804+ outb((u8)(startingSector >> 16), pChan->io_ports[IDE_HCYL_OFFSET]);
805+
806+ /*
807+ * Start the IDE read/write DMA command.
808+ */
809+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
810+ {
811+ outb(IDE_COMMAND_READ_DMA, pChan->io_ports[IDE_COMMAND_OFFSET]);
812+ }
813+ else if (Srb->SrbFlags & SRB_FLAGS_DATA_OUT)
814+ {
815+ outb(IDE_COMMAND_WRITE_DMA, pChan->io_ports[IDE_COMMAND_OFFSET]);
816+ }
817+ }
818+
819+ /*
820+ * Indicate expecting an interrupt.
821+ */
822+ pChan->ExpectingInterrupt = TRUE;
823+
824+ /*
825+ * Setup PRD table physical address.
826+ */
827+ outl(pChan->dmatable_dma, dma_base + 4);
828+
829+ /*
830+ * Read Bus Master status.
831+ */
832+ bmClearStat = inb(dma_base + 2);
833+ if (Srb->TargetId & 1)
834+ {
835+ bmClearStat = bmClearStat | BM_DRV1_DMA_CAPABLE |
836+ BM_STAT_FLG_INT | BM_STAT_FLG_ERR;
837+ }
838+ else
839+ {
840+ bmClearStat = bmClearStat | BM_DRV0_DMA_CAPABLE |
841+ BM_STAT_FLG_INT | BM_STAT_FLG_ERR;
842+ }
843+
844+ outb(0, dma_base);
845+
846+ /*
847+ * Clear INTR and ERROR flags.
848+ */
849+ outb(bmClearStat, dma_base + 2);
850+
851+ /*
852+ * Start DMA read/write.
853+ */
854+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
855+ {
856+ outb(BM_CMD_FLG_START | BM_CMD_FLG_WRTTOMEM, dma_base);
857+ }
858+ else if (Srb->SrbFlags & SRB_FLAGS_DATA_OUT)
859+ {
860+ outb(BM_CMD_FLG_START | BM_CMD_FLG_WRTTODSK, dma_base);
861+ }
862+
863+ dprintk("IdeStartTransfer exit\n");
864+
865+} /* end IdeStartTransfer */
866+
867+/************************************************************************
868+ * Setup the PRD table.
869+ ************************************************************************/
870+static int
871+IdeBuildSglist(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
872+{
873+
874+ int nents = 0;
875+ u32 bytesRemaining = Srb->DataTransferLength;
876+ unsigned char * virt_addr = Srb->DataBuffer;
877+ struct scatterlist * sg = pChan->sg_table;
878+
879+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
880+ {
881+ pChan->sg_dma_direction = PCI_DMA_FROMDEVICE;
882+ }
883+ else
884+ {
885+ pChan->sg_dma_direction = PCI_DMA_TODEVICE;
886+ }
887+
888+ /*
889+ * The upper layer will never give the memory more than 64K bytes.
890+ */
891+ memset(&sg[nents], 0, sizeof(*sg));
892+ sg[nents].dma_address = (dma_addr_t)virt_addr;
893+ sg[nents].length = bytesRemaining;
894+ nents++;
895+
896+ return pci_map_sg(pChan->pPciDev, sg, nents, pChan->sg_dma_direction);
897+
898+} /* end IdeBuildSglist */
899+
900+/************************************************************************
901+ * Prepares a dma request.
902+ ************************************************************************/
903+static int
904+IdeBuildDmaTable(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
905+{
906+
907+ unsigned long * table = pChan->dmatable_cpu;
908+ unsigned int count = 0;
909+ int i;
910+ struct scatterlist * sg;
911+
912+ i = IdeBuildSglist(pChan, Srb);
913+
914+ sg = pChan->sg_table;
915+ while (i && sg_dma_len(sg))
916+ {
917+ u32 cur_len;
918+ u32 cur_addr;
919+
920+ cur_addr = sg_dma_address(sg);
921+ cur_len = sg_dma_len(sg);
922+
923+ /*
924+ * Fill in the dma table, without crossing any 64kB boundaries.
925+ */
926+ while (cur_len)
927+ {
928+ if (count++ >= PRD_ENTRIES)
929+ {
930+ printk(KERN_WARNING "@@DMA table too small\n");
931+ }
932+ else
933+ {
934+ u32 xcount, bcount = 0x10000 - (cur_addr & 0xFFFF);
935+
936+ if (bcount > cur_len) bcount = cur_len;
937+ *table++ = cpu_to_le32(cur_addr);
938+ xcount = bcount & 0xFFFF;
939+ if (xcount == 0x0000)
940+ {
941+ /*
942+ * Most chipsets correctly interpret a length
943+ * of 0x0000 as 64KB, but at least one
944+ * (e.g. CS5530) misinterprets it as zero (!).
945+ * So here we break the 64KB entry into two
946+ * 32KB entries instead.
947+ */
948+ if (count++ >= PRD_ENTRIES)
949+ printk(KERN_WARNING "##DMA table too small\n");
950+
951+ *table++ = cpu_to_le32(0x8000);
952+ *table++ = cpu_to_le32(cur_addr + 0x8000);
953+ xcount = 0x8000;
954+ }
955+ *table++ = cpu_to_le32(xcount);
956+ cur_addr += bcount;
957+ cur_len -= bcount;
958+ }
959+ }
960+ sg++;
961+ i--;
962+ }
963+
964+ if (count)
965+ {
966+ *--table |= cpu_to_le32(0x80000000);
967+ return count;
968+ }
969+ else
970+ {
971+ printk(KERN_WARNING "Empty DMA table?\n");
972+ }
973+
974+ return count;
975+
976+} /* end IdeBuildDmaTable */
977+
978+/************************************************************************
979+ * Prepares a dma scatter/gather request.
980+ ************************************************************************/
981+static void
982+IdeBuildDmaSgTable(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
983+{
984+
985+ int use_sg = 0;
986+ int i;
987+ PPRD_TABLE_ENTRY pSG = (PPRD_TABLE_ENTRY)pChan->dmatable_cpu;
988+ struct scatterlist * sg = (struct scatterlist *)Srb->DataBuffer;
989+
990+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
991+ {
992+ pChan->sg_dma_direction = PCI_DMA_FROMDEVICE;
993+ }
994+ else
995+ {
996+ pChan->sg_dma_direction = PCI_DMA_TODEVICE;
997+ }
998+
999+ use_sg = pci_map_sg(pChan->pPciDev, Srb->DataBuffer, Srb->UseSg, pChan->sg_dma_direction);
1000+
1001+ for (i = 0; i < use_sg; i++)
1002+ {
1003+ pSG[i].PhysicalBaseAddress = sg_dma_address(&sg[i]);
1004+ pSG[i].ByteCount = sg_dma_len(&sg[i]);
1005+ pSG[i].EndOfTable = (i == use_sg - 1) ? SG_FLAG_EOT : 0;
1006+ }
1007+
1008+} /* end IdeBuildDmaSgTable */
1009+
1010+/************************************************************************
1011+ * Setup DMA table for channel.
1012+ ************************************************************************/
1013+static void
1014+IdeSetupDma(PChannel pChan, unsigned long dma_base, unsigned short num_ports)
1015+{
1016+
1017+ printk("Channel[%d] BM-DMA at 0x%lX-0x%lX\n", pChan->channel, dma_base,
1018+ dma_base + num_ports - 1);
1019+
1020+ /*
1021+ * Allocate IDE DMA buffer.
1022+ */
1023+ pChan->dmatable_cpu = pci_alloc_consistent(pChan->pPciDev,
1024+ PRD_ENTRIES * PRD_BYTES, &pChan->dmatable_dma);
1025+
1026+ if (pChan->dmatable_cpu == NULL)
1027+ {
1028+ printk("IdeSetupDma: allocate prd table failed.\n");
1029+ return;
1030+ }
1031+
1032+ memset(pChan->dmatable_cpu, 0, PRD_ENTRIES * PRD_BYTES);
1033+
1034+ /*
1035+ * Allocate SCATTER/GATHER table buffer.
1036+ */
1037+ pChan->sg_table = kmalloc(sizeof(struct scatterlist) * PRD_ENTRIES,
1038+ GFP_KERNEL);
1039+
1040+ if (pChan->sg_table == NULL)
1041+ {
1042+ printk("IdeSetupDma: allocate sg_table failed.\n");
1043+ pci_free_consistent(pChan->pPciDev, PRD_ENTRIES * PRD_BYTES,
1044+ pChan->dmatable_cpu, pChan->dmatable_dma);
1045+ return;
1046+ }
1047+
1048+ return;
1049+
1050+} /* end IdeSetupDma */
1051+
1052+/************************************************************************
1053+ * This will be only used in RAID mode.
1054+ ************************************************************************/
1055+void
1056+IT8212ReconfigChannel(PChannel pChan, u8 ArrayId, u8 Operation)
1057+{
1058+
1059+ u8 enableVirtualChannel;
1060+ struct pci_dev * pPciDev = pChan->pPciDev;
1061+
1062+ pci_read_config_byte(pPciDev, 0x43, &enableVirtualChannel);
1063+
1064+ if (Operation == DisableChannel)
1065+ {
1066+ enableVirtualChannel &= ~(1 << ArrayId);
1067+ printk("IT8212ReconfigChannel: disable channel %X\n", ArrayId);
1068+ }
1069+ else
1070+ {
1071+ enableVirtualChannel |= ~(1 << ArrayId);
1072+ printk("IT8212ReconfigChannel: enable channel %X\n", ArrayId);
1073+ }
1074+
1075+ printk("IT8212ReconfigChannel: channel enabled after set 0x%X\n",
1076+ enableVirtualChannel);
1077+
1078+ /*
1079+ * Set enabled virtual channels.
1080+ */
1081+ pci_write_config_byte(pPciDev, 0x43, enableVirtualChannel);
1082+
1083+} /* end IT8212ReconfigChannel */
1084+
1085+/************************************************************************
1086+ * Get the chip status. This is a vendor specific command. According to
1087+ * all of the device configurations, the BIOS then can consider the
1088+ * existing RAID configuration reasonable. If the existing RAID configur-
1089+ * ation is not reasonable, or if there is NO existing RAID configuration
1090+ * , the BIOS can ask the user to setup the RAID configuration. Finally,
1091+ * the BIOS or AP should send the SET CHIP STATUS to every virtual device.
1092+ * Only after receiving SET CHIP STATUS command, the corresponding virtual
1093+ * device will be active.
1094+ ************************************************************************/
1095+u8
1096+IT8212GetChipStatus(uioctl_t *ioc)
1097+{
1098+
1099+ u8 PriMasterIsNull = FALSE;
1100+ u8 statusByte;
1101+ u8 srbStatus;
1102+ PChannel pChan;
1103+ PITE_ADAPTER pAdap;
1104+ PHYSICAL_DISK_STATUS * pPhyDiskInfo;
1105+ dprintk("IT8212GetChipStatus enter\n");
1106+
1107+ /*
1108+ * Only support one controller now! In the future, we can pass the
1109+ * argument (user ioctl structure) to know which controller need to be
1110+ * identified.
1111+ */
1112+ pAdap = ite_adapters[0];
1113+ pChan = &pAdap->IDEChannel[0];
1114+
1115+ /*
1116+ * Allocate space for PHYSICAL_DISK_STATUS.
1117+ */
1118+ if ((pPhyDiskInfo = kmalloc(sizeof(PHYSICAL_DISK_STATUS) * 4, GFP_KERNEL)) == NULL)
1119+ {
1120+ printk("IT8212GetChipStatus: error kmalloc for PHYSCIAL_DISK_STATUS.\n");
1121+ return -ENOMEM;
1122+ }
1123+
1124+ memset(pPhyDiskInfo, 0, sizeof(PHYSICAL_DISK_STATUS));
1125+
1126+ /*
1127+ * Always send GET CHIP STATUS command to primary channel master device.
1128+ * Select device.
1129+ */
1130+ outb((u8) 0xA0, pChan->io_ports[IDE_SELECT_OFFSET]);
1131+
1132+ /*
1133+ * If primary master channel is not enabled, enable it.
1134+ */
1135+ statusByte = inb(pChan->io_ports[IDE_ALTERNATE_OFFSET]);
1136+ if (statusByte == 0)
1137+ {
1138+ PriMasterIsNull = TRUE;
1139+ IT8212ReconfigChannel(pChan, 0, EnableChannel);
1140+ }
1141+
1142+ /*
1143+ * Wait for device ready (Not BUSY and not DRQ)
1144+ */
1145+ WaitForDeviceReady(pChan, statusByte);
1146+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
1147+ (statusByte == 0))
1148+ {
1149+ printk("IT8212GetChipStatus: disk[0] not ready. status=0x%X\n",
1150+ statusByte);
1151+ srbStatus = SRB_STATUS_BUSY;
1152+ goto exit;
1153+ }
1154+
1155+ /*
1156+ * Disable interrupt to avoid the unexpected interrupt.
1157+ */
1158+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
1159+
1160+ /*
1161+ * Issue the command.
1162+ */
1163+ outb(IDE_COMMAND_GET_CHIP_STATUS, pChan->io_ports[IDE_COMMAND_OFFSET]);
1164+
1165+ /*
1166+ * Wait for BUSY = 0, DRQ = 1.
1167+ */
1168+ CheckBusyDrq(pChan, statusByte)
1169+ if (statusByte != 0x58)
1170+ {
1171+ printk("IT8212GetChipStatus: disk[0] return unexpected status after");
1172+ printk("issue command. status=0x%X\n", statusByte);
1173+ goto exit_error;
1174+ }
1175+
1176+ /*
1177+ * Read the physical disk info.
1178+ */
1179+ ReadBuffer(pChan, (unsigned short *)pPhyDiskInfo, 256);
1180+
1181+#if (0)
1182+ HexDump((unsigned char *)pPhyDiskInfo, 512);
1183+#endif
1184+
1185+ /*
1186+ * Copy physical disk info to user area.
1187+ */
1188+ copy_to_user((unsigned short *)ioc->data, (unsigned char *)pPhyDiskInfo, 512);
1189+
1190+ /*
1191+ * Check error.
1192+ */
1193+ WaitForCommandComplete(pChan, statusByte);
1194+
1195+ if (statusByte != IDE_STATUS_IDLE)
1196+ {
1197+ printk("IT8212GetChipStatus: disk[0] return unexpected status after");
1198+ printk("read data. status=0x%X\n", statusByte);
1199+ goto exit_error;
1200+ }
1201+
1202+ srbStatus = SRB_STATUS_SUCCESS;
1203+ goto exit;
1204+
1205+exit_error:
1206+
1207+ /*
1208+ * If fail, hard reset to avoid the DRQ status pending.
1209+ */
1210+ srbStatus = SRB_STATUS_ERROR;
1211+ IdeHardReset(pChan, statusByte);
1212+
1213+exit:
1214+
1215+ /*
1216+ * Reenable interrupt after command complete.
1217+ */
1218+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1219+
1220+ /*
1221+ * If primary master is null, disable primary master channel before we leave.
1222+ */
1223+ if (PriMasterIsNull)
1224+ {
1225+ IT8212ReconfigChannel(pChan, 0, DisableChannel);
1226+ }
1227+
1228+
1229+ dprintk("IT8212GetChipStatus exit\n");
1230+
1231+ return srbStatus;
1232+
1233+} /* end IT8212GetChipStatus */
1234+
1235+/************************************************************************
1236+ * Erase the partition table.
1237+ ************************************************************************/
1238+unsigned char
1239+IT8212ErasePartition(uioctl_t *pioc)
1240+{
1241+
1242+ unsigned char drvSelect;
1243+ unsigned char statusByte = 0;
1244+ unsigned char srbStatus;
1245+ unsigned char * buffer;
1246+ PRAID_CREATE_INFO createInfo = (PRAID_CREATE_INFO) pioc->data;
1247+ PITE_ADAPTER pAdap;
1248+ PChannel pChan;
1249+ printk("IT8212ErasePartition enter\n");
1250+
1251+ printk("createInfo->DiskArrayId = %d\n", createInfo->DiskArrayId);
1252+
1253+ if (createInfo->ErasePartition == 0 || (createInfo->RaidType == RAID_LEVEL_NODISK))
1254+ return SRB_STATUS_SUCCESS;
1255+
1256+ pAdap = ite_adapters[0];
1257+
1258+ if (createInfo->DiskArrayId < 2)
1259+ {
1260+ pChan = &pAdap->IDEChannel[0];
1261+ }
1262+ else
1263+ {
1264+ pChan = &pAdap->IDEChannel[1];
1265+ }
1266+
1267+ /*
1268+ * Allocate 512 bytes for buffer.
1269+ */
1270+ if ((buffer = kmalloc(512, GFP_KERNEL)) == NULL)
1271+ {
1272+ printk("IT8212ErasePartition: error kmalloc.\n");
1273+ return -ENOMEM;
1274+ }
1275+
1276+ memset(buffer, 0, 512);
1277+
1278+ /*
1279+ * Select device.
1280+ */
1281+ drvSelect = (((u8) createInfo->DiskArrayId & 0x1) << 4) | 0xA0 | 0x40;
1282+ outb(drvSelect, pChan->io_ports[IDE_SELECT_OFFSET]);
1283+
1284+ /*
1285+ * Wait for device ready (not BUSY and not DRQ).
1286+ */
1287+ WaitForDeviceReady(pChan, statusByte);
1288+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
1289+ (statusByte == 0))
1290+ {
1291+ printk("IT8212ErasePartition: disk[%d] not ready. status=0x%X\n",
1292+ createInfo->DiskArrayId, statusByte);
1293+ return SRB_STATUS_BUSY;
1294+ }
1295+
1296+ /*
1297+ * Disable interrupt to avoid the unexpected interrupt.
1298+ */
1299+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
1300+
1301+ /*
1302+ * Write LBA 0 (1 sector).
1303+ */
1304+ outb(1, pChan->io_ports[IDE_NSECTOR_OFFSET]);
1305+ outb(0, pChan->io_ports[IDE_LOCYL_OFFSET]);
1306+ outb(0, pChan->io_ports[IDE_MIDCYL_OFFSET]);
1307+ outb(0, pChan->io_ports[IDE_HCYL_OFFSET]);
1308+ outb(drvSelect, pChan->io_ports[IDE_SELECT_OFFSET]);
1309+ outb(IDE_COMMAND_WRITE_SECTOR, pChan->io_ports[IDE_COMMAND_OFFSET]);
1310+
1311+ /*
1312+ * Wait for BUSY = 0, DRQ = 1.
1313+ */
1314+ CheckBusyDrq(pChan, statusByte);
1315+ if (statusByte != 0x58)
1316+ {
1317+ printk("IT8212ErasePartition: disk[%d] error status. status=0x%X\n",
1318+ createInfo->DiskArrayId, statusByte);
1319+ goto exit_error;
1320+ }
1321+
1322+ /*
1323+ * Start erase partition table.
1324+ */
1325+ WriteBuffer(pChan, (unsigned short *)buffer, 256);
1326+
1327+ /*
1328+ * Check error.
1329+ */
1330+ WaitForCommandComplete(pChan, statusByte);
1331+
1332+ if (statusByte != IDE_STATUS_IDLE)
1333+ {
1334+ printk("IT8212ErasePartition: disk[%d] error status. status=0x%X\n",
1335+ createInfo->DiskArrayId, statusByte);
1336+ goto exit_error;
1337+ }
1338+
1339+ srbStatus = SRB_STATUS_SUCCESS;
1340+ goto exit;
1341+
1342+exit_error:
1343+
1344+ /*
1345+ * If failed, hard reset to avoid the DRQ status pending.
1346+ */
1347+ IdeHardReset(pChan, statusByte);
1348+ srbStatus = SRB_STATUS_ERROR;
1349+
1350+exit:
1351+
1352+ /*
1353+ * Reenable interrupt after command complete.
1354+ */
1355+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1356+
1357+ printk("IT8212ErasePartition exit\n");
1358+ return srbStatus;
1359+
1360+} /* end IT8212ErasePartition */
1361+
1362+/************************************************************************
1363+ *
1364+ ************************************************************************/
1365+u32
1366+IT8212TruncateReduentSectors
1367+(
1368+ u32 OriginalSectorCount,
1369+ u16 StripeSizeInKBytes
1370+)
1371+{
1372+
1373+ u16 stripeSizeInSector;
1374+
1375+ /*
1376+ * 0 means using default value (32 sectors).
1377+ */
1378+ if (StripeSizeInKBytes == 0)
1379+ {
1380+ stripeSizeInSector = 64 * 2;
1381+ }
1382+ else
1383+ {
1384+ stripeSizeInSector = StripeSizeInKBytes * 2;
1385+ }
1386+
1387+ return ((OriginalSectorCount / stripeSizeInSector) * stripeSizeInSector);
1388+
1389+
1390+} /* end IT8212TruncateReduentSectors */
1391+
1392+/************************************************************************
1393+ * Calculate the addressable sector for this RAID.
1394+ ************************************************************************/
1395+u32
1396+IT8212DiskArrayAddressableSector(unsigned char * DiskArrayCreateInfo)
1397+{
1398+
1399+ u8 DiskNo;
1400+ u8 NumOfDisks;
1401+ u32 MinDiskCapacity;
1402+ u32 ArrayCapacity;
1403+ PRAID_CREATE_INFO createInfo = (PRAID_CREATE_INFO) DiskArrayCreateInfo;
1404+
1405+ MinDiskCapacity = ArrayCapacity = NumOfDisks = 0;
1406+
1407+ printk("createInfo->AddressableSectors[0] = 0x%X\n", createInfo->AddressableSectors[0]);
1408+ printk("createInfo->AddressableSectors[1] = 0x%X\n", createInfo->AddressableSectors[1]);
1409+ printk("createInfo->AddressableSectors[2] = 0x%X\n", createInfo->AddressableSectors[2]);
1410+ printk("createInfo->AddressableSectors[3] = 0x%X\n", createInfo->AddressableSectors[3]);
1411+
1412+ for (DiskNo = 0; DiskNo < 4; DiskNo++)
1413+ {
1414+ /*
1415+ * If disk exist.
1416+ */
1417+ if ((createInfo->ContainingDisks >> DiskNo) & 0x1)
1418+ {
1419+ NumOfDisks += 1;
1420+ if (!MinDiskCapacity || (createInfo->AddressableSectors[DiskNo] <
1421+ MinDiskCapacity))
1422+ {
1423+ MinDiskCapacity = createInfo->AddressableSectors[DiskNo];
1424+ }
1425+ }
1426+ }
1427+
1428+ switch (createInfo->RaidType)
1429+ {
1430+ /*
1431+ * Containing 2 or 3 or 4 disks.
1432+ */
1433+ case RAID_LEVEL_0:
1434+ MinDiskCapacity = IT8212TruncateReduentSectors(MinDiskCapacity - 2,
1435+ createInfo->StripeSize);
1436+ ArrayCapacity = MinDiskCapacity * NumOfDisks;
1437+ break;
1438+
1439+ /*
1440+ * Containing 2 disks.
1441+ */
1442+ case RAID_LEVEL_1:
1443+ ArrayCapacity = MinDiskCapacity - 2;
1444+ break;
1445+
1446+ /*
1447+ * Containing 4 disks.
1448+ */
1449+ case RAID_LEVEL_10:
1450+ MinDiskCapacity = IT8212TruncateReduentSectors(MinDiskCapacity - 2,
1451+ createInfo->StripeSize);
1452+ ArrayCapacity = MinDiskCapacity * 2;
1453+ break;
1454+
1455+ /*
1456+ * Containing 2, 3, or 4 disks.
1457+ */
1458+ case RAID_LEVEL_JBOD:
1459+ for (DiskNo = 0; DiskNo < 4; DiskNo++)
1460+ {
1461+ if ((createInfo->ContainingDisks >> DiskNo) & 0x1)
1462+ {
1463+ ArrayCapacity = ArrayCapacity + (createInfo->AddressableSectors[DiskNo] - 2);
1464+ }
1465+ }
1466+ break;
1467+
1468+ /*
1469+ * Containing only 1 disk.
1470+ */
1471+ case RAID_LEVEL_NORMAL:
1472+ ArrayCapacity = MinDiskCapacity;
1473+ break;
1474+
1475+ }
1476+
1477+ return ArrayCapacity;
1478+
1479+} /* end IT8212DiskArrayAddressableSector */
1480+
1481+/************************************************************************
1482+ * Create a new array.
1483+ ************************************************************************/
1484+u8
1485+IT8212CreateDiskArray(uioctl_t *pioc)
1486+{
1487+
1488+ u8 i;
1489+ u8 subCommand = 0xFF;
1490+ u8 statusByte;
1491+ u8 dmaSupported;
1492+ u8 udmaSupported;
1493+ u8 srbStatus;
1494+ u8 PriMasterIsNull = FALSE;
1495+ u32 UserAddressableSectors;
1496+ void * buffer;
1497+ PChannel pChan;
1498+ PITE_ADAPTER pAdap;
1499+ PRAID_CREATE_INFO createInfo = (PRAID_CREATE_INFO)pioc->data;
1500+ PIDENTIFY_DATA2 identifyData;
1501+ PIT8212_SET_CHIP_STATUS_INFO setChipStatus;
1502+
1503+ static const u16 IT8212TimingTable[7] =
1504+ {
1505+ 0x3133, /* UDMA timimg register 01 */
1506+ 0x2121, /* UDMA timimg register 23 */
1507+ 0x9111, /* UDMA timimg register 45 */
1508+ 0x0091, /* UDMA timimg register 6 */
1509+ 0x3266, /* DMA timimg register 01 */
1510+ 0x0021, /* DMA timimg register 2 */
1511+ 0x0021 /* PIO timimg register */
1512+ };
1513+
1514+ static const u16 IT8212ClockTable[7] =
1515+ {
1516+ 0x0505, /* UDMA clock register 01 */
1517+ 0x0005, /* UDMA clock register 23 */
1518+ 0x0500, /* UDMA clock register 45 */
1519+ 0x0000, /* UDMA clock register 6 */
1520+ 0x0005, /* DMA clock register 01 */
1521+ 0x0005, /* DMA clock register 2 */
1522+ 0x0005 /* PIO clock register */
1523+ };
1524+
1525+ printk("IT8212CreateDiskArray enter\n");
1526+
1527+#if (MARK_DUMP_CREATE_INFO)
1528+ printk("createInfo->DiskArrayId = %d\n", createInfo->DiskArrayId);
1529+ printk("createInfo->ModelNumber = %s\n", createInfo->ModelNumber);
1530+ printk("createInfo->RaidType = %d\n", createInfo->RaidType);
1531+ printk("createInfo->ContainingDisks = %d\n", createInfo->ContainingDisks);
1532+ printk("createInfo->AutoRebuildEnable = %d\n", createInfo->AutoRebuildEnable);
1533+ printk("createInfo->StripeSize = %d\n", createInfo->StripeSize);
1534+ printk("createInfo->BootableDisk = %d\n", createInfo->BootableDisk);
1535+ printk("createInfo->NewlyCreated = %d\n", createInfo->NewlyCreated);
1536+ printk("createInfo->ErasePartition = %d\n", createInfo->ErasePartition);
1537+ printk("createInfo->DMASupported[0] = 0x%x\n", createInfo->DMASupported[0]);
1538+ printk("createInfo->DMASupported[1] = 0x%x\n", createInfo->DMASupported[1]);
1539+ printk("createInfo->DMASupported[2] = 0x%x\n", createInfo->DMASupported[2]);
1540+ printk("createInfo->DMASupported[3] = 0x%x\n", createInfo->DMASupported[3]);
1541+ printk("createInfo->UDMASupported[0] = 0x%x\n", createInfo->UDMASupported[0]);
1542+ printk("createInfo->UDMASupported[1] = 0x%x\n", createInfo->UDMASupported[1]);
1543+ printk("createInfo->UDMASupported[2] = 0x%x\n", createInfo->UDMASupported[2]);
1544+ printk("createInfo->UDMASupported[3] = 0x%x\n", createInfo->UDMASupported[3]);
1545+ printk("createInfo->AddressableSectors[0] = 0x%lX\n", createInfo->AddressableSectors[0]);
1546+ printk("createInfo->AddressableSectors[1] = 0x%lX\n", createInfo->AddressableSectors[1]);
1547+ printk("createInfo->AddressableSectors[2] = 0x%lX\n", createInfo->AddressableSectors[2]);
1548+ printk("createInfo->AddressableSectors[3] = 0x%lX\n", createInfo->AddressableSectors[3]);
1549+#endif
1550+
1551+ switch (createInfo->RaidType)
1552+ {
1553+ case RAID_LEVEL_0:
1554+ case RAID_LEVEL_1:
1555+ case RAID_LEVEL_10:
1556+ case RAID_LEVEL_JBOD:
1557+ case RAID_LEVEL_NORMAL:
1558+ subCommand = 0x50;
1559+ break;
1560+
1561+ case RAID_LEVEL_NODISK:
1562+ subCommand = 0x48;
1563+ break;
1564+ }
1565+
1566+ /*
1567+ * The command should be sent to virtual primary master.
1568+ */
1569+ pAdap = ite_adapters[0];
1570+ pChan = &pAdap->IDEChannel[0];
1571+
1572+ /*
1573+ * Allocate 512-bytes buffer.
1574+ */
1575+ if ((buffer = kmalloc(512, GFP_KERNEL)) == NULL)
1576+ {
1577+ printk("IT8212CreateDiskArray: error kmalloc.\n");
1578+ return -ENOMEM;
1579+ }
1580+
1581+ identifyData = (PIDENTIFY_DATA2) buffer;
1582+
1583+ /*
1584+ * 2003/05/08
1585+ * Remember the vendor specific parameters starts from word 129 not 128.
1586+ */
1587+ setChipStatus = (PIT8212_SET_CHIP_STATUS_INFO) (buffer + 258);
1588+
1589+ /*
1590+ * Configure to RAID or NORMAL.
1591+ */
1592+ if (subCommand == 0x50)
1593+ {
1594+ /*
1595+ * Zero identify data structure.
1596+ */
1597+ memset((unsigned char *) identifyData, 0, sizeof(IDENTIFY_DATA));
1598+
1599+ /*
1600+ * Fill up identify data.
1601+ */
1602+ memmove(identifyData->ModelNumber, createInfo->ModelNumber, 40);
1603+ memmove(identifyData->SerialNumber, &createInfo->SerialNumber, sizeof(RAID_SERIAL_NUMBER));
1604+
1605+ /*
1606+ * Set disk array virtual capacity.
1607+ */
1608+ UserAddressableSectors = IT8212DiskArrayAddressableSector(pioc->data);
1609+
1610+ printk("IT8212CreateDiskArray: array capacity = %X\n", UserAddressableSectors);
1611+
1612+ identifyData->Capacity_48bit_LOW = UserAddressableSectors;
1613+ identifyData->Capacity_48bit_HIGH = 0;
1614+
1615+ if (UserAddressableSectors > 0x0FFFFFFF)
1616+ {
1617+ identifyData->UserAddressableSectors = 0x0FFFFFFF;
1618+ }
1619+ else
1620+ {
1621+ identifyData->UserAddressableSectors = UserAddressableSectors;
1622+ }
1623+
1624+ /*
1625+ * Get DMA supported mode and UDMA supported mode.
1626+ */
1627+ dmaSupported = udmaSupported = 0xFF;
1628+
1629+ for (i = 0; i < 4; i++)
1630+ {
1631+ if ((createInfo->ContainingDisks >> i) & 1)
1632+ {
1633+ dmaSupported &= (u8) createInfo->DMASupported[i];
1634+ udmaSupported &= (u8) createInfo->UDMASupported[i];
1635+ }
1636+ }
1637+
1638+ identifyData->MultiWordDMASupport = dmaSupported;
1639+ identifyData->UltraDMASupport = udmaSupported;
1640+
1641+ /*
1642+ * Fill up SET CHIP STATUS data (word 129 - 153)
1643+ */
1644+ setChipStatus->RaidType = createInfo->RaidType;
1645+ setChipStatus->ContainingDisks = createInfo->ContainingDisks;
1646+ setChipStatus->UltraDmaTiming01 = IT8212TimingTable[0];
1647+ setChipStatus->UltraDmaTiming23 = IT8212TimingTable[1];
1648+ setChipStatus->UltraDmaTiming45 = IT8212TimingTable[2];
1649+ setChipStatus->UltraDmaTiming6 = IT8212TimingTable[3];
1650+ setChipStatus->MultiWordDmaTiming01 = IT8212TimingTable[4];
1651+ setChipStatus->UltraDmaTiming2 = IT8212TimingTable[5];
1652+ setChipStatus->PioTiming4 = IT8212TimingTable[6];
1653+ setChipStatus->AutoRebuildEnable = createInfo->AutoRebuildEnable;
1654+ setChipStatus->IdeClkUDma01 = IT8212ClockTable[0];
1655+ setChipStatus->IdeClkUDma23 = IT8212ClockTable[1];
1656+ setChipStatus->IdeClkUDma45 = IT8212ClockTable[2];
1657+ setChipStatus->IdeClkUDma6 = IT8212ClockTable[3];
1658+ setChipStatus->IdeClkMDma01 = IT8212ClockTable[4];
1659+ setChipStatus->IdeClkMDma2 = IT8212ClockTable[5];
1660+ setChipStatus->IdeClkPio4 = IT8212ClockTable[6];
1661+ setChipStatus->StripeSize = createInfo->StripeSize;
1662+ setChipStatus->BootableDisk = createInfo->BootableDisk;
1663+ setChipStatus->CheckHotSwapInterval = 0;
1664+ setChipStatus->TargetSourceDisk = createInfo->TargetSourceDisk;
1665+ setChipStatus->RebuildBlockSize = 0;
1666+ setChipStatus->ResetInterval1 = 0;
1667+ setChipStatus->ResetInterval2 = 0;
1668+ setChipStatus->RebuildRetryTimes = 0;
1669+ setChipStatus->NewlyCreated = createInfo->NewlyCreated;
1670+ }
1671+
1672+#if (MARK_DEBUG_DUMP_MEM)
1673+ HexDump(buffer, 512);
1674+#endif
1675+
1676+ /*
1677+ * There are some contrains of disk placement. AP will take care of it.
1678+ */
1679+
1680+ /*
1681+ * Select device.
1682+ */
1683+ outb((u8) 0xA0, pChan->io_ports[IDE_SELECT_OFFSET]);
1684+
1685+ /*
1686+ * If primary master channel is not enabled, enable it.
1687+ */
1688+ statusByte = inb(pChan->io_ports[IDE_CONTROL_OFFSET]);
1689+ if (statusByte == 0)
1690+ {
1691+ PriMasterIsNull = TRUE;
1692+ IT8212ReconfigChannel(pChan, 0, EnableChannel);
1693+ }
1694+
1695+ /*
1696+ * Wait for device ready (not BUSY and not DRQ)
1697+ */
1698+ WaitForDeviceReady(pChan, statusByte);
1699+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
1700+ (statusByte == 0))
1701+ {
1702+ printk("IT8212CreateDiskArray: disk[0] not ready. status=0x%X\n",
1703+ statusByte);
1704+ srbStatus = SRB_STATUS_BUSY;
1705+ goto exit;
1706+ }
1707+
1708+ /*
1709+ * Disable interrupt to avoid the unexpected interrupt.
1710+ */
1711+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
1712+
1713+ outb(subCommand, pChan->io_ports[IDE_FEATURE_OFFSET]);
1714+ outb(createInfo->DiskArrayId, pChan->io_ports[IDE_SELECT_OFFSET]);
1715+ outb(IDE_COMMAND_SET_CHIP_STATUS, pChan->io_ports[IDE_COMMAND_OFFSET]);
1716+
1717+ /*
1718+ * No disk (no data command protocol)
1719+ */
1720+ if (subCommand == 0x48)
1721+ {
1722+ WaitForCommandComplete(pChan, statusByte);
1723+ if (statusByte != IDE_STATUS_IDLE)
1724+ {
1725+ printk("IT8212CreateDiskArray: disk[0] return unexpected status after issue command.\n");
1726+ goto exit_error;
1727+ }
1728+
1729+ IT8212ReconfigChannel(pChan, createInfo->DiskArrayId, DisableChannel);
1730+ srbStatus = SRB_STATUS_SUCCESS;
1731+ goto exit;
1732+ }
1733+
1734+ /*
1735+ * Create RAID (PIO data out command protocol).
1736+ */
1737+ if (subCommand == 0x50)
1738+ {
1739+ /*
1740+ * Wait for BUSY=0, DRQ=1.
1741+ */
1742+ CheckBusyDrq(pChan, statusByte);
1743+ if (statusByte != 0x58)
1744+ {
1745+ printk("IT8212CreateDiskArray: disk[0] return unexpected status after issue command.\n");
1746+ goto exit_error;
1747+ }
1748+
1749+ WriteBuffer(pChan, buffer, 256);
1750+
1751+ /*
1752+ * Check error.
1753+ */
1754+ WaitForCommandComplete(pChan, statusByte);
1755+
1756+ if (statusByte != IDE_STATUS_IDLE)
1757+ {
1758+ printk("IT8212CreateDiskArray: disk[0] return unexpected status after issue command.\n");
1759+ goto exit_error;
1760+ }
1761+
1762+ IT8212ReconfigChannel(pChan, createInfo->DiskArrayId, EnableChannel);
1763+ srbStatus = SRB_STATUS_SUCCESS;
1764+ goto exit;
1765+ }
1766+
1767+exit_error:
1768+
1769+ /*
1770+ * If fail, hard reset to avoid the DRQ pending.
1771+ */
1772+ IdeHardReset(pChan, statusByte);
1773+ srbStatus = SRB_STATUS_ERROR;
1774+
1775+exit:
1776+
1777+ /*
1778+ * If primary master is null, and we are not configuring array 0. Disable
1779+ * primary master channel again.
1780+ */
1781+ if (PriMasterIsNull && createInfo->DiskArrayId)
1782+ {
1783+ IT8212ReconfigChannel(pChan, 0 , DisableChannel);
1784+ }
1785+
1786+ /*
1787+ * Reenable interrupt after command complete.
1788+ */
1789+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1790+
1791+ printk("IT8212CreateDiskArray exit\n");
1792+
1793+ return srbStatus;
1794+
1795+
1796+} /* end IT8212CreateDiskArray */
1797+
1798+/************************************************************************
1799+ * Return "virtual" drive 512 bytes identification data.
1800+ ************************************************************************/
1801+u8
1802+IT8212IssueIdentify(uioctl_t *pioc)
1803+{
1804+
1805+ u8 channum;
1806+ u8 devnum;
1807+ u8 statusByte;
1808+ u8 srbStatus;
1809+ PITE_ADAPTER pAdap;
1810+ PChannel pChan;
1811+
1812+ /*
1813+ * Only support one adapter now! In the future, we can pass the argument
1814+ * to know which adapter need to be identified.
1815+ */
1816+ pAdap = ite_adapters[0];
1817+
1818+ memset(pioc->data, 0, 512 * 4);
1819+
1820+ /*
1821+ * Two channels per controller.
1822+ */
1823+ for (channum = 0; channum < pAdap->num_channels; channum++)
1824+ {
1825+ pChan = &pAdap->IDEChannel[channum];
1826+
1827+ /*
1828+ * Two devices per channel.
1829+ */
1830+ for (devnum = 0; devnum < 2; devnum++)
1831+ {
1832+ /*
1833+ * Select device.
1834+ */
1835+ outb((u8)((devnum << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
1836+
1837+ /*
1838+ * Check if disk online?
1839+ */
1840+ statusByte = inb(pChan->io_ports[IDE_ALTERNATE_OFFSET]);
1841+ if ((statusByte & 0x40) != 0x40)
1842+ {
1843+ printk("IT8212IssueIdentify: disk[%d] is offline\n",
1844+ devnum + channum * 2);
1845+ continue;
1846+ }
1847+
1848+ /*
1849+ * Wait for device ready (Not busy and not DRQ)
1850+ */
1851+ WaitForDeviceReady(pChan, statusByte);
1852+
1853+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
1854+ (statusByte == 0))
1855+ {
1856+ printk("IT8212IssueIdentify: disk[%d] not ready. status=0x%X\n",
1857+ devnum + channum * 2, statusByte);
1858+ srbStatus = SRB_STATUS_BUSY;
1859+ goto exit;
1860+ }
1861+
1862+ /*
1863+ * Disable interrupt to avoid the unexpected interrupt.
1864+ */
1865+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
1866+
1867+ /*
1868+ * Issue command.
1869+ */
1870+ outb(IDE_COMMAND_IDENTIFY, pChan->io_ports[IDE_COMMAND_OFFSET]);
1871+
1872+ /*
1873+ * Wait for BUSY = 0 and DRQ = 1.
1874+ */
1875+ CheckBusyDrq(pChan, statusByte);
1876+ if (statusByte != 0x58)
1877+ {
1878+ printk("IT8212IssueIndetify: disk[%d] returns unexpedted status after issue command. status=0x%X\n",
1879+ devnum + channum * 2, statusByte);
1880+ goto error;
1881+ }
1882+
1883+ /*
1884+ * Read the identify data.
1885+ */
1886+ ReadBuffer(pChan, (unsigned short *)&pChan->FullIdentifyData, 256);
1887+
1888+ /*
1889+ * Then copy to user area.
1890+ * unsigned long copy_to_user(void *to, const void *from, unsigned long count).
1891+ */
1892+ copy_to_user((unsigned short *) (pioc->data + ((devnum + channum * 2) * 512)),
1893+ (unsigned short *)&pChan->FullIdentifyData, 256);
1894+
1895+ /*
1896+ * Check error after reading data.
1897+ */
1898+ WaitForCommandComplete(pChan, statusByte);
1899+ if (statusByte != IDE_STATUS_IDLE)
1900+ {
1901+ printk("IT8212IssueIdentify: disk[%d] returns unexpected status after read data. status=0x%X\n",
1902+ devnum + channum * 2, statusByte);
1903+ goto error;
1904+ }
1905+
1906+ } /* end for each device */
1907+
1908+ } /* end for each channel */
1909+
1910+ srbStatus = SRB_STATUS_SUCCESS;
1911+ goto exit;
1912+
1913+error:
1914+
1915+ /*
1916+ * If failed, hard reset to avoid the IRQ pending.
1917+ */
1918+ IdeHardReset(pChan, statusByte);
1919+ srbStatus = SRB_STATUS_ERROR;
1920+
1921+exit:
1922+
1923+ /*
1924+ * Reenable interrupt after command complete.
1925+ */
1926+ for (channum = 0; channum < pAdap->num_channels; channum++)
1927+ {
1928+ pChan = &pAdap->IDEChannel[channum];
1929+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1930+ }
1931+
1932+ return srbStatus;
1933+
1934+} /* end IT8212IssueIdentify */
1935+
1936+/************************************************************************
1937+ * Reset the controller.
1938+ ************************************************************************/
1939+static u8
1940+IT8212ResetAdapter(PITE_ADAPTER pAdap)
1941+{
1942+
1943+ u8 resetChannel[2];
1944+ u8 channel;
1945+ u8 device;
1946+ u8 status[4];
1947+ int i;
1948+ PChannel pChan;
1949+
1950+ /*
1951+ * First, perform ATAPI soft reset if ATAPI devices are attached.
1952+ */
1953+ for (channel = 0; channel < 2; channel++)
1954+ {
1955+ pChan = &pAdap->IDEChannel[channel];
1956+ resetChannel[channel] = FALSE;
1957+ for (device = 0; device < 2; device++)
1958+ {
1959+ if (pChan->DeviceFlags[device] & DFLAGS_DEVICE_PRESENT)
1960+ {
1961+ if (pChan->DeviceFlags[device] & DFLAGS_ATAPI_DEVICE)
1962+ {
1963+ printk("IT8212ResetAdapter: perform ATAPI soft reset (%d, %d)\n",
1964+ channel, device);
1965+ AtapiSoftReset(pChan, device);
1966+ }
1967+ else
1968+ {
1969+ resetChannel[channel] = TRUE;
1970+ }
1971+ }
1972+ }
1973+ }
1974+
1975+ /*
1976+ * If ATA device is present on this channel, perform channel reset.
1977+ */
1978+ for (channel = 0; channel < 2; channel++)
1979+ {
1980+ pChan = &pAdap->IDEChannel[channel];
1981+ if (resetChannel[channel])
1982+ {
1983+ printk("IT8212ResetAdapter: reset channel %d\n", channel);
1984+ outb(IDE_DC_RESET_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1985+ mdelay(50);
1986+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
1987+ }
1988+ }
1989+
1990+ /*
1991+ * Check device status after reset.
1992+ */
1993+ for (i = 0; i < 1000 * 1000; i++)
1994+ {
1995+ for (channel = 0; channel < 2; channel++)
1996+ {
1997+ pChan = &pAdap->IDEChannel[channel];
1998+ for (device = 0; device < 2; device++)
1999+ {
2000+ if (pChan->DeviceFlags[device] & DFLAGS_DEVICE_PRESENT)
2001+ {
2002+ outb((u8)((device << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
2003+ status[(channel * 2) + device] = inb(pChan->io_ports[IDE_COMMAND_OFFSET]);
2004+ }
2005+ else
2006+ {
2007+ status[(channel * 2) + device] = 0;
2008+ }
2009+ }
2010+ }
2011+
2012+ /*
2013+ * ATA device should present status 0x50 after reset.
2014+ * ATAPI device should present status 0 after reset.
2015+ */
2016+ if ((status[0] != IDE_STATUS_IDLE && status[0] != 0x0) ||
2017+ (status[1] != IDE_STATUS_IDLE && status[1] != 0x0) ||
2018+ (status[2] != IDE_STATUS_IDLE && status[2] != 0x0) ||
2019+ (status[3] != IDE_STATUS_IDLE && status[3] != 0x0))
2020+ {
2021+ udelay(30);
2022+ }
2023+ else
2024+ {
2025+ break;
2026+ }
2027+ }
2028+
2029+ if (i == 1000 * 1000)
2030+ {
2031+ printk("IT8212ResetAdapter Fail!\n");
2032+ printk("Device status after reset = [0x%x, 0x%x, 0x%x, 0x%x]\n",
2033+ status[0], status[1], status[2], status[3]);
2034+ return FALSE;
2035+ }
2036+ else
2037+ {
2038+ printk("IT8212ResetAdapter Success!\n");
2039+ return TRUE;
2040+ }
2041+
2042+} /* end IT8212ResetAdapter */
2043+
2044+/************************************************************************
2045+ * Rebuild disk array.
2046+ ************************************************************************/
2047+u8
2048+IT8212Rebuild(uioctl_t *pioc)
2049+{
2050+
2051+ u8 rebuildDirection;
2052+ u8 statusByte = 0;
2053+ PRAID_REBUILD_INFO apRebuildInfo = (PRAID_REBUILD_INFO) pioc->data;
2054+ PITE_ADAPTER pAdap;
2055+ PChannel pChan;
2056+ dprintk("IT8212Rebuild enter\n");
2057+
2058+ rebuildDirection = (apRebuildInfo->Resume << 4) | (apRebuildInfo->DestDisk << 2) |
2059+ apRebuildInfo->SrcDisk;
2060+
2061+ apRebuildInfo->Status = 0xFF;
2062+
2063+ pAdap = ite_adapters[0];
2064+
2065+ printk("IT8212Rebuild: diskArrayId=%d\n", apRebuildInfo->DiskArrayId);
2066+
2067+ if (apRebuildInfo->DiskArrayId < 2)
2068+ {
2069+ pChan = &pAdap->IDEChannel[0];
2070+ }
2071+ else
2072+ {
2073+ pChan = &pAdap->IDEChannel[1];
2074+ }
2075+
2076+ /*
2077+ * Selcet device.
2078+ */
2079+ outb((u8)((apRebuildInfo->DiskArrayId & 0x1) << 4 | 0xA0),
2080+ pChan->io_ports[IDE_SELECT_OFFSET]);
2081+
2082+ /*
2083+ * Wait for device ready (not BUSY and not DRQ).
2084+ */
2085+ WaitForDeviceReady(pChan, statusByte);
2086+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
2087+ (statusByte == 0))
2088+ {
2089+ apRebuildInfo->Status = REBUILD_ERR_DISK_BUSY;
2090+ printk("IT8212Rebuild: disk[%d] not ready. status=0x%X\n",
2091+ apRebuildInfo->DiskArrayId, statusByte);
2092+ return SRB_STATUS_BUSY;
2093+ }
2094+
2095+ /*
2096+ * Disable interrupt to avoid the unexpected interrupt.
2097+ */
2098+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
2099+
2100+ /*
2101+ * Give a direction.
2102+ */
2103+ outb(rebuildDirection, pChan->io_ports[IDE_FEATURE_OFFSET]);
2104+
2105+ /*
2106+ * Issue a REBUILD commmand.
2107+ */
2108+ outb(IDE_COMMAND_REBUILD, pChan->io_ports[IDE_COMMAND_OFFSET]);
2109+
2110+ /*
2111+ * Check for errors.
2112+ */
2113+ WaitForCommandComplete(pChan, statusByte);
2114+
2115+ /*
2116+ * Reenable interrupt after command complete.
2117+ */
2118+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
2119+
2120+ if (statusByte != IDE_STATUS_IDLE)
2121+ {
2122+ if (statusByte & IDE_STATUS_ERROR)
2123+ {
2124+ apRebuildInfo->Status = inb(pChan->io_ports[IDE_NSECTOR_OFFSET]);
2125+ printk("IT8212Rebuild: rebuild error. reason=0x%X\n", apRebuildInfo->Status);
2126+ }
2127+ return apRebuildInfo->Status;
2128+ }
2129+
2130+ dprintk("IT8212Rebuild exit\n");
2131+
2132+ return SRB_STATUS_PENDING;
2133+
2134+} /* end IT8212Rebuild */
2135+
2136+/************************************************************************
2137+ * Switch to DMA mode if necessary.
2138+ *
2139+ * offset 0x50 = PCI Mode Control Register
2140+ *
2141+ * Bit 0 = PCI Mode Select (1=firmware mode, 0=transparent mode)
2142+ * Bit 1 = Primary Channel IDE Clock Frequency Select (1=50, 0=66)
2143+ * Bit 2 = Secondary Channel IDE Clock Freq Select (1=50, 0=66)
2144+ * Bit 3 = Primary Channel Dev 0 Transfer Mode (1=MultiWord DMA, 0=Ultra DMA)
2145+ * Bit 4 = Primary Channel Dev 1 Transfer Mode (1=MultiWord DMA, 0=Ultra DMA)
2146+ * Bit 5 = Secondary Channel Dev 0 Transfer Mode (1=MultiWord DMA, 0=Ultra DMA)
2147+ * Bit 6 = Secondary Channel Dev 1 Transfer Mode (1=MultiWord DMA, 0=Ultra DMA)
2148+ * Bit 7 = PCI Mode Reset
2149+ ************************************************************************/
2150+void
2151+IT8212SwitchDmaMode(PChannel pChan, u8 DeviceId)
2152+{
2153+
2154+ u8 pciControl;
2155+ u8 channel;
2156+ u8 device;
2157+ u8 configByte = 0;
2158+ u8 RevisionID;
2159+ struct pci_dev * pPciDev = pChan->pPciDev;
2160+
2161+ /*
2162+ * These tables are for performance issue. Better formance than lots
2163+ * of "Shifts".
2164+ */
2165+ static const u8 dmaModeV10[4] = {0x18, 0x18, 0x60, 0x60};
2166+ static const u8 udmaModeV10[4] = {0xE7, 0xE7, 0x9F, 0x9F};
2167+ static const u8 ideClock[4] = {0xFD, 0xFD, 0xFB, 0xFB};
2168+
2169+ /*
2170+ * channel --> 0-1; device --> 0-1; DeviceId --> 0-3;
2171+ */
2172+ channel = DeviceId >> 1;
2173+ device = DeviceId & 1;
2174+
2175+ /*
2176+ * Do nothing if the mode switch is unnecessary.
2177+ */
2178+ if (!pChan->DoSwitch || pChan->ActiveDevice == DeviceId)
2179+ {
2180+ dprintk("IT8212SwitchDmaMode: do not need to switch mode!\n");
2181+ return;
2182+ }
2183+
2184+ printk("IT8212SwitchDmaMode: switch DMA mode for dev (%x)\n", DeviceId);
2185+
2186+ pci_read_config_byte(pPciDev, 0x50, &pciControl);
2187+ pci_read_config_byte(pPciDev, 0x08, &RevisionID);
2188+
2189+ /*
2190+ * Running on MULTIWORD_DMA mode.
2191+ */
2192+ if (pChan->DmaType[device] == USE_MULTIWORD_DMA)
2193+ {
2194+ /*
2195+ * Switch to DMA mode.
2196+ */
2197+ if (RevisionID == 0x10)
2198+ {
2199+ configByte = pciControl | dmaModeV10[DeviceId];
2200+ }
2201+ pci_write_config_byte(pPciDev, 0x50, configByte);
2202+ }
2203+ /*
2204+ * Running on ULTRA DMA mode.
2205+ */
2206+ else
2207+ {
2208+ /*
2209+ * Select UDMA mode.
2210+ */
2211+ configByte = pciControl;
2212+ if (RevisionID == 0x10)
2213+ {
2214+ configByte &= udmaModeV10[DeviceId];
2215+ }
2216+
2217+ /*
2218+ * Select IDE clock.
2219+ */
2220+ configByte = (configByte & ideClock[DeviceId]) |
2221+ (pChan->IdeClock[device] << (channel + 1));
2222+
2223+ pci_write_config_byte(pPciDev, 0x50, configByte);
2224+
2225+ /*
2226+ * Set UDMA timing.
2227+ *
2228+ * offset 0x56 = PCI Mode Primary Device 0 Ultra DMA Timing Registers
2229+ * offset 0x57 = PCI Mode Primary Device 1 Ultra DMA Timing Registers
2230+ * offset 0x5A = PCI Mode Secondary Device 0 Ultra DMA Timing Registers
2231+ * offset 0x5B = PCI Mode Secondary Device 1 Ultra DMA Timing Registers
2232+ */
2233+ if (RevisionID == 0x10)
2234+ {
2235+ configByte = pChan->UdmaTiming[device];
2236+ pci_write_config_byte(pPciDev, (u8) (0x56 + (channel * 4)), configByte);
2237+ pci_write_config_byte(pPciDev, (u8) (0x56 + (channel * 4) + 1), configByte);
2238+ }
2239+
2240+ /*
2241+ * Set PIO/DMA timing (Becasuse maybe the IDE clock is changed.)
2242+ */
2243+ configByte = pChan->PioDmaTiming[pChan->IdeClock[device]];
2244+ pci_write_config_byte(pPciDev, (u8) (0x54 + (channel * 4)), configByte);
2245+ }
2246+
2247+ /*
2248+ * Record the Active device on this channel
2249+ */
2250+ pChan->ActiveDevice = device;
2251+
2252+} /* end IT8212SwitchDmaMode */
2253+
2254+/************************************************************************
2255+ * IT8212 read/write routine.
2256+ ************************************************************************/
2257+u32
2258+IT8212ReadWrite(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
2259+{
2260+
2261+ u8 statusByte = 0;
2262+ u32 startingSector;
2263+ u32 sectorNumber;
2264+ u32 capacity;
2265+ PITE_ADAPTER pAdap;
2266+
2267+ if (Srb->TargetId >= 4)
2268+ {
2269+ pAdap = ite_adapters[1];
2270+ if (Srb->TargetId < 6) pChan = &pAdap->IDEChannel[0];
2271+ else pChan = &pAdap->IDEChannel[1];
2272+ }
2273+ else
2274+ {
2275+ pAdap = ite_adapters[0];
2276+ if (Srb->TargetId < 2) pChan = &pAdap->IDEChannel[0];
2277+ else pChan = &pAdap->IDEChannel[1];
2278+ }
2279+
2280+ /*
2281+ * Return error if overrun.
2282+ */
2283+ startingSector = ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte3 |
2284+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte2 << 8 |
2285+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte1 << 16 |
2286+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte0 << 24;
2287+
2288+ sectorNumber = (unsigned short) ((Srb->DataTransferLength + 0x1FF) / 0x200);
2289+
2290+ capacity = pChan->IdentifyData[Srb->TargetId & 0x1].UserAddressableSectors;
2291+ if (capacity == 0x0FFFFFFF)
2292+ {
2293+ capacity = pChan->IdentifyData[Srb->TargetId & 0x1].Capacity_48bit_LOW;
2294+ }
2295+
2296+ if ((startingSector + sectorNumber - 1) > capacity)
2297+ {
2298+ printk("IT8212ReadWrite: disk[%d] over disk size.\n", Srb->TargetId);
2299+ printk("capacity: %d. starting sector: %d. sector number: %d\n",
2300+ capacity, startingSector, sectorNumber);
2301+ return SRB_STATUS_ERROR;
2302+ }
2303+
2304+ /*
2305+ * Select device.
2306+ */
2307+ outb((u8)((Srb->TargetId & 0x1) << 4 | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
2308+
2309+ /*
2310+ * Wait for device ready (Not Busy and Not DRQ).
2311+ */
2312+ WaitForDeviceReady(pChan, statusByte);
2313+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
2314+ (statusByte == 0))
2315+ {
2316+ printk("IT8212ReadWrite: disk[%d] not ready. status=0x%x\n",
2317+ Srb->TargetId, statusByte);
2318+ return SRB_STATUS_BUSY;
2319+ }
2320+
2321+ /*
2322+ * First, switch to DMA or UDMA mode if running on bypass mode.
2323+ */
2324+ if (pAdap->bypass_mode)
2325+ {
2326+ IT8212SwitchDmaMode(pChan, Srb->TargetId);
2327+ }
2328+
2329+ /*
2330+ * Check the SCATTER/GATHER count. The upper will give the different
2331+ * memory address depend on whether use_sg is used or not.
2332+ */
2333+ if (Srb->UseSg == 0)
2334+ {
2335+ IdeBuildDmaTable(pChan, Srb);
2336+ }
2337+ else
2338+ {
2339+ IdeBuildDmaSgTable(pChan, Srb);
2340+ }
2341+
2342+ /*
2343+ * Start transfer the data.
2344+ */
2345+ IdeStartTransfer(pChan, Srb, startingSector, sectorNumber);
2346+
2347+ /*
2348+ * Wait for interrupt.
2349+ */
2350+ return SRB_STATUS_PENDING;
2351+
2352+} /* end IT8212ReadWrite */
2353+
2354+/************************************************************************
2355+ * Setup the transfer mode.
2356+ ************************************************************************/
2357+void
2358+IT8212SetTransferMode
2359+(
2360+ PChannel pChan,
2361+ u32 DiskId,
2362+ u8 TransferMode,
2363+ u8 ModeNumber
2364+)
2365+{
2366+
2367+ u8 statusByte = 0;
2368+
2369+ /*
2370+ * Select device.
2371+ */
2372+ outb((u8) ((DiskId & 0x1) << 4 | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
2373+
2374+ /*
2375+ * Wait for device ready (Not Busy and Not DRQ).
2376+ */
2377+ WaitForDeviceReady(pChan, statusByte);
2378+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ))
2379+ {
2380+ printk("IT8212SetTransferMode: disk[%d] not ready. status=0x%x\n",
2381+ DiskId, statusByte);
2382+ return;
2383+ }
2384+
2385+ /*
2386+ * Feature number ==> 03
2387+ *
2388+ * Mode contained in Sector Count Register.
2389+ *
2390+ * Bits(7:3) Bits(2:0) Mode
2391+ *
2392+ * 00000 000 PIO default mode
2393+ * 00000 001 PIO default mode, disable IORDY
2394+ * 00001 mode PIO flow control transfer mode
2395+ * 00010 mode Single Word DMA mode
2396+ * 00100 mode Multi-word DMA mode
2397+ * 01000 mode Ultra DMA mode
2398+ */
2399+ TransferMode |= ModeNumber;
2400+
2401+ outb(0x03, pChan->io_ports[IDE_FEATURE_OFFSET]);
2402+ outb(TransferMode, pChan->io_ports[IDE_NSECTOR_OFFSET]);
2403+ outb(0, pChan->io_ports[IDE_HCYL_OFFSET]);
2404+ outb(0, pChan->io_ports[IDE_MIDCYL_OFFSET]);
2405+ outb(IDE_COMMAND_SET_FEATURE, pChan->io_ports[IDE_COMMAND_OFFSET]);
2406+
2407+ /*
2408+ * Check error.
2409+ */
2410+ WaitForBaseCommandComplete(pChan, statusByte);
2411+
2412+ if ((statusByte != IDE_STATUS_IDLE) && (statusByte != 0))
2413+ {
2414+ printk("IT8212SetTransferMode: disk[%d]", DiskId);
2415+ printk("return unexpected status after issue command. 0x%x\n",
2416+ statusByte);
2417+ }
2418+
2419+} /* end IT8212SetTransferMode */
2420+
2421+/************************************************************************
2422+ * Set the best transfer mode for device.
2423+ ************************************************************************/
2424+void
2425+IT8212SetBestTransferMode(PITE_ADAPTER pAdap, PChannel pChan, u8 channel)
2426+{
2427+
2428+ u8 i;
2429+ u8 k;
2430+ u8 transferMode;
2431+ u8 modeNumber;
2432+ u8 pciControl;
2433+ u8 device;
2434+ u8 configByte;
2435+ u8 cableStatus[2] = {CABLE_40_PIN, CABLE_40_PIN};
2436+ u8 RevisionID;
2437+ struct pci_dev * pPciDev = pChan->pPciDev;
2438+ PIDENTIFY_DATA2 ideIdentifyData;
2439+
2440+ /*
2441+ * UDMA timing table for 66MHz clock.
2442+ * UDMA timing table for 50MHz clock.
2443+ * Best of IDE clock in this mode.
2444+ */
2445+ static const u8 udmaTiming[3][7] =
2446+ {
2447+ {0x44, 0x42, 0x31, 0x21, 0x11, 0x22, 0x11},
2448+ {0x33, 0x31, 0x21, 0x21, 0x11, 0x11, 0x11},
2449+ {IDE_CLOCK_66, IDE_CLOCK_50, IDE_CLOCK_66, IDE_CLOCK_66, IDE_CLOCK_66, IDE_CLOCK_50, IDE_CLOCK_66}
2450+ };
2451+
2452+ /*
2453+ * DMA timing table for 66 MHz clock.
2454+ * DMA timing table for 50 MHz clock.
2455+ */
2456+ static const u8 dmaTiming[2][3] =
2457+ {
2458+ {0x88, 0x32, 0x31},
2459+ {0x66, 0x22, 0x21}
2460+ };
2461+
2462+ /*
2463+ * PIO timing table for 66 MHz clock.
2464+ * PIO timing table for 50 MHz clock.
2465+ */
2466+ static const u8 pioTiming[2][5] =
2467+ {
2468+ {0xAA, 0xA3, 0xA1, 0x33, 0x31},
2469+ {0x88, 0x82, 0x81, 0x32, 0x21}
2470+ };
2471+
2472+ u8 pio_dma_timing[2][2][4] =
2473+ {
2474+ {{0, 0, 0, 0}, {0, 0, 0, 0}},
2475+ {{0, 0, 0, 0}, {0, 0, 0, 0}}
2476+ };
2477+
2478+ /*
2479+ * These tables are for performance issue. Better formance than lots
2480+ * of "Shifts".
2481+ */
2482+ static const u8 udmaModeV10[4] = {0xE7, 0xE7, 0x9F, 0x9F};
2483+ static const u8 dmaMode[4] = {0x08, 0x10, 0x20, 0x40};
2484+ static const u8 udmaMode[4] = {0xF7, 0xEF, 0xDF, 0xBF};
2485+ static const u8 ideClock[4] = {0xFD, 0xFD, 0xFB, 0xFB};
2486+
2487+ /*
2488+ * 2003/07/24
2489+ * If running on Firmware mode, get cable status from it.
2490+ */
2491+
2492+ for (i = 0; i < 2; i++)
2493+ {
2494+ /*
2495+ * The dafault of cable status is in PCI configuration 0x40.
2496+ */
2497+ cableStatus[i] = pChan->Cable80[i];
2498+
2499+ /*
2500+ * channel -->0 to 1.
2501+ * device -->0 or 1.
2502+ */
2503+ pChan->UseDma[i] = TRUE;
2504+ device = i & 1;
2505+
2506+ if (!(pChan->DeviceFlags[i] & DFLAGS_DEVICE_PRESENT) ||
2507+ (pChan->DeviceFlags[i] & DFLAGS_CONFIG_CHANGED))
2508+ {
2509+ pio_dma_timing[0][channel][device] = pio_dma_timing[0][channel][device + 2] = 0;
2510+ pio_dma_timing[1][channel][device] = pio_dma_timing[1][channel][device + 2] = 0;
2511+ continue;
2512+ }
2513+
2514+ /*
2515+ * Set PIO Mode.
2516+ */
2517+ ideIdentifyData = &pChan->IdentifyData[i];
2518+ if ((!(ideIdentifyData->ValidFieldIndicator & 0x02)) || (ideIdentifyData->AdvancedPIOModes == 0))
2519+ {
2520+ transferMode = PIO_FLOW_CONTROL;
2521+ modeNumber = 2;
2522+ }
2523+ else
2524+ {
2525+ transferMode = PIO_FLOW_CONTROL;
2526+ modeNumber = RaidGetHighestBit((u8) ideIdentifyData->AdvancedPIOModes) + 3;
2527+ }
2528+
2529+ IT8212SetTransferMode(pChan, i, transferMode, modeNumber);
2530+
2531+ /*
2532+ * Record the PIO timing for later use.(0 to 4)
2533+ */
2534+ pio_dma_timing[0][channel][device] = pioTiming[0][modeNumber];
2535+ pio_dma_timing[1][channel][device] = pioTiming[1][modeNumber];
2536+
2537+ /*
2538+ * Get the best transfer mode (maybe Ultra DMA or Multi-Word DMA).
2539+ */
2540+ ideIdentifyData = &pChan->IdentifyData[i];
2541+ if ((!(ideIdentifyData->ValidFieldIndicator & 0x04)) || (ideIdentifyData->UltraDMASupport == 0))
2542+ {
2543+ /*
2544+ * UltraDMA is not valid.
2545+ */
2546+ transferMode = MULTIWORD_DMA;
2547+ modeNumber = RaidGetHighestBit(ideIdentifyData->MultiWordDMASupport);
2548+ printk("The best transfer mode of Device[%d] is DMA-%d\n", i, modeNumber);
2549+ }
2550+ else
2551+ {
2552+ transferMode = ULTRA_DMA;
2553+ modeNumber = RaidGetHighestBit(ideIdentifyData->UltraDMASupport);
2554+ printk("The best transfer mode of Device[%d] is Ultra-%d\n", i, modeNumber);
2555+
2556+ /*
2557+ * If this is 40-pin cable. Limit to Ultra DMA mode 2.
2558+ */
2559+# if (0)
2560+ if ((cableStatus[i] == CABLE_40_PIN) && (modeNumber > 2))
2561+ {
2562+ printk("Reduce trans mode of Device[%d] to Ultra-2 for cable issue.\n", i);
2563+ modeNumber = 0x02;
2564+ }
2565+# endif
2566+ }
2567+
2568+ IT8212SetTransferMode(pChan, i, transferMode, modeNumber);
2569+
2570+ /*
2571+ * If running on ByPass mode, driver must take the responsibility to
2572+ * set the PIO/DMA/UDMA timing.
2573+ */
2574+ if (pAdap->bypass_mode)
2575+ {
2576+ pci_read_config_byte(pPciDev, 0x50, &pciControl);
2577+ pci_read_config_byte(pPciDev, 0x08, &RevisionID);
2578+
2579+ if (transferMode == ULTRA_DMA)
2580+ {
2581+ /*
2582+ * Set this channel to UDMA mode (not only the device).
2583+ */
2584+ if (RevisionID == 0x10)
2585+ {
2586+ configByte = pciControl & udmaModeV10[i + channel * 2];
2587+ }
2588+ else
2589+ {
2590+ configByte = pciControl & udmaMode[i + channel * 2];
2591+ }
2592+
2593+ /*
2594+ * Select IDE clock (50MHz or 66MHz).
2595+ */
2596+ configByte &= ideClock[i + channel * 2];
2597+ configByte |= (udmaTiming[2][modeNumber] << (channel + 1));
2598+
2599+ pci_write_config_byte(pPciDev, 0x50, configByte);
2600+
2601+ /*
2602+ * Set UDMA timing.
2603+ */
2604+ configByte = udmaTiming[udmaTiming[2][modeNumber]][modeNumber];
2605+ if (modeNumber == 5 || modeNumber == 6)
2606+ {
2607+ /*
2608+ * Enable UDMA mode 5/6
2609+ */
2610+ configByte |= UDMA_MODE_5_6;
2611+ }
2612+
2613+ /*
2614+ * Bug Bug. Fill these two fields into the same value.
2615+ */
2616+ if (RevisionID == 0x10)
2617+ {
2618+ pci_write_config_byte(pPciDev, (u8) (0x56 + (channel * 4)), configByte);
2619+ pci_write_config_byte(pPciDev, (u8) (0x56 + (channel * 4) + 1), configByte);
2620+ }
2621+ else
2622+ {
2623+ pci_write_config_byte(pPciDev, (u8) (0x56 + (channel * 4) + device), configByte);
2624+ }
2625+
2626+ /*
2627+ * Record the best UDMA mode for this device.
2628+ */
2629+ pChan->DmaType[i] = ULTRA_DMA;
2630+ pChan->IdeClock[i] = udmaTiming[2][modeNumber];
2631+ pChan->UdmaTiming[i] = configByte;
2632+ }
2633+ else if (transferMode == MULTIWORD_DMA)
2634+ {
2635+ /*
2636+ * If an ATAPI device with DMA mode, force it to run in PIO mode.
2637+ */
2638+ if (RevisionID == 0x10 && pChan->DeviceFlags[i] & DFLAGS_ATAPI_DEVICE)
2639+ {
2640+ pChan->UseDma[i] = FALSE;
2641+ }
2642+ else
2643+ {
2644+ /*
2645+ * Set this device to DMA mode.
2646+ */
2647+ configByte = pciControl | dmaMode[i + channel * 2];
2648+ pci_write_config_byte(pPciDev, 0x50, configByte);
2649+
2650+ /*
2651+ * Record DMA timing (for later use).
2652+ */
2653+ pio_dma_timing[0][channel][device + 2] = dmaTiming[0][modeNumber];
2654+ pio_dma_timing[1][channel][device + 2] = dmaTiming[1][modeNumber];
2655+ }
2656+ pChan->DmaType[i] = USE_MULTIWORD_DMA;
2657+ }
2658+ pChan->ActiveDevice = device;
2659+ }
2660+ }
2661+
2662+ /*
2663+ * Because each channel owns one PIO/DMA timimg register only, so we
2664+ * must set the timing to the slowest one to fit all. Really stupid H/W! :(
2665+ */
2666+ if (pAdap->bypass_mode)
2667+ {
2668+ /*
2669+ * Loop for the two IDE clocks (50 MHz and 66 MHz).
2670+ */
2671+ for (i = 0; i < 2; i++)
2672+ {
2673+ configByte = 0;
2674+ for (k = 0; k < 4; k++)
2675+ {
2676+ /*
2677+ * High part.
2678+ */
2679+ if ((pio_dma_timing[i][channel][k] & 0xF0) > (configByte & 0xF0))
2680+ {
2681+ configByte = (configByte & 0xF) | (pio_dma_timing[i][channel][k] & 0xF0);
2682+ }
2683+
2684+ /*
2685+ * Low part.
2686+ */
2687+ if ((pio_dma_timing[i][channel][k] & 0xF) > (configByte & 0xF))
2688+ {
2689+ configByte = (configByte & 0xF0) | (pio_dma_timing[i][channel][k] & 0xF);
2690+ }
2691+ }
2692+
2693+ /*
2694+ * Record the PIO/DMA timing for this channel.
2695+ */
2696+ pChan->PioDmaTiming[i] = configByte;
2697+ }
2698+
2699+ /*
2700+ * Set PIO/DMA timing register for each channel.
2701+ */
2702+ configByte = pChan->PioDmaTiming[(pciControl >> (channel + 1)) & 1];
2703+ if (configByte != 0)
2704+ {
2705+ pci_write_config_byte(pPciDev, (u8) (0x54 + (channel * 4)), configByte);
2706+ }
2707+
2708+ /*
2709+ * Check shall we do switch between the two devices
2710+ */
2711+ for (i = 0; i < 2; i++)
2712+ {
2713+ pChan->DoSwitch = TRUE;
2714+
2715+ /*
2716+ * Master is not present
2717+ */
2718+ if (!(pChan->DeviceFlags[i] & DFLAGS_DEVICE_PRESENT) ||
2719+ (pChan->DeviceFlags[i] & DFLAGS_CONFIG_CHANGED))
2720+ {
2721+ printk("Channel %x: master is not present. No switch mode.\n", channel);
2722+ pChan->DoSwitch = FALSE;
2723+ continue;
2724+ }
2725+
2726+ /*
2727+ * Slave is not present
2728+ */
2729+ if (!(pChan->DeviceFlags[i + 1] & DFLAGS_DEVICE_PRESENT) ||
2730+ (pChan->DeviceFlags[i + 1] & DFLAGS_CONFIG_CHANGED))
2731+ {
2732+ printk("Channel %x: slave is not present. No switch mode.\n", channel);
2733+ pChan->DoSwitch = FALSE;
2734+ continue;
2735+ }
2736+
2737+ /*
2738+ * If both devices are running on DMA mode, no switch.
2739+ */
2740+ if (pChan->DmaType[i] == USE_MULTIWORD_DMA && pChan->DmaType[i + 1] == USE_MULTIWORD_DMA)
2741+ {
2742+ printk("Channel %x: run on DMA mode only. No switch mode.\n", channel);
2743+ pChan->DoSwitch = FALSE;
2744+ continue;
2745+ }
2746+
2747+ /*
2748+ * No switch if the two devices are running on the same mode.
2749+ */
2750+ if ((pChan->DmaType[i] == pChan->DmaType[i + 1] ) &&
2751+ (pChan->UdmaTiming[i] == pChan->UdmaTiming[i + 1]) &&
2752+ (pChan->IdeClock[i] == pChan->IdeClock[i + 1] ))
2753+ {
2754+ printk("Channel %x: two dev run on the same mode. No switch mode.\n", channel);
2755+ pChan->DoSwitch = FALSE;
2756+ continue;
2757+ }
2758+
2759+ printk("Channel %x: switch mode if needed.\n", channel);
2760+ }
2761+ }
2762+
2763+} /* end IT8212SetBestTransferMode */
2764+
2765+/************************************************************************
2766+ * Initialize bypass(transparent) mode if BIOS is not ready.
2767+ ************************************************************************/
2768+u8
2769+IT8212InitBypassMode(struct pci_dev *pPciDev)
2770+{
2771+
2772+ /*
2773+ * Reset local CPU, and set BIOS not ready.
2774+ */
2775+ pci_write_config_byte(pPciDev, 0x5E, 0x01);
2776+
2777+ /*
2778+ * Set to bypass mode, and reset PCI bus.
2779+ */
2780+ pci_write_config_byte(pPciDev, 0x50, 0x00);
2781+
2782+ pci_write_config_word(pPciDev, 0x4, 0x0047);
2783+ pci_write_config_word(pPciDev, 0x40, 0xA0F3);
2784+
2785+ pci_write_config_dword(pPciDev,0x4C, 0x02040204);
2786+ pci_write_config_byte(pPciDev, 0x42, 0x36);
2787+ pci_write_config_byte(pPciDev, 0x0D, 0x00);
2788+
2789+ return TRUE;
2790+
2791+} /* end IT8212InitBypassMode */
2792+
2793+/************************************************************************
2794+ * This is the interrupt service routine for ATAPI IDE miniport driver.
2795+ * TURE if expecting an interrupt.
2796+ ************************************************************************/
2797+u8
2798+IT8212Interrupt(PChannel pChan, u8 bypass_mode)
2799+{
2800+
2801+ u8 statusByte;
2802+ u8 bmstatus;
2803+ u32 i;
2804+ unsigned long bmbase;
2805+ PSCSI_REQUEST_BLOCK Srb;
2806+
2807+ bmstatus = 0;
2808+ bmbase = pChan->dma_base;
2809+ Srb = pChan->CurrentSrb;
2810+
2811+ if (Srb == 0 || pChan->ExpectingInterrupt == 0)
2812+ {
2813+ dprintk("IT8212Interrupt: suspicious interrupt!\n");
2814+
2815+ /*
2816+ * Clear interrupt by reading status register.
2817+ */
2818+ outb((u8) 0xA0, pChan->io_ports[IDE_SELECT_OFFSET]);
2819+ GetBaseStatus(pChan, statusByte);
2820+ outb((u8) 0xB0, pChan->io_ports[IDE_SELECT_OFFSET]);
2821+ GetBaseStatus(pChan, statusByte);
2822+ outb(bmbase + 2, (u8) (inb(bmbase + 2) | BM_STAT_FLG_INT));
2823+ return FALSE;
2824+ }
2825+
2826+ /*
2827+ * To handle share IRQ condition. If the interrupt is not ours, just
2828+ * return FALSE.
2829+ */
2830+ bmstatus = inb(bmbase + 2);
2831+ if ((bmstatus & BM_STAT_FLG_INT) == 0)
2832+ {
2833+ dprintk("IT8212Interrupt: suspicious interrupt (int bit is not on)\n");
2834+ return FALSE;
2835+ }
2836+
2837+ /*
2838+ * Bug Fixed: All PIO access are blocked during bus master operation, so
2839+ * stop bus master operation before we try to access IDE registers.
2840+ */
2841+ if (bypass_mode)
2842+ {
2843+ outb(bmbase, 0);
2844+ }
2845+
2846+ /*
2847+ * Clear interrupt by reading status register.
2848+ */
2849+ GetBaseStatus(pChan, statusByte);
2850+ outb(bmbase + 2, (u8) (bmstatus | BM_STAT_FLG_INT));
2851+
2852+ /*
2853+ * Handle ATAPI interrupt.
2854+ */
2855+ if (pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_ATAPI_DEVICE)
2856+ {
2857+ return AtapiInterrupt(pChan);
2858+ }
2859+
2860+ pChan->ExpectingInterrupt = FALSE;
2861+
2862+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ))
2863+ {
2864+ /*
2865+ * Ensure BUSY and DRQ is non-asserted.
2866+ */
2867+ for (i = 0; i < 100; i++)
2868+ {
2869+ GetBaseStatus(pChan, statusByte);
2870+ if (!(statusByte & IDE_STATUS_BUSY) && !(statusByte & IDE_STATUS_DRQ))
2871+ {
2872+ break;
2873+ }
2874+ mdelay(5);
2875+ }
2876+
2877+ if (i == 100)
2878+ {
2879+ printk("IT8212Interrupt: disk[%x] return busy or drq status. status = 0x%x\n",
2880+ Srb->TargetId, statusByte);
2881+ return FALSE;
2882+ }
2883+ }
2884+
2885+ if (statusByte & IDE_STATUS_ERROR)
2886+ {
2887+ /*
2888+ * Stop bus master operation.
2889+ */
2890+ outb(bmbase, 0);
2891+
2892+ printk("IT8212Interrupt: error!\n");
2893+
2894+ /*
2895+ * Map error to specific SRB status and handle request sense.
2896+ */
2897+ Srb->SrbStatus = MapError(pChan, Srb);
2898+ }
2899+ else
2900+ {
2901+ Srb->SrbStatus = SRB_STATUS_SUCCESS;
2902+ }
2903+
2904+ pChan->CurrentSrb = NULL;
2905+
2906+ TaskDone(pChan, Srb);
2907+
2908+ return TRUE;
2909+
2910+} /* end IT8212Interrupt */
2911+
2912+/************************************************************************
2913+ * This is the interrupt service routine for ATAPI IDE miniport driver.
2914+ * TRUE if expecting an interrupt. Remember the ATAPI io registers are
2915+ * different from IDE io registers and this is for each channel not for
2916+ * entire controller.
2917+ ************************************************************************/
2918+static u8
2919+AtapiInterrupt(PChannel pChan)
2920+{
2921+
2922+ u32 wordCount;
2923+ u32 wordsThisInterrupt;
2924+ u32 status;
2925+ u32 i;
2926+ u8 statusByte;
2927+ u8 interruptReason;
2928+ u8 target_id;
2929+ PSCSI_REQUEST_BLOCK srb;
2930+ PITE_ADAPTER pAdap;
2931+
2932+ wordCount = 0;
2933+ wordsThisInterrupt = 256;
2934+ srb = pChan->CurrentSrb;
2935+ target_id = srb->TargetId;
2936+
2937+ if (target_id >= 4)
2938+ {
2939+ pAdap = ite_adapters[1];
2940+ if (target_id < 6) pChan = &pAdap->IDEChannel[0];
2941+ else pChan = &pAdap->IDEChannel[1];
2942+ }
2943+ else
2944+ {
2945+ pAdap = ite_adapters[0];
2946+ if (target_id < 2) pChan = &pAdap->IDEChannel[0];
2947+ else pChan = &pAdap->IDEChannel[1];
2948+ }
2949+
2950+ /*
2951+ * Clear interrupt by reading status.
2952+ */
2953+ GetBaseStatus(pChan, statusByte);
2954+
2955+ dprintk("AtapiInterrupt: entered with status (%x)\n", statusByte);
2956+
2957+ if (statusByte & IDE_STATUS_BUSY)
2958+ {
2959+ /*
2960+ * Ensure BUSY is non-asserted.
2961+ */
2962+ for (i = 0; i < 10; i++)
2963+ {
2964+ GetBaseStatus(pChan, statusByte);
2965+ if (!(statusByte & IDE_STATUS_BUSY))
2966+ {
2967+ break;
2968+ }
2969+ mdelay(5);
2970+ }
2971+
2972+ if (i == 10)
2973+ {
2974+ printk("AtapiInterrupt: BUSY on entry. Status %x\n", statusByte);
2975+ return FALSE;
2976+ }
2977+ }
2978+
2979+ /*
2980+ * Check for error conditions.
2981+ */
2982+ if (statusByte & IDE_STATUS_ERROR)
2983+ {
2984+ if (srb->Cdb[0] != SCSIOP_REQUEST_SENSE)
2985+ {
2986+ /*
2987+ * Fail this request.
2988+ */
2989+ status = SRB_STATUS_ERROR;
2990+ goto CompleteRequest;
2991+ }
2992+ }
2993+
2994+ /*
2995+ * Check reason for this interrupt.
2996+ */
2997+ interruptReason = (inb(pChan->io_ports[ATAPI_INTREASON_OFFSET]) & 0x3);
2998+ wordsThisInterrupt = 256;
2999+
3000+ if (interruptReason == 0x1 && (statusByte & IDE_STATUS_DRQ))
3001+ {
3002+ /*
3003+ * Write the packet.
3004+ */
3005+ printk("AtapiInterrupt: writing Atapi packet.\n");
3006+
3007+ /*
3008+ * Send CDB to device.
3009+ */
3010+ WriteBuffer(pChan, (unsigned short *)srb->Cdb, 6);
3011+
3012+ return TRUE;
3013+ }
3014+ else if (interruptReason == 0x0 && (statusByte & IDE_STATUS_DRQ))
3015+ {
3016+ /*
3017+ * Write the data.
3018+ */
3019+
3020+ /*
3021+ * Pick up bytes to transfer and convert to words.
3022+ */
3023+ wordCount = inb(pChan->io_ports[ATAPI_LCYL_OFFSET]);
3024+ wordCount |= inb(pChan->io_ports[ATAPI_HCYL_OFFSET]) << 8;
3025+
3026+ /*
3027+ * Covert bytes to words.
3028+ */
3029+ wordCount >>= 1;
3030+
3031+ if (wordCount != pChan->WordsLeft)
3032+ {
3033+ printk( "AtapiInterrupt: %d words requested; %d words xferred\n",
3034+ pChan->WordsLeft, wordCount);
3035+ }
3036+
3037+ /*
3038+ * Verify this makes sense.
3039+ */
3040+ if (wordCount > pChan->WordsLeft)
3041+ {
3042+ wordCount = pChan->WordsLeft;
3043+ }
3044+
3045+ /*
3046+ * Ensure that this is a write command.
3047+ */
3048+ if (srb->SrbFlags & SRB_FLAGS_DATA_OUT)
3049+ {
3050+ dprintk("AtapiInterrupt: write interrupt\n");
3051+ WaitOnBusy(pChan, statusByte);
3052+ WriteBuffer(pChan, pChan->DataBuffer, wordCount);
3053+
3054+# if (0)
3055+ /*
3056+ * Translate ATAPI data back to SCSI data if needed (don't
3057+ * convert if the original command is SCSIOP_MODE_SELECT10)
3058+ */
3059+ if (srb->Cdb[0] == ATAPI_MODE_SELECT && pchan->ConvertCdb)
3060+ {
3061+ Atapi2Scsi(pChan, srb, (char *)pChan->DataBuffer, wordCount << 1);
3062+ }
3063+# endif
3064+ }
3065+ else
3066+ {
3067+ printk("AtapiInterrupt: int reason %x, but srb is for a write %p.\n",
3068+ interruptReason, srb);
3069+
3070+ /*
3071+ * Fail this request.
3072+ */
3073+ status = SRB_STATUS_ERROR;
3074+ goto CompleteRequest;
3075+ }
3076+
3077+ /*
3078+ * Advance data buffer pointer and bytes left.
3079+ */
3080+ pChan->DataBuffer += wordCount;
3081+ pChan->WordsLeft -= wordCount;
3082+
3083+ return TRUE;
3084+ }
3085+ else if (interruptReason == 0x2 && (statusByte & IDE_STATUS_DRQ))
3086+ {
3087+ /*
3088+ * Pick up bytes to transfer and convert to words.
3089+ */
3090+ wordCount = inb(pChan->io_ports[ATAPI_LCYL_OFFSET]);
3091+ wordCount |= inb(pChan->io_ports[ATAPI_HCYL_OFFSET]) << 8;
3092+
3093+ /*
3094+ * Covert bytes to words.
3095+ */
3096+ wordCount >>= 1;
3097+ if (wordCount != pChan->WordsLeft)
3098+ {
3099+ printk("AtapiInterrupt: %d words requested; %d words xferred\n",
3100+ pChan->WordsLeft, wordCount);
3101+ }
3102+
3103+ /*
3104+ * Verify this makes sense.
3105+ */
3106+ if (wordCount > pChan->WordsLeft)
3107+ {
3108+ wordCount = pChan->WordsLeft;
3109+ }
3110+
3111+ /*
3112+ * Ensure that this is a read command.
3113+ */
3114+ if (srb->SrbFlags & SRB_FLAGS_DATA_IN)
3115+ {
3116+ dprintk("AtapiInterrupt: read interrupt\n");
3117+ WaitOnBusy(pChan, statusByte);
3118+ ReadBuffer(pChan, pChan->DataBuffer, wordCount);
3119+
3120+ /*
3121+ * From Windows DDK
3122+ * You should typically set the ANSI-approved Version field,
3123+ * in the INQUIRY response, to at least 2.
3124+ */
3125+ if (srb->Cdb[0] == SCSIOP_INQUIRY)
3126+ {
3127+ /*
3128+ * Maybe it's not necessary in Linux driver.
3129+ */
3130+ *((unsigned char *)pChan->DataBuffer + 2) = 2;
3131+ }
3132+ }
3133+ else
3134+ {
3135+ printk("AtapiInterrupt: int reason %x, but srb is for a read %p.\n",
3136+ interruptReason, srb);
3137+
3138+ /*
3139+ * Fail this request.
3140+ */
3141+ status = SRB_STATUS_ERROR;
3142+ goto CompleteRequest;
3143+ }
3144+
3145+ /*
3146+ * Advance data buffer pointer and bytes left.
3147+ */
3148+ pChan->DataBuffer += wordCount;
3149+ pChan->WordsLeft -= wordCount;
3150+
3151+ /*
3152+ * Check for read command complete.
3153+ */
3154+ if (pChan->WordsLeft == 0)
3155+ {
3156+ /*
3157+ * Work around to make many atapi devices return correct sector size
3158+ * of 2048. Also certain devices will have sector count == 0x00, check
3159+ * for that also.
3160+ */
3161+ if ((srb->Cdb[0] == 0x25) &&
3162+ ((pChan->IdentifyData[srb->TargetId & 1].GeneralConfiguration >> 8) & 0x1F) == 0x05)
3163+ {
3164+ pChan->DataBuffer -= wordCount;
3165+ if (pChan->DataBuffer[0] == 0x00)
3166+ {
3167+ *((u32 *) &(pChan->DataBuffer[0])) = 0xFFFFFF7F;
3168+ }
3169+
3170+ *((u32 *) &(pChan->DataBuffer[2])) = 0x00080000;
3171+ pChan->DataBuffer += wordCount;
3172+ }
3173+ }
3174+ return TRUE;
3175+ }
3176+ else if (interruptReason == 0x3 && !(statusByte & IDE_STATUS_DRQ))
3177+ {
3178+ dprintk("AtapiInterrupt: command complete!\n");
3179+ /*
3180+ * Command complete.
3181+ */
3182+ if (pChan->WordsLeft)
3183+ {
3184+ status = SRB_STATUS_DATA_OVERRUN;
3185+ }
3186+ else
3187+ {
3188+ status = SRB_STATUS_SUCCESS;
3189+ }
3190+
3191+CompleteRequest:
3192+
3193+ if (status == SRB_STATUS_ERROR)
3194+ {
3195+ /*
3196+ * Map error to specific SRB status and handle request sense.
3197+ */
3198+ printk("AtapiInterrupt error\n");
3199+
3200+ status = MapError(pChan, srb);
3201+
3202+ /*
3203+ * Try to recover it.... 2003/02/27
3204+ */
3205+
3206+
3207+ pChan->RDP = FALSE;
3208+ }
3209+ else
3210+ {
3211+ /*
3212+ * Wait for busy to drop.
3213+ */
3214+ for (i = 0; i < 30; i++)
3215+ {
3216+ GetStatus(pChan, statusByte);
3217+ if (!(statusByte & IDE_STATUS_BUSY))
3218+ {
3219+ break;
3220+ }
3221+ udelay(500);
3222+ }
3223+
3224+ if (i == 30)
3225+ {
3226+ /*
3227+ * Reset the controller.
3228+ */
3229+ printk("AtapiInterrupt: resetting due to BSY still up - %x.\n",
3230+ statusByte);
3231+ AtapiResetController(pAdap, pChan);
3232+ return TRUE;
3233+ }
3234+
3235+ /*
3236+ * Check to see if DRQ is still up.
3237+ */
3238+ if (statusByte & IDE_STATUS_DRQ)
3239+ {
3240+ for (i = 0; i < 500; i++)
3241+ {
3242+ GetStatus(pChan, statusByte);
3243+ if (!(statusByte & IDE_STATUS_DRQ))
3244+ {
3245+ break;
3246+ }
3247+ udelay(100);
3248+ }
3249+
3250+ if (i == 500)
3251+ {
3252+ /*
3253+ * Reset the controller.
3254+ */
3255+ printk("AtapiInterrupt: resetting due to DRQ still up - %x\n",
3256+ statusByte);
3257+ AtapiResetController(pAdap, pChan);
3258+ return TRUE;
3259+ }
3260+ }
3261+ }
3262+
3263+ /*
3264+ * Clear interrupt expecting flag.
3265+ */
3266+ pChan->ExpectingInterrupt = FALSE;
3267+
3268+ /*
3269+ * Sanity check that there is a current request.
3270+ */
3271+ if (srb != NULL)
3272+ {
3273+ /*
3274+ * Set status in SRB.
3275+ */
3276+ srb->SrbStatus = (u8)status;
3277+
3278+ /*
3279+ * Check for underflow.
3280+ */
3281+ if (pChan->WordsLeft)
3282+ {
3283+ /*
3284+ * Subtract out residual words and update if filemark hit,
3285+ * setmark hit , end of data, end of media...
3286+ */
3287+ if (!(pChan->DeviceFlags[srb->TargetId & 1] & DFLAGS_TAPE_DEVICE))
3288+ {
3289+ if (status == SRB_STATUS_DATA_OVERRUN)
3290+ {
3291+ srb->DataTransferLength -= pChan->WordsLeft * 2;
3292+ }
3293+ else
3294+ {
3295+ srb->DataTransferLength = 0;
3296+ }
3297+ }
3298+ else
3299+ {
3300+ srb->DataTransferLength -= pChan->WordsLeft * 2;
3301+ }
3302+ }
3303+
3304+ GetBaseStatus(pChan, statusByte);
3305+ if (pChan->RDP && !(statusByte & IDE_STATUS_DSC))
3306+ {
3307+ printk("-@@-\n");
3308+ }
3309+ else
3310+ {
3311+ /*
3312+ * Clear current SRB. Indicate ready for next request.
3313+ */
3314+ pChan->CurrentSrb = NULL;
3315+ TaskDone(pChan, srb);
3316+ }
3317+ }
3318+ else
3319+ {
3320+ printk("AtapiInterrupt: no SRB!\n");
3321+ }
3322+
3323+ return TRUE;
3324+ }
3325+ else
3326+ {
3327+ /*
3328+ * Unexpected int.
3329+ */
3330+ printk("AtapiInterrupt: unexpected interrupt. intReason %x. status %x.\n",
3331+ interruptReason, statusByte);
3332+ return FALSE;
3333+ }
3334+
3335+ return TRUE;
3336+
3337+} /* end AtapiInterrupt */
3338+
3339+/************************************************************************
3340+ * IRQ handler.
3341+ ************************************************************************/
3342+static irqreturn_t
3343+Irq_Handler(int irq, void *dev_id, struct pt_regs *regs)
3344+{
3345+
3346+ int handled = 0;
3347+ u8 i;
3348+ u8 j;
3349+ unsigned long flags;
3350+ PITE_ADAPTER pAdap;
3351+
3352+ spin_lock_irqsave(&io_request_lock, flags);
3353+
3354+ /*
3355+ * Scan for interrupt to process.
3356+ */
3357+ for (i = 0; i < NumAdapters; i++)
3358+ {
3359+ pAdap = ite_adapters[i];
3360+ if (pAdap->irq != irq) continue;
3361+
3362+ handled = 1;
3363+ for (j = 0; j < pAdap->num_channels; j++)
3364+ {
3365+ IT8212Interrupt(&pAdap->IDEChannel[j], pAdap->bypass_mode);
3366+ }
3367+ }
3368+
3369+ spin_unlock_irqrestore(&io_request_lock, flags);
3370+
3371+ return IRQ_RETVAL(handled);
3372+
3373+} /* end Irq_Handler */
3374+
3375+/************************************************************************
3376+ * This routine handles IDE Verify.
3377+ ************************************************************************/
3378+u8
3379+IdeVerify(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
3380+{
3381+
3382+ u8 drvSelect;
3383+ u8 statusByte = 0;
3384+ u32 startingSector;
3385+ u32 sectors;
3386+ u32 endSector;
3387+ u32 sectorCount;
3388+
3389+ /*
3390+ * Select device
3391+ */
3392+ outb((u8)((Srb->TargetId & 0x1) << 4 | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
3393+
3394+ /*
3395+ * Wait for device ready (Not BUSY and Not DRQ)
3396+ */
3397+ WaitForDeviceReady(pChan, statusByte);
3398+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
3399+ (statusByte == 0))
3400+ {
3401+ printk("IdeVerify: disk[%d] not ready. status=0x%x\n",
3402+ Srb->TargetId, statusByte);
3403+ return SRB_STATUS_BUSY;
3404+ }
3405+
3406+ /*
3407+ * Get the starting sector number from CDB.
3408+ */
3409+ startingSector = ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte3 |
3410+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte2 << 8 |
3411+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte1 << 16 |
3412+ ((PCDB)Srb->Cdb)->CDB10.LogicalBlockByte0 << 24;
3413+
3414+ sectorCount = (u16)(((PCDB)Srb->Cdb)->CDB10.TransferBlocksMsb << 8 |
3415+ ((PCDB)Srb->Cdb)->CDB10.TransferBlocksLsb );
3416+
3417+ endSector = startingSector + sectorCount;
3418+
3419+ /*
3420+ * Drive has these number sectors.
3421+ *
3422+ * 48-bit addressing.
3423+ */
3424+ if (endSector > 0x0FFFFFFF)
3425+ {
3426+ sectors = pChan->IdentifyData[Srb->TargetId & 0x01].Capacity_48bit_LOW;
3427+
3428+ printk("IdeVerify (48-bit): starting sector %d, Ending sector %d\n",
3429+ startingSector, endSector);
3430+
3431+ if (endSector > sectors)
3432+ {
3433+ /*
3434+ * Too big, round down.
3435+ */
3436+ printk("IdeVerify: truncating request to %x blocks\n",
3437+ sectors - startingSector - 1);
3438+
3439+ outb((u8)((sectors - startingSector - 1) >> 8),
3440+ pChan->io_ports[IDE_NSECTOR_OFFSET]);
3441+ outb((u8)(sectors - startingSector - 1),
3442+ pChan->io_ports[IDE_NSECTOR_OFFSET]);
3443+ }
3444+ else
3445+ {
3446+ /*
3447+ * Set up sector count register. Round up to next block.
3448+ */
3449+ if (sectorCount > 0xFFFF)
3450+ {
3451+ sectorCount = (u16)0xFFFF;
3452+ }
3453+
3454+ outb((u8)(sectorCount >> 8), pChan->io_ports[IDE_NSECTOR_OFFSET]);
3455+ outb((u8) sectorCount, pChan->io_ports[IDE_NSECTOR_OFFSET]);
3456+ }
3457+
3458+ /*
3459+ * Indicate expecting an interrupt.
3460+ */
3461+ pChan->ExpectingInterrupt = TRUE;
3462+
3463+ /*
3464+ * Set up LBA address
3465+ */
3466+ outb((u8) (startingSector >> 24), pChan->io_ports[IDE_LOCYL_OFFSET]);
3467+ outb((u8) startingSector, pChan->io_ports[IDE_LOCYL_OFFSET]);
3468+ outb((u8) 0, pChan->io_ports[IDE_MIDCYL_OFFSET]);
3469+ outb((u8) (startingSector >> 8), pChan->io_ports[IDE_MIDCYL_OFFSET]);
3470+ outb((u8) 0, pChan->io_ports[IDE_HCYL_OFFSET]);
3471+ outb((u8) (startingSector >> 16), pChan->io_ports[IDE_HCYL_OFFSET]);
3472+
3473+ /*
3474+ * Send verify command.
3475+ */
3476+ outb(IDE_COMMAND_READ_VERIFY_EXT, pChan->io_ports[IDE_COMMAND_OFFSET]);
3477+ }
3478+ /*
3479+ * 28-bit addressing
3480+ */
3481+ else
3482+ {
3483+ sectors = pChan->IdentifyData[Srb->TargetId & 0x01].UserAddressableSectors;
3484+
3485+ printk("IdeVerify: starting sector %d, ending sector %d\n",
3486+ startingSector, endSector);
3487+
3488+ if (endSector > sectors)
3489+ {
3490+ /*
3491+ * Too big, round down.
3492+ */
3493+ printk("IdeVerify: truncating request to %d blocks\n",
3494+ sectors - startingSector - 1);
3495+ outb((u8)(sectors - startingSector - 1),
3496+ pChan->io_ports[IDE_NSECTOR_OFFSET]);
3497+ }
3498+ else
3499+ {
3500+ /*
3501+ * Set up sector count register. Round up to next block.
3502+ */
3503+ if (sectorCount > 0xFF)
3504+ {
3505+ sectorCount = (u16)0xFF;
3506+ }
3507+ outb((u8)sectorCount, pChan->io_ports[IDE_NSECTOR_OFFSET]);
3508+ }
3509+
3510+ /*
3511+ * Indicate expecting an interrupt.
3512+ */
3513+ pChan->ExpectingInterrupt = TRUE;
3514+
3515+ /*
3516+ * Set up LBA address
3517+ */
3518+ outb((u8) startingSector, pChan->io_ports[IDE_LOCYL_OFFSET]);
3519+ outb((u8) (startingSector >> 8), pChan->io_ports[IDE_MIDCYL_OFFSET]);
3520+ outb((u8) (startingSector >> 16),pChan->io_ports[IDE_HCYL_OFFSET]);
3521+
3522+ /*
3523+ * Select driver, set LBA mode, set LBA (27:27)
3524+ */
3525+ drvSelect = (u8) (startingSector >> 24);
3526+ drvSelect = drvSelect | (((u8) Srb->TargetId & 0x1) << 4) | 0xA0 | 0x40;
3527+ outb(drvSelect, pChan->io_ports[IDE_SELECT_OFFSET]);
3528+
3529+ /*
3530+ * Send verify command.
3531+ */
3532+ outb(IDE_COMMAND_READ_VERIFY, pChan->io_ports[IDE_COMMAND_OFFSET]);
3533+ }
3534+
3535+ /*
3536+ * Wait for interrupt.
3537+ */
3538+ return SRB_STATUS_PENDING;
3539+
3540+} /* end IdeVerify */
3541+
3542+/************************************************************************
3543+ * This function is used to copy memory with overlapped destination and
3544+ * source. I guess ScsiPortMoveMemory cannot handle this well. Can it?
3545+ ************************************************************************/
3546+void
3547+IT8212MoveMemory(unsigned char * DestAddr, unsigned char * SrcAddr, u32 ByteCount)
3548+{
3549+
3550+ long i;
3551+
3552+ dprintk("IT8212MoveMemory: DestAddr=0x%p, SrcAddr=0x%p, ByteCount=0x%x\n",
3553+ DestAddr, SrcAddr, ByteCount);
3554+
3555+ if (DestAddr > SrcAddr)
3556+ {
3557+ /*
3558+ * If Destination Area is in the back of the Source Area, copy from
3559+ * the end of the requested area.
3560+ */
3561+ for (i = (ByteCount - 1); i >= 0; i--)
3562+ {
3563+ *(DestAddr + i) = *(SrcAddr + i);
3564+ }
3565+ }
3566+ else if (DestAddr < SrcAddr)
3567+ {
3568+ /*
3569+ * If Destination Area is in the front of the Source Area, copy from
3570+ * the begin of the requested area.
3571+ */
3572+ for (i = 0; i < ByteCount; i++)
3573+ {
3574+ *(DestAddr + i) = *(SrcAddr + i);
3575+ }
3576+ }
3577+
3578+} /* end IT8212MoveMemory */
3579+
3580+/************************************************************************
3581+ * Convert SCSI packet command to Atapi packet command.
3582+ ************************************************************************/
3583+void
3584+Scsi2Atapi(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
3585+{
3586+
3587+ /*
3588+ * Change the cdb length.
3589+ */
3590+ Srb->CdbLength = 12;
3591+
3592+ /*
3593+ * Because the block descripter and the header translation, we must
3594+ * adjust the requested length.
3595+ */
3596+ Srb->DataTransferLength -= 4;
3597+
3598+ /*
3599+ * Record the original CDB for later restore.
3600+ */
3601+ memcpy(pChan->TempCdb, Srb->Cdb, MAXIMUM_CDB_SIZE);
3602+
3603+ /*
3604+ * Indicate that we have performed Scsi2Atapi function. And we must
3605+ * restore the CDB back once the command complete.
3606+ */
3607+ pChan->ConvertCdb = TRUE;
3608+
3609+ switch (Srb->Cdb[0])
3610+ {
3611+ /*
3612+ * Convert the command from SCSIOP_MODE_SENSE (0x1A) to
3613+ * SCSIOP_MODE_SENSE10 (0x5A).
3614+ */
3615+ case SCSIOP_MODE_SENSE:
3616+ {
3617+ PSCSI_MODE_SENSE10 modeSense10 = (PSCSI_MODE_SENSE10) Srb->Cdb;
3618+ PSCSI_MODE_SENSE6 modeSense6 = (PSCSI_MODE_SENSE6) pChan->TempCdb;
3619+
3620+ /*
3621+ * 1. Zero out the whole CDB.
3622+ */
3623+ memset((unsigned char *)modeSense10, 0, MAXIMUM_CDB_SIZE);
3624+
3625+ /*
3626+ * 2. Fill in command code (SCSI_MODE_SENSE10).
3627+ */
3628+ modeSense10->OperationCode = ATAPI_MODE_SENSE;
3629+ modeSense10->Dbd = modeSense6->Dbd;
3630+ modeSense10->PageCode = modeSense6->PageCode;
3631+ modeSense10->Pc = modeSense6->Pc;
3632+ modeSense10->SubpageCode = modeSense6->SubpageCode;
3633+ modeSense10->AllocationLengthLsb = modeSense6->AllocationLength;
3634+ modeSense10->Control = modeSense6->Control;
3635+
3636+ /*
3637+ * 3. Becasuse we will fake a block descripter (-8), and
3638+ * translate the header (+4), so the requested length
3639+ * should be modified. That is, -8+4=-4 bytes.
3640+ */
3641+ modeSense10->AllocationLengthLsb -= 4;
3642+
3643+ break;
3644+ }
3645+
3646+ /*
3647+ * Convert the command from SCSIOP_MODE_SELECT (0x15) to
3648+ * SCSIOP_MODE_SELECT10 (0x5A).
3649+ */
3650+ case SCSIOP_MODE_SELECT:
3651+ {
3652+ u8 tempHeader[sizeof(PSCSI_MODE_PARAMETER_HEADER6)];
3653+ u16 byteCount;
3654+ PSCSI_MODE_PARAMETER_HEADER10 header10 =
3655+ (PSCSI_MODE_PARAMETER_HEADER10)Srb->DataBuffer;
3656+ PSCSI_MODE_PARAMETER_HEADER6 header6 =
3657+ (PSCSI_MODE_PARAMETER_HEADER6)tempHeader;
3658+ PSCSI_MODE_SELECT10 modeSelect10 = (PSCSI_MODE_SELECT10)Srb->Cdb;
3659+ PSCSI_MODE_SELECT6 modeSelect6 = (PSCSI_MODE_SELECT6)pChan->TempCdb;
3660+
3661+ /*
3662+ * First, convert the command block.
3663+ */
3664+
3665+ /*
3666+ * 1. Zero out the whole CDB.
3667+ */
3668+ memset((unsigned char *)modeSelect10, 0, MAXIMUM_CDB_SIZE);
3669+
3670+ /*
3671+ * 2. Fill in command code (SCSI_MODE_SENSE10).
3672+ */
3673+ modeSelect10->OperationCode = ATAPI_MODE_SELECT;
3674+ modeSelect10->SPBit = modeSelect6->SPBit;
3675+ modeSelect10->PFBit = modeSelect6->PFBit;
3676+ modeSelect10->ParameterListLengthLsb = modeSelect6->ParameterListLength;
3677+ modeSelect10->Control = modeSelect6->Control;
3678+
3679+ /*
3680+ * 3. Becasuse we will remove the block descripter (-8), and
3681+ * translate the header (+4), so the requested length should
3682+ * be modified. That is, -8+4=-4 bytes.
3683+ */
3684+ modeSelect10->ParameterListLengthLsb -= 4;
3685+
3686+ /*
3687+ * Second, convert the parameter page format from SCSI to ATAPI.
3688+ */
3689+
3690+ /*
3691+ * Remove the mode parameter data (except the header and the
3692+ * block descripter).
3693+ */
3694+ byteCount = modeSelect6->ParameterListLength -
3695+ sizeof(SCSI_MODE_PARAMETER_HEADER6) -
3696+ sizeof(SCSI_MODE_PARAMTER_BLOCK_DESCRIPTER);
3697+ if (byteCount > 0)
3698+ {
3699+ IT8212MoveMemory(
3700+ (unsigned char *) header10 + sizeof(SCSI_MODE_PARAMETER_HEADER10),
3701+ (unsigned char *) header10 + sizeof(SCSI_MODE_PARAMETER_HEADER6) +
3702+ sizeof(SCSI_MODE_PARAMTER_BLOCK_DESCRIPTER),
3703+ byteCount);
3704+ }
3705+
3706+ /*
3707+ * Keep the original header6 (4 bytes) in tempHeader for later use
3708+ */
3709+ memcpy(tempHeader, header10, sizeof(SCSI_MODE_PARAMETER_HEADER6));
3710+
3711+ /*
3712+ * Change the "mode parameter header(6)" to "mode parameter header(10)"
3713+ * Notice: Remove the block descripter in SCSI-2 command out. It
3714+ * won't be used in MMC.
3715+ */
3716+ memset((unsigned char *)header10, 0, sizeof(SCSI_MODE_PARAMETER_HEADER10));
3717+ header10->ModeDataLengthLsb = header6->ModeDataLength;
3718+ header10->MediumType = header6->MediumType;
3719+ header10->DeviceSpecificParameter = header6->DeviceSpecificParameter;
3720+ header10->BlockDescriptorLengthLsb = header6->BlockDescriptorLength;
3721+
3722+ /*
3723+ * ATAPI doesn't support block descripter, so remove it from the
3724+ * mode paramter.
3725+ */
3726+ header10->BlockDescriptorLengthLsb = 0;
3727+
3728+ break;
3729+ }
3730+ }
3731+
3732+} /* end Scsi2Atapi */
3733+
3734+/************************************************************************
3735+ * Send ATAPI packet command to device.
3736+ ************************************************************************/
3737+u32
3738+AtapiSendCommand(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
3739+{
3740+
3741+ u8 statusByte;
3742+ u8 byteCountLow;
3743+ u8 byteCountHigh;
3744+ u8 useDMA;
3745+ u8 RevisionID = 0;
3746+ u8 bmClearStat;
3747+ u32 flags;
3748+ int i;
3749+ unsigned long bmAddress = pChan->dma_base;
3750+ PITE_ADAPTER pAdap = ite_adapters[0];
3751+
3752+ dprintk("AtapiSendCommand: command 0x%X to device %d\n",
3753+ Srb->Cdb[0], Srb->TargetId);
3754+
3755+ /*
3756+ * Default use PIO mode.
3757+ */
3758+ useDMA = 0;
3759+ pChan->ConvertCdb = FALSE;
3760+
3761+ /*
3762+ * Make sure command is to ATAPI device.
3763+ */
3764+ flags = pChan->DeviceFlags[Srb->TargetId & 1];
3765+ if (flags & (DFLAGS_SANYO_ATAPI_CHANGER | DFLAGS_ATAPI_CHANGER))
3766+ {
3767+ if ((Srb->Lun) > (pChan->DiscsPresent[Srb->TargetId & 1] - 1))
3768+ {
3769+ /*
3770+ * Indicate no device found at this address.
3771+ */
3772+ return SRB_STATUS_SELECTION_TIMEOUT;
3773+ }
3774+ }
3775+ else if (Srb->Lun > 0)
3776+ {
3777+ return SRB_STATUS_SELECTION_TIMEOUT;
3778+ }
3779+
3780+ if (!(flags & DFLAGS_ATAPI_DEVICE))
3781+ {
3782+ return SRB_STATUS_SELECTION_TIMEOUT;
3783+ }
3784+
3785+ /*
3786+ * Select device 0 or 1.
3787+ */
3788+ outb((u8)(((Srb->TargetId & 0x1) << 4) | 0xA0),
3789+ pChan->io_ports[ATAPI_SELECT_OFFSET]);
3790+
3791+ /*
3792+ * Try to enable interrupt again. (2003/02/25)
3793+ */
3794+#if (0)
3795+ outb(0x00, pChan->io_ports[ATAPI_CONTROL_OFFSET]);
3796+#endif
3797+
3798+ /*
3799+ * Verify that controller is ready for next command.
3800+ */
3801+ GetStatus(pChan, statusByte);
3802+
3803+ dprintk("AtapiSendCommand: entered with status %x\n", statusByte);
3804+
3805+ if (statusByte & IDE_STATUS_BUSY)
3806+ {
3807+ printk("AtapiSendCommand: device busy (%x)\n", statusByte);
3808+ return SRB_STATUS_BUSY;
3809+ }
3810+
3811+ if (statusByte & IDE_STATUS_ERROR)
3812+ {
3813+ if (Srb->Cdb[0] != SCSIOP_REQUEST_SENSE)
3814+ {
3815+ printk("AtapiSendCommand: error on entry: (%x)\n", statusByte);
3816+
3817+ /*
3818+ * Read the error reg. to clear it and fail this request.
3819+ */
3820+ return MapError(pChan, Srb);
3821+ }
3822+ }
3823+
3824+ /*
3825+ * If a tape drive doesn't have DSC set and the last command is
3826+ * restrictive, don't send the next command. See discussion of
3827+ * Restrictive Delayed Process commands in QIC-157.
3828+ */
3829+ if ((!(statusByte & IDE_STATUS_DSC)) && (flags & DFLAGS_TAPE_DEVICE) && pChan->RDP)
3830+ {
3831+ mdelay(1);
3832+ printk("AtapiSendCommand: DSC not set. %x\n", statusByte);
3833+ return SRB_STATUS_BUSY;
3834+ }
3835+
3836+ if (statusByte & IDE_STATUS_DRQ)
3837+ {
3838+ printk("AtapiSendCommand: enter with status (%x). Attempt to recover.\n",
3839+ statusByte);
3840+
3841+ /*
3842+ * Try to drain the data that one preliminary device thinks that it has
3843+ * to transfer. Hopefully this random assertion of DRQ will not be present
3844+ * in production devices.
3845+ */
3846+ for (i = 0; i < 0x10000; i++)
3847+ {
3848+ GetStatus(pChan, statusByte);
3849+
3850+ if (statusByte & IDE_STATUS_DRQ)
3851+ {
3852+ /*
3853+ * Note: The data register is always referenced as a 16-bit word.
3854+ */
3855+ inw(pChan->io_ports[ATAPI_DATA_OFFSET]);
3856+ }
3857+ else
3858+ {
3859+ break;
3860+ }
3861+ }
3862+
3863+ if (i == 0x10000)
3864+ {
3865+ printk("AtapiSendCommand: DRQ still asserted.Status (%x)\n", statusByte);
3866+ printk("AtapiSendCommand: issued soft reset to Atapi device. \n");
3867+
3868+ AtapiSoftReset(pChan, Srb->TargetId);
3869+
3870+ /*
3871+ * Re-initialize Atapi device.
3872+ */
3873+ IssueIdentify(pChan, (Srb->TargetId & 1), IDE_COMMAND_ATAPI_IDENTIFY);
3874+
3875+ /*
3876+ * Inform the port driver that the bus has been reset.
3877+ */
3878+
3879+ /*
3880+ * Clean up device extension fields that AtapiStartIo won't.
3881+ */
3882+ pChan->ExpectingInterrupt = FALSE;
3883+ pChan->RDP = FALSE;
3884+
3885+ return SRB_STATUS_BUS_RESET;
3886+ }
3887+ }
3888+
3889+ if (flags & (DFLAGS_SANYO_ATAPI_CHANGER | DFLAGS_ATAPI_CHANGER))
3890+ {
3891+ /*
3892+ * As the cdrom driver sets the LUN field in the cdb, it must be removed.
3893+ */
3894+ Srb->Cdb[1] &= ~0xE0;
3895+
3896+ if ((Srb->Cdb[0] == SCSIOP_TEST_UNIT_READY) && (flags & DFLAGS_SANYO_ATAPI_CHANGER))
3897+ {
3898+ /*
3899+ * Torisan changer. TUR's are overloaded to be platter switches.
3900+ */
3901+ Srb->Cdb[7] = Srb->Lun;
3902+ }
3903+ }
3904+
3905+ /*
3906+ * Convert SCSI to ATAPI commands if needed
3907+ */
3908+ switch (Srb->Cdb[0])
3909+ {
3910+ case SCSIOP_MODE_SENSE:
3911+ case SCSIOP_MODE_SELECT:
3912+ if (flags & DFLAGS_ATAPI_DEVICE)
3913+ {
3914+ Scsi2Atapi(pChan, Srb);
3915+ }
3916+ break;
3917+ }
3918+
3919+ if (pChan->UseDma[Srb->TargetId & 1])
3920+ {
3921+ switch (Srb->Cdb[0])
3922+ {
3923+ case SCSIOP_READ: /* (0x28) */
3924+ case 0xA8: /* READ(12) */
3925+ case SCSIOP_READ_CD:
3926+
3927+ if (Srb->DataTransferLength == 0)
3928+ {
3929+ break;
3930+ }
3931+
3932+ /*
3933+ * First, switch to DMA or UDMA mode if running on Bypass mode.
3934+ */
3935+ if (pAdap->bypass_mode)
3936+ {
3937+ IT8212SwitchDmaMode(pChan, Srb->TargetId);
3938+ }
3939+
3940+ /*
3941+ * Check the SCATTER/GATHER count. The upper will give the
3942+ * different memory address depend on whether use_sg is used
3943+ * or not.
3944+ */
3945+ if (Srb->UseSg == 0)
3946+ {
3947+ IdeBuildDmaTable(pChan, Srb);
3948+ }
3949+ else
3950+ {
3951+ IdeBuildDmaSgTable(pChan, Srb);
3952+ }
3953+
3954+ bmClearStat = inb(bmAddress + 2);
3955+ if (Srb->TargetId & 0x01)
3956+ {
3957+ bmClearStat = bmClearStat | BM_DRV1_DMA_CAPABLE |
3958+ BM_STAT_FLG_INT | BM_STAT_FLG_ERR;
3959+ }
3960+ else
3961+ {
3962+ bmClearStat = bmClearStat | BM_DRV0_DMA_CAPABLE |
3963+ BM_STAT_FLG_INT | BM_STAT_FLG_ERR;
3964+ }
3965+
3966+ useDMA = 1;
3967+
3968+ outb(0, bmAddress);
3969+
3970+ /*
3971+ * Setup PRD table physical address.
3972+ */
3973+ outl(pChan->dmatable_dma, bmAddress + 4);
3974+
3975+ /*
3976+ * Clear the status.
3977+ */
3978+ outb(bmClearStat, bmAddress + 2);
3979+
3980+ break;
3981+ } /* end switch (Srb->Cdb[0]) */
3982+ }
3983+
3984+ /*
3985+ * Set data buffer pointer and words left.
3986+ */
3987+ pChan->DataBuffer = (unsigned short *)Srb->DataBuffer;
3988+
3989+ if (useDMA)
3990+ {
3991+ pChan->WordsLeft = 0;
3992+ }
3993+ else
3994+ {
3995+ pChan->WordsLeft = Srb->DataTransferLength / 2;
3996+ }
3997+
3998+ outb((u8)(((Srb->TargetId & 0x1) << 4) | 0xA0),
3999+ pChan->io_ports[ATAPI_SELECT_OFFSET]);
4000+
4001+ WaitOnBusy(pChan, statusByte);
4002+
4003+ /*
4004+ * Write transfer byte count to registers.
4005+ */
4006+ byteCountLow = (u8)(Srb->DataTransferLength & 0xFF);
4007+ byteCountHigh = (u8)(Srb->DataTransferLength >> 8);
4008+
4009+ if (Srb->DataTransferLength >= 0x10000)
4010+ {
4011+ byteCountLow = byteCountHigh = 0xFF;
4012+ }
4013+
4014+ outb(byteCountLow, pChan->io_ports[ATAPI_LCYL_OFFSET]);
4015+ outb(byteCountHigh, pChan->io_ports[ATAPI_HCYL_OFFSET]);
4016+ outb(0, pChan->io_ports[ATAPI_INTREASON_OFFSET]);
4017+ outb(0, pChan->io_ports[ATAPI_UNUSED1_OFFSET]);
4018+ outb(useDMA, pChan->io_ports[ATAPI_FEATURE_OFFSET]);
4019+
4020+ WaitOnBusy(pChan, statusByte);
4021+
4022+ if (flags & DFLAGS_INT_DRQ)
4023+ {
4024+ /*
4025+ * This device interrupts when ready to receive the packet.
4026+ *
4027+ * Write ATAPI packet command.
4028+ */
4029+ outb(IDE_COMMAND_ATAPI_PACKET, pChan->io_ports[IDE_COMMAND_OFFSET]);
4030+
4031+ printk("AtapiSendCommand: wait for int. to send packet. status (%x)\n",
4032+ statusByte);
4033+
4034+ pChan->ExpectingInterrupt = TRUE;
4035+
4036+ return SRB_STATUS_PENDING;
4037+ }
4038+ else
4039+ {
4040+ /*
4041+ * Write ATAPI packet command.
4042+ */
4043+ outb(IDE_COMMAND_ATAPI_PACKET, pChan->io_ports[IDE_COMMAND_OFFSET]);
4044+
4045+ /*
4046+ * Wait for DRQ.
4047+ */
4048+ WaitOnBusy(pChan, statusByte);
4049+ WaitForDrq(pChan, statusByte);
4050+
4051+ if (!(statusByte & IDE_STATUS_DRQ))
4052+ {
4053+ printk("AtapiSendCommand: DRQ never asserted (%x)\n", statusByte);
4054+ return SRB_STATUS_ERROR;
4055+ }
4056+ }
4057+
4058+ /*
4059+ * Need to read status register.
4060+ */
4061+ GetBaseStatus(pChan, statusByte);
4062+
4063+ /*
4064+ * Send CDB to device.
4065+ * After detecting DRQ, the host writes the 12 bytes(6 words) of Command
4066+ * to the Data Register.
4067+ */
4068+ WaitOnBusy(pChan, statusByte);
4069+ WriteBuffer(pChan, (unsigned short *)Srb->Cdb, 6);
4070+
4071+ /*
4072+ * If running on DMA mode, start BUS MASTER operation.
4073+ */
4074+ if (useDMA)
4075+ {
4076+ /*
4077+ * If SCSIOP_READ command is sent to an Audio CD, error will be
4078+ * returned. But the error will be blocked by our controller if bus
4079+ * master operation started. So wait for a short period to check if
4080+ * error occurs. If error occurs, don't start bus master operation.
4081+ */
4082+ if (RevisionID == 0x10)
4083+ {
4084+ for (i = 0; i < 500; i++)
4085+ {
4086+ udelay(1);
4087+ statusByte = inb(bmAddress + 2);
4088+ if (statusByte & BM_STAT_FLG_INT)
4089+ {
4090+ /*
4091+ * If error occurs, give up this round.
4092+ */
4093+ printk("AtapiSendCommand: command failed. Don't start bus master.");
4094+ printk("status=%x, i=%d\n", statusByte, i);
4095+
4096+ pChan->ExpectingInterrupt = TRUE;
4097+ return SRB_STATUS_PENDING;
4098+ }
4099+ }
4100+ }
4101+
4102+ if (Srb->SrbFlags & SRB_FLAGS_DATA_IN)
4103+ {
4104+ outb(BM_CMD_FLG_START | BM_CMD_FLG_WRTTOMEM, bmAddress);
4105+ }
4106+ else if (Srb->SrbFlags & SRB_FLAGS_DATA_OUT)
4107+ {
4108+ outb(BM_CMD_FLG_START | BM_CMD_FLG_WRTTODSK, bmAddress);
4109+ }
4110+ } /* end if (useDMA) */
4111+
4112+ /*
4113+ * Indicate expecting an interrupt and wait for it.
4114+ */
4115+ pChan->ExpectingInterrupt = TRUE;
4116+
4117+ return SRB_STATUS_PENDING;
4118+
4119+} /* end AtapiSendCommand */
4120+
4121+/************************************************************************
4122+ * Program ATA registers for IDE disk transfer.
4123+ ************************************************************************/
4124+static u32
4125+IdeSendCommand(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
4126+{
4127+
4128+ u8 statusByte;
4129+ u32 status;
4130+ u32 i;
4131+ Scsi_Cmnd * pREQ;
4132+ unsigned char * request_buffer;
4133+ PINQUIRYDATA inquiryData;
4134+
4135+ pREQ = Srb->pREQ;
4136+ status = SRB_STATUS_SUCCESS;
4137+ statusByte = 0;
4138+
4139+ switch (Srb->Cdb[0])
4140+ {
4141+ case SCSIOP_INQUIRY:
4142+ dprintk("SCSIOP_INQUIRY\n");
4143+
4144+ /*
4145+ * Filter out all TIDs but 0 and 1 since this is an IDE interface
4146+ * which support up to two devices.
4147+ */
4148+ if ((pREQ->device->lun != 0) ||
4149+ (!pChan->DeviceFlags[pREQ->device->id & 1] & DFLAGS_DEVICE_PRESENT))
4150+ {
4151+ /*
4152+ * Indicate no device found at this address.
4153+ */
4154+ status = SRB_STATUS_INVALID_TARGET_ID;
4155+ break;
4156+ }
4157+ else
4158+ {
4159+ request_buffer = Srb->DataBuffer;
4160+ inquiryData = Srb->DataBuffer;
4161+
4162+ /*
4163+ * Zero INQUIRY data structure.
4164+ */
4165+ memset(request_buffer, 0, Srb->DataTransferLength);
4166+
4167+ /*
4168+ * Standard IDE interface only supports disks.
4169+ */
4170+ inquiryData->DeviceType = DIRECT_ACCESS_DEVICE;
4171+
4172+ /*
4173+ * Device type modifer.
4174+ */
4175+ request_buffer[1] = 0;
4176+
4177+ /*
4178+ * No ANSI/ISO compliance.
4179+ */
4180+ request_buffer[2] = 0;
4181+
4182+ /*
4183+ * Additional length.
4184+ */
4185+ request_buffer[4] = 31;
4186+ memcpy(&request_buffer[8], "ITE ", 8);
4187+ memcpy(&request_buffer[16], "IT8212F ", 16);
4188+ memcpy(&request_buffer[32], "1.3", 3);
4189+
4190+ /*
4191+ * Set the removable bit, if applicable.
4192+ */
4193+ if (pChan->DeviceFlags[pREQ->device->id & 1] & DFLAGS_REMOVABLE_DRIVE)
4194+ {
4195+ inquiryData->RemovableMedia = 1;
4196+ }
4197+
4198+ status = SRB_STATUS_SUCCESS;
4199+ }
4200+
4201+ break;
4202+
4203+ case SCSIOP_MODE_SENSE:
4204+ status = SRB_STATUS_INVALID_REQUEST;
4205+ break;
4206+
4207+ case SCSIOP_TEST_UNIT_READY:
4208+ status = SRB_STATUS_SUCCESS;
4209+ break;
4210+
4211+ case SCSIOP_READ_CAPACITY:
4212+ /*
4213+ * Claim 512 byte blocks (big-endian).
4214+ */
4215+ ((PREAD_CAPACITY_DATA)Srb->DataBuffer)->BytesPerBlock = 0x20000;
4216+
4217+ /*
4218+ * Calculate last sector.
4219+ */
4220+ if (pChan->IdentifyData[pREQ->device->id & 0x01].UserAddressableSectors == 0x0FFFFFFF)
4221+ {
4222+ i = pChan->IdentifyData[pREQ->device->id & 0x01].Capacity_48bit_LOW - 1;
4223+ }
4224+ else
4225+ {
4226+ i = pChan->IdentifyData[pREQ->device->id & 0x01].UserAddressableSectors - 1;
4227+ }
4228+
4229+ ((PREAD_CAPACITY_DATA)Srb->DataBuffer)->LogicalBlockAddress =
4230+ (((unsigned char *)&i)[0] << 24) | (((unsigned char *)&i)[1] << 16) |
4231+ (((unsigned char *)&i)[2] << 8) | ((unsigned char *)&i)[3];
4232+
4233+ status = SRB_STATUS_SUCCESS;
4234+ break;
4235+
4236+ case SCSIOP_VERIFY:
4237+ status = IdeVerify(pChan, Srb);
4238+ break;
4239+
4240+ case SCSIOP_READ:
4241+ case SCSIOP_WRITE:
4242+ status = IT8212ReadWrite(pChan, Srb);
4243+ break;
4244+
4245+ case SCSIOP_START_STOP_UNIT:
4246+ /*
4247+ * Determine what type of operation we should perform
4248+ */
4249+ status = SRB_STATUS_SUCCESS;
4250+ break;
4251+
4252+ case SCSIOP_REQUEST_SENSE:
4253+ /*
4254+ * This function makes sense buffers to report the results
4255+ * of the original GET_MEDIA_STATUS command
4256+ */
4257+ status = SRB_STATUS_INVALID_REQUEST;
4258+ break;
4259+
4260+ default:
4261+ printk("IdeSendCommand: unsupported command %x\n", Srb->Cdb[0]);
4262+ status = SRB_STATUS_INVALID_REQUEST;
4263+ } /* end switch */
4264+
4265+ return status;
4266+
4267+} /* end IdeSendCommand */
4268+
4269+/************************************************************************
4270+ * This routine is called from the SCSI port driver synchronized with
4271+ * the kernel to start an IO request. If the current SRB is busy, return
4272+ * FALSE, else return TURE.
4273+ ************************************************************************/
4274+static void
4275+AtapiStartIo(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
4276+{
4277+
4278+ u32 status = 0;
4279+
4280+ /*
4281+ * Determine which function.
4282+ */
4283+ switch (Srb->Function)
4284+ {
4285+ case SRB_FUNCTION_EXECUTE_SCSI:
4286+ /*
4287+ * Sanity check. Only one request can be outstanding on a
4288+ * controller.
4289+ */
4290+ if (pChan->CurrentSrb)
4291+ {
4292+ printk("AtapiStartIo: already have a request!\n");
4293+ status = SRB_STATUS_BUSY;
4294+ Srb->SrbStatus = SRB_STATUS_BUSY;
4295+ goto busy;
4296+ }
4297+
4298+ /*
4299+ * Indicate that a request is active on the controller.
4300+ */
4301+ pChan->CurrentSrb = Srb;
4302+ Srb->SrbStatus = SRB_STATUS_PENDING;
4303+
4304+ /*
4305+ * Send command to device.
4306+ */
4307+ if (pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_ATAPI_DEVICE)
4308+ {
4309+ /*
4310+ * If this is ATAPI device.
4311+ */
4312+ status = AtapiSendCommand(pChan, Srb);
4313+ }
4314+ else if (pChan->DeviceFlags[Srb->TargetId & 1] & DFLAGS_DEVICE_PRESENT)
4315+ {
4316+ /*
4317+ * If this is IDE device.
4318+ */
4319+ status = IdeSendCommand(pChan, Srb);
4320+ }
4321+ else
4322+ {
4323+ /*
4324+ * Nothing else.
4325+ */
4326+ status = SRB_STATUS_SELECTION_TIMEOUT;
4327+ }
4328+
4329+ break;
4330+
4331+ case SRB_FUNCTION_IO_CONTROL:
4332+ /*
4333+ * IO control function.
4334+ */
4335+ printk("AtapiStartIo: IO control\n");
4336+ break;
4337+
4338+ default:
4339+ /*
4340+ * Indicate unsupported command.
4341+ */
4342+ status = SRB_STATUS_INVALID_REQUEST;
4343+ break;
4344+
4345+ } /* end switch */
4346+
4347+ busy:
4348+ if (status != SRB_STATUS_PENDING)
4349+ {
4350+ /*
4351+ * Set status in SRB.
4352+ */
4353+ Srb->SrbStatus = (u8)status;
4354+ dprintk("AtapiStartIo: status=%x\n", status);
4355+ TaskDone(pChan, Srb);
4356+ }
4357+
4358+} /* end AtapiStartIo */
4359+
4360+/************************************************************************
4361+ * Convert Scsi_Cmnd structure to SCSI_REQUEST_BLOCK.
4362+ ************************************************************************/
4363+static void
4364+MapRequest(Scsi_Cmnd * pREQ, PSCSI_REQUEST_BLOCK Srb)
4365+{
4366+
4367+ Srb->Length = sizeof(SCSI_REQUEST_BLOCK);
4368+ Srb->CdbLength = pREQ->cmd_len;
4369+ Srb->TargetId = pREQ->device->id;
4370+ Srb->Lun = pREQ->device->lun;
4371+ Srb->UseSg = pREQ->use_sg;
4372+
4373+ /*
4374+ * Copy the actual command from Scsi_Cmnd to CDB.
4375+ */
4376+ memcpy(Srb->Cdb, pREQ->cmnd, Srb->CdbLength);
4377+
4378+ /*
4379+ * Always the SCSI_FUNCTION_EXECUTE_SCSI now.
4380+ */
4381+ Srb->Function = SRB_FUNCTION_EXECUTE_SCSI;
4382+
4383+ Srb->SrbStatus = 0;
4384+ Srb->ScsiStatus = 0;
4385+ Srb->SenseInfoBufferLength = 16;
4386+
4387+ /*
4388+ * The CDB's first byte is operation code.
4389+ */
4390+ if ((Srb->Cdb[0] == SCSIOP_WRITE6) || (Srb->Cdb[0] == SCSIOP_WRITE) ||
4391+ (Srb->Cdb[0] == SCSIOP_MODE_SELECT10))
4392+ {
4393+ Srb->SrbFlags = SRB_FLAGS_DATA_OUT;
4394+ }
4395+ else
4396+ {
4397+ Srb->SrbFlags = SRB_FLAGS_DATA_IN;
4398+ }
4399+
4400+ Srb->TimeOutValue = 0;
4401+ Srb->SenseInfoBuffer = pREQ->sense_buffer;
4402+
4403+ if (Srb->Cdb[0] == SCSIOP_REQUEST_SENSE)
4404+ {
4405+ Srb->DataTransferLength = 0x40;
4406+ Srb->DataBuffer = pREQ->sense_buffer;
4407+ }
4408+ else
4409+ {
4410+ Srb->DataTransferLength = pREQ->request_bufflen;
4411+ Srb->DataBuffer = pREQ->request_buffer;
4412+ }
4413+
4414+ if (pREQ->use_sg)
4415+ {
4416+ Srb->WorkingFlags |= SRB_WFLAGS_USE_SG;
4417+ }
4418+
4419+ Srb->pREQ = pREQ;
4420+
4421+} /* end MapRequest */
4422+
4423+/************************************************************************
4424+ * A task execution has been done. For OS request, we need to Notify OS
4425+ * and invoke next take which wait at queue.
4426+ ************************************************************************/
4427+static void
4428+TaskDone(PChannel pChan, PSCSI_REQUEST_BLOCK Srb)
4429+{
4430+
4431+ Scsi_Cmnd * pREQ = Srb->pREQ;
4432+
4433+ pChan->CurrentSrb = NULL;
4434+ pChan->RetryCount = 0;
4435+
4436+ switch (SRB_STATUS(Srb->SrbStatus))
4437+ {
4438+ case SRB_STATUS_SUCCESS:
4439+ pREQ->result = (DID_OK << 16);
4440+ break;
4441+
4442+ case SRB_STATUS_SELECTION_TIMEOUT:
4443+ pREQ->result = (DID_NO_CONNECT << 16);
4444+ break;
4445+
4446+ case SRB_STATUS_BUSY:
4447+ pREQ->result = (DID_BUS_BUSY << 16);
4448+ break;
4449+
4450+ case SRB_STATUS_BUS_RESET:
4451+ pREQ->result = (DID_RESET << 16);
4452+ break;
4453+
4454+ case SRB_STATUS_INVALID_TARGET_ID:
4455+ case SRB_STATUS_INVALID_PATH_ID:
4456+ case SRB_STATUS_INVALID_LUN:
4457+ case SRB_STATUS_NO_HBA:
4458+ pREQ->result = (DID_BAD_TARGET << 16);
4459+ break;
4460+
4461+ case SRB_STATUS_NO_DEVICE:
4462+ pREQ->result = (DID_BAD_TARGET << 16);
4463+ break;
4464+
4465+ case SRB_STATUS_ERROR:
4466+ pREQ->result = (DRIVER_SENSE << 24) | (DID_OK << 16) |
4467+ (CHECK_CONDITION << 1);
4468+ break;
4469+ }
4470+
4471+ dprintk("TaskDone(pChan=%p, pREQ=%p, result=%x)\n",
4472+ pChan, pREQ, pREQ->result);
4473+
4474+ /*
4475+ * Notify OS that this OS request has been done.
4476+ */
4477+ pREQ->scsi_done(pREQ);
4478+
4479+ /*
4480+ * Check the queue again.
4481+ */
4482+ TaskQueue();
4483+
4484+} /* end TaskDone */
4485+
4486+/************************************************************************
4487+ * Start a command, doing convert first.
4488+ ************************************************************************/
4489+static void
4490+TaskStart(PChannel pChan, Scsi_Cmnd *pREQ)
4491+{
4492+
4493+ PSCSI_REQUEST_BLOCK Srb;
4494+
4495+ dprintk("TaskStart(pChan=%p, pREQ=%p)\n", pChan, pREQ);
4496+
4497+ Srb = &pChan->_Srb;
4498+
4499+ /*
4500+ * Clear the SRB structure.
4501+ */
4502+ memset(Srb, 0, sizeof(SCSI_REQUEST_BLOCK));
4503+
4504+ /*
4505+ * Convert Scsi_Cmnd structure to SCSI_REQUEST_BLOCK.
4506+ */
4507+ MapRequest(pREQ, Srb);
4508+
4509+ /*
4510+ * Start IDE I/O command.
4511+ */
4512+ AtapiStartIo(pChan, Srb);
4513+
4514+} /* end TaskStart */
4515+
4516+/************************************************************************
4517+ * Check if queue is empty. If there are request in queue, transfer the
4518+ * request to HIM's request and execute the request.
4519+ ************************************************************************/
4520+static void
4521+TaskQueue(void)
4522+{
4523+
4524+ unsigned long flags;
4525+ Scsi_Cmnd * SCpnt;
4526+ PChannel pChan;
4527+ PITE_ADAPTER pAdap;
4528+
4529+ check_next:
4530+
4531+ if (it8212_req_last != NULL)
4532+ {
4533+ spin_lock_irqsave(&queue_request_lock, flags);
4534+ SCpnt = (Scsi_Cmnd *)it8212_req_last->SCp.ptr;
4535+
4536+ if (it8212_req_last == SCpnt)
4537+ {
4538+ it8212_req_last = NULL;
4539+ }
4540+ else
4541+ {
4542+ it8212_req_last->SCp.ptr = (char *)SCpnt->SCp.ptr;
4543+ }
4544+ spin_unlock_irqrestore(&queue_request_lock, flags);
4545+
4546+ /*
4547+ * Check the command.
4548+ */
4549+ if (SCpnt->device->host)
4550+ {
4551+ if ((SCpnt->device->channel != 0) ||
4552+ (SCpnt->device->id >= (4 * NumAdapters)))
4553+ {
4554+ /*
4555+ * Returns that we have a bad target.
4556+ */
4557+ SCpnt->result = (DID_BAD_TARGET << 16);
4558+ SCpnt->scsi_done(SCpnt);
4559+ goto check_next;
4560+ }
4561+ }
4562+
4563+ if (SCpnt->device->id >= 4)
4564+ {
4565+ pAdap = ite_adapters[1];
4566+ if (SCpnt->device->id < 6) pChan = &pAdap->IDEChannel[0];
4567+ else pChan = &pAdap->IDEChannel[1];
4568+ }
4569+ else
4570+ {
4571+ pAdap = ite_adapters[0];
4572+ if (SCpnt->device->id < 2) pChan = &pAdap->IDEChannel[0];
4573+ else pChan = &pAdap->IDEChannel[1];
4574+ }
4575+
4576+ TaskStart(pChan, SCpnt);
4577+ return;
4578+ }
4579+
4580+} /* end TaskQueue */
4581+
4582+/****************************************************************
4583+ * Name: iteraid_queuecommand
4584+ * Description: Process a queued command from the SCSI manager.
4585+ * Parameters: SCpnt - Pointer to SCSI command structure.
4586+ * done - Pointer to done function to call.
4587+ * Returns: Status code.
4588+ ****************************************************************/
4589+int
4590+iteraid_queuecommand(Scsi_Cmnd *SCpnt, void (*done)(Scsi_Cmnd *))
4591+{
4592+
4593+ unsigned long flags;
4594+ dprintk("##Queuecommand enter##\n");
4595+
4596+ /*
4597+ * Hooks the done routine.
4598+ */
4599+ SCpnt->scsi_done = (void *)done;
4600+
4601+ spin_lock_irqsave(&queue_request_lock, flags);
4602+ if (it8212_req_last == NULL)
4603+ {
4604+ SCpnt->SCp.ptr = (char *)SCpnt;
4605+ }
4606+ else
4607+ {
4608+ SCpnt->SCp.ptr = it8212_req_last->SCp.ptr;
4609+ it8212_req_last->SCp.ptr = (char *)SCpnt;
4610+ }
4611+ it8212_req_last = SCpnt;
4612+ spin_unlock_irqrestore(&queue_request_lock, flags);
4613+
4614+ TaskQueue();
4615+
4616+ dprintk("@@Queuecommand exit@@\n");
4617+ return 0;
4618+
4619+} /* end iteraid_queuecommand */
4620+
4621+/****************************************************************
4622+ * Name: internal_done :LOCAL
4623+ * Description: Done handler for non-queued commands
4624+ * Parameters: SCpnt - Pointer to SCSI command structure.
4625+ * Returns: Nothing.
4626+ ****************************************************************/
4627+static void
4628+internal_done(Scsi_Cmnd * SCpnt)
4629+{
4630+
4631+ SCpnt->SCp.Status++;
4632+
4633+} /* end internal_done */
4634+
4635+/****************************************************************
4636+ * Name: iteraid_command
4637+ * Description: Process a command from the SCSI manager.
4638+ * Parameters: SCpnt - Pointer to SCSI command structure.
4639+ * Returns: Status code.
4640+ ****************************************************************/
4641+int
4642+iteraid_command(Scsi_Cmnd *SCpnt)
4643+{
4644+
4645+ unsigned long timeout;
4646+
4647+ SCpnt->SCp.Status = 0;
4648+ iteraid_queuecommand(SCpnt, internal_done);
4649+
4650+ /*
4651+ * Should be longer than hard-reset time.
4652+ */
4653+ timeout = jiffies + 60 * HZ;
4654+ while (!SCpnt->SCp.Status && time_before(jiffies, timeout))
4655+ {
4656+ barrier();
4657+ }
4658+
4659+ if (!SCpnt->SCp.Status) SCpnt->result = (DID_ERROR << 16);
4660+
4661+ return SCpnt->result;
4662+
4663+} /* end iteraid_command */
4664+
4665+/************************************************************************
4666+ * Enables/disables media status notification.
4667+ ************************************************************************/
4668+static void
4669+IdeMediaStatus(u8 EnableMSN, PChannel pChan, u8 Device)
4670+{
4671+
4672+ u8 statusByte;
4673+ u8 errorByte;
4674+
4675+ statusByte = 0;
4676+
4677+ if (EnableMSN == TRUE)
4678+ {
4679+ /*
4680+ * If supported enable Media Status Notification support.
4681+ */
4682+ if ((pChan->DeviceFlags[Device] & DFLAGS_REMOVABLE_DRIVE))
4683+ {
4684+ outb((u8) (0x95), pChan->io_ports[IDE_FEATURE_OFFSET]);
4685+ outb(IDE_COMMAND_ENABLE_MEDIA_STATUS, pChan->io_ports[IDE_COMMAND_OFFSET]);
4686+
4687+ WaitOnBaseBusy(pChan, statusByte);
4688+
4689+ if (statusByte & IDE_STATUS_ERROR)
4690+ {
4691+ /*
4692+ * Read the error register.
4693+ */
4694+ errorByte = inb(pChan->io_ports[IDE_ERROR_OFFSET]);
4695+
4696+ printk("IdeMediaStatus: error enabling media status. status %u, error byte %u\n",
4697+ statusByte, errorByte);
4698+ }
4699+ else
4700+ {
4701+ pChan->DeviceFlags[Device] |= DFLAGS_MEDIA_STATUS_ENABLED;
4702+ printk("IdeMediaStatus: media status notification supported!\n");
4703+ pChan->ReturningMediaStatus = 0;
4704+ }
4705+ }
4706+ }
4707+ else /* end if EnableMSN == TRUE */
4708+ {
4709+ /*
4710+ * Disable if previously enabled.
4711+ */
4712+ if ((pChan->DeviceFlags[Device] & DFLAGS_MEDIA_STATUS_ENABLED))
4713+ {
4714+ outb((u8)(0x31), pChan->io_ports[IDE_FEATURE_OFFSET]);
4715+ outb(IDE_COMMAND_ENABLE_MEDIA_STATUS,
4716+ pChan->io_ports[IDE_COMMAND_OFFSET]);
4717+
4718+ WaitOnBaseBusy(pChan, statusByte);
4719+ pChan->DeviceFlags[Device] &= ~DFLAGS_MEDIA_STATUS_ENABLED;
4720+ }
4721+ }
4722+
4723+} /* end IdeMediaStatus */
4724+
4725+/************************************************************************
4726+ * Issue IDENTIFY command to a device.
4727+ * Either the standard (EC) or the ATAPI packet (A1) IDENTIFY.
4728+ ************************************************************************/
4729+static u8
4730+IssueIdentify(PChannel pChan, u8 DeviceNumber, u8 Command)
4731+{
4732+
4733+ u8 statusByte = 0;
4734+ u32 i;
4735+ u32 j;
4736+
4737+ /*
4738+ * Check that the status register makes sense.
4739+ */
4740+ GetBaseStatus(pChan, statusByte);
4741+
4742+ if (Command == IDE_COMMAND_IDENTIFY)
4743+ {
4744+ /*
4745+ * Mask status byte ERROR bits.
4746+ */
4747+ statusByte &= ~(IDE_STATUS_ERROR | IDE_STATUS_INDEX);
4748+
4749+ dprintk("IssueIdentify: checking for IDE. status (%x)\n", statusByte);
4750+
4751+ /*
4752+ * Check if register value is reasonable.
4753+ */
4754+ if (statusByte != IDE_STATUS_IDLE)
4755+ {
4756+ /*
4757+ * Reset the channel.
4758+ */
4759+ printk("IssueIdentify: resetting channel.\n");
4760+ IdeHardReset(pChan, statusByte);
4761+
4762+ outb((u8)((DeviceNumber << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
4763+ GetBaseStatus(pChan, statusByte);
4764+ statusByte &= ~IDE_STATUS_INDEX;
4765+
4766+ if (statusByte != IDE_STATUS_IDLE)
4767+ {
4768+ /*
4769+ * Give up on this.
4770+ */
4771+ printk("IssueIdentify(IDE): disk[%d] not ready. status=0x%x\n",
4772+ DeviceNumber, statusByte);
4773+ return FALSE;
4774+ }
4775+ }
4776+ }
4777+ else
4778+ {
4779+ dprintk("IssueIdentify: checking for ATAPI. status (%x)\n", statusByte);
4780+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ))
4781+ {
4782+ /*
4783+ * Reset the device.
4784+ */
4785+ dprintk("IssueIdentify: resetting device.\n");
4786+ AtapiSoftReset(pChan, DeviceNumber);
4787+
4788+ outb((u8)((DeviceNumber << 4) | 0xA0),
4789+ pChan->io_ports[IDE_SELECT_OFFSET]);
4790+ GetBaseStatus(pChan, statusByte);
4791+ if (statusByte != 0)
4792+ {
4793+ /*
4794+ * Give up on this.
4795+ */
4796+ printk("IssueIdentify(ATAPI): disk[%d] not ready. status=0x%x\n",
4797+ DeviceNumber, statusByte);
4798+ return FALSE;
4799+ }
4800+ }
4801+ }
4802+
4803+ for (j = 0; j < 2; j++)
4804+ {
4805+ /*
4806+ * Wait for device ready (Not Busy and Not DRQ).
4807+ */
4808+ outb((u8)((DeviceNumber << 4) | 0xA0),
4809+ pChan->io_ports[IDE_SELECT_OFFSET]);
4810+ WaitForDeviceReady(pChan, statusByte);
4811+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ))
4812+ {
4813+ printk("IssueIdentify: disk[%d] not ready. status=0x%x\n",
4814+ DeviceNumber, statusByte);
4815+ continue;
4816+ }
4817+
4818+ /*
4819+ * Send IDENTIFY command.
4820+ */
4821+ outb(Command, pChan->io_ports[IDE_COMMAND_OFFSET]);
4822+
4823+ /*
4824+ * Wait for DRQ.
4825+ */
4826+ WaitForBaseDrq(pChan, statusByte);
4827+ if (!(statusByte & IDE_STATUS_DRQ))
4828+ {
4829+ printk("IssueIdentify: disk[%d] DRQ never asserted. status=%x\n",
4830+ DeviceNumber, statusByte);
4831+
4832+ /*
4833+ * Give one more chance.
4834+ */
4835+ if (Command == IDE_COMMAND_IDENTIFY)
4836+ {
4837+ IdeHardReset(pChan, statusByte);
4838+ }
4839+ else
4840+ {
4841+ AtapiSoftReset(pChan, DeviceNumber);
4842+ }
4843+ }
4844+ else
4845+ {
4846+ break;
4847+ }
4848+ }
4849+
4850+ /*
4851+ * Check for error on really stupid master devices that assert random
4852+ * patterns of bits in the status register at the slave address.
4853+ */
4854+ outb((u8)((DeviceNumber << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
4855+ GetBaseStatus(pChan, statusByte);
4856+ if (statusByte & IDE_STATUS_ERROR)
4857+ {
4858+ printk("IssueIdentify: disk[%d] returns error status\n", DeviceNumber);
4859+ return FALSE;
4860+ }
4861+
4862+ dprintk("IssueIdentify: status before read words %x\n", statusByte);
4863+
4864+ /*
4865+ * Suck out 256 words. After waiting for one model that asserts busy
4866+ * after receiving the Packet Identify command.
4867+ */
4868+ WaitOnBusy(pChan, statusByte);
4869+
4870+ if (!(statusByte & IDE_STATUS_DRQ)) { return FALSE; }
4871+
4872+ ReadBuffer(pChan, (unsigned short *)&pChan->FullIdentifyData, 256);
4873+
4874+ /*
4875+ * Check out a few capabilities / limitations of the device.
4876+ * 01/29/2003
4877+ */
4878+ if (pChan->FullIdentifyData.SpecialFunctionsEnabled & 1)
4879+ {
4880+ /*
4881+ * Determine if this drive supports the MSN functions.
4882+ */
4883+ printk("Marking drive %x as removable. SFE = %x\n",
4884+ DeviceNumber, pChan->FullIdentifyData.SpecialFunctionsEnabled);
4885+ pChan->DeviceFlags[DeviceNumber] |= DFLAGS_REMOVABLE_DRIVE;
4886+ }
4887+
4888+ memcpy(&pChan->IdentifyData[DeviceNumber], &pChan->FullIdentifyData,
4889+ sizeof(IDENTIFY_DATA2));
4890+
4891+ if (pChan->IdentifyData[DeviceNumber].GeneralConfiguration & 0x20 &&
4892+ Command != IDE_COMMAND_IDENTIFY)
4893+ {
4894+ /*
4895+ * This device interrupts with the assertion of DRQ after receiving
4896+ * Atapi Packet Command.
4897+ */
4898+ pChan->DeviceFlags[DeviceNumber] |= DFLAGS_INT_DRQ;
4899+
4900+ dprintk(KERN_NOTICE "Device interrupts on assertion of DRQ.\n");
4901+ }
4902+ else
4903+ {
4904+ dprintk(KERN_NOTICE "Device does't interrupt on assertion of DRQ.\n");
4905+ }
4906+
4907+ if (((pChan->IdentifyData[DeviceNumber].GeneralConfiguration & 0xF00)
4908+ == 0x100) && Command != IDE_COMMAND_IDENTIFY)
4909+ {
4910+ /*
4911+ * This is a tape.
4912+ */
4913+ pChan->DeviceFlags[DeviceNumber] |= DFLAGS_TAPE_DEVICE;
4914+ printk(KERN_NOTICE "IssueIdentify: device is a tape drive.\n");
4915+ }
4916+ else
4917+ {
4918+ dprintk(KERN_NOTICE "IssueIdentify: device is not a tape drive.\n");
4919+ }
4920+
4921+ /*
4922+ * Work around for some IDE and one model Atapi that will present more
4923+ * then 256 bytes for the Identify data.
4924+ */
4925+ WaitOnBaseBusy(pChan, statusByte);
4926+
4927+ for (i = 0; i < 0x10000; i++)
4928+ {
4929+ GetStatus(pChan, statusByte);
4930+
4931+ if (statusByte & IDE_STATUS_DRQ)
4932+ {
4933+ /*
4934+ * Suck out any remaining bytes and throw away.
4935+ */
4936+ inw(pChan->io_ports[IDE_DATA_OFFSET]);
4937+ }
4938+ else
4939+ {
4940+ break;
4941+ }
4942+ }
4943+
4944+ return TRUE;
4945+
4946+} /* end IssueIdentify() */
4947+
4948+/************************************************************************
4949+ * Check this is the IDE or ATAPI disk then identify it.
4950+ ************************************************************************/
4951+static u8
4952+iteraid_find_device(PChannel pChan, u8 channel)
4953+{
4954+
4955+ u8 deviceNumber;
4956+ u8 signatureLow;
4957+ u8 signatureHigh;
4958+ u8 deviceResponded = FALSE;
4959+ u8 statusByte = 0;
4960+
4961+ /*
4962+ * Clear expecting interrupt flag and current SRB field.
4963+ */
4964+ pChan->ExpectingInterrupt = FALSE;
4965+ pChan->CurrentSrb = NULL;
4966+
4967+ /*
4968+ * Search for devices in each channel.
4969+ */
4970+ for (deviceNumber = 0; deviceNumber < 2; deviceNumber++)
4971+ {
4972+ /*
4973+ * Select the device.
4974+ */
4975+ outb((u8)((deviceNumber << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
4976+
4977+ /*
4978+ * Disable interrupts during initialization.
4979+ */
4980+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
4981+
4982+ /*
4983+ * Check here for some SCSI adapters that incorporate IDE emulation.
4984+ */
4985+ statusByte = inb(pChan->io_ports[IDE_CONTROL_OFFSET]);
4986+
4987+ /*
4988+ * Do soft reset on selected device. (AtapiSoftReset)
4989+ */
4990+ AtapiSoftReset(pChan, deviceNumber);
4991+ WaitOnBusy(pChan, statusByte);
4992+
4993+ signatureLow = inb(pChan->io_ports[IDE_MIDCYL_OFFSET]);
4994+ signatureHigh = inb(pChan->io_ports[IDE_HCYL_OFFSET]);
4995+
4996+ if (signatureLow == 0x14 && signatureHigh == 0xEB)
4997+ {
4998+ /*
4999+ * ATAPI signature found. Issue ATAPI packet identify command.
5000+ */
5001+ if (IssueIdentify(pChan, deviceNumber, IDE_COMMAND_ATAPI_IDENTIFY))
5002+ {
5003+ /*
5004+ * Indicate ATAPI device.
5005+ */
5006+ printk("iteraid_find_device: channel %x device %x is ATAPI.\n",
5007+ channel, deviceNumber);
5008+
5009+ pChan->DeviceFlags[deviceNumber] |= DFLAGS_ATAPI_DEVICE;
5010+ pChan->DeviceFlags[deviceNumber] |= DFLAGS_DEVICE_PRESENT;
5011+ pChan->DeviceFlags[deviceNumber] &= ~DFLAGS_CONFIG_CHANGED;
5012+
5013+ deviceResponded = TRUE;
5014+
5015+ GetStatus(pChan, statusByte);
5016+ if (statusByte & IDE_STATUS_ERROR)
5017+ {
5018+ AtapiSoftReset(pChan, deviceNumber);
5019+ }
5020+ }
5021+ else
5022+ {
5023+ /*
5024+ * Indicate no working device.
5025+ */
5026+ printk("iteraid_find_device: channel %x device %x doesn't respond.\n",
5027+ channel, deviceNumber);
5028+ pChan->DeviceFlags[deviceNumber] &= ~DFLAGS_DEVICE_PRESENT;
5029+ }
5030+ }
5031+ else
5032+ {
5033+ /*
5034+ * Select the device.
5035+ */
5036+ outb((u8)((deviceNumber << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]);
5037+
5038+ /*
5039+ * Check here for some SCSI adapters that incorporate IDE emulation.
5040+ */
5041+ GetStatus(pChan, statusByte);
5042+
5043+ /*
5044+ * No Disk.
5045+ */
5046+ if (statusByte == 0xFF || statusByte == 0x7F || statusByte == 0x0)
5047+ {
5048+ dprintk("FindDevices: cannot find IDE device. status = %x\n", statusByte);
5049+ continue;
5050+ }
5051+
5052+ /*
5053+ * Issue IDE Identify. If an ATAPI device is actually present,
5054+ * the signature will be asserted, and the drive will be
5055+ * recognized as such.
5056+ */
5057+ if (IssueIdentify(pChan, deviceNumber, IDE_COMMAND_IDENTIFY))
5058+ {
5059+ /*
5060+ * IDE drive found.
5061+ */
5062+ printk(KERN_WARNING "FindDevices: device %u is IDE\n",
5063+ (channel * 2) + deviceNumber);
5064+ pChan->DeviceFlags[deviceNumber] |= DFLAGS_DEVICE_PRESENT;
5065+ pChan->DeviceFlags[deviceNumber] &= ~DFLAGS_ATAPI_DEVICE;
5066+ pChan->DeviceFlags[deviceNumber] &= ~DFLAGS_CONFIG_CHANGED;
5067+ deviceResponded = TRUE;
5068+ }
5069+ else
5070+ {
5071+ printk(KERN_WARNING "FindDevices: device %u is not present\n",
5072+ (channel * 2) + deviceNumber);
5073+ pChan->DeviceFlags[deviceNumber] &= ~DFLAGS_DEVICE_PRESENT;
5074+ }
5075+ }
5076+ }
5077+
5078+ return deviceResponded;
5079+
5080+} /* end iteraid_find_device */
5081+
5082+/************************************************************************
5083+ * IDE disk hardware initialize.
5084+ ************************************************************************/
5085+u8
5086+AtapiHwInitialize(PITE_ADAPTER pAdap, PChannel pChan, u8 channel)
5087+{
5088+
5089+ u8 i;
5090+ u8 statusByte = 0;
5091+
5092+ /*
5093+ * For two devices in this channel.
5094+ */
5095+ for (i = 0; i < 2; i++)
5096+ {
5097+ /*
5098+ * only check in Fireware mode.
5099+ */
5100+ if (pAdap->bypass_mode == FALSE)
5101+ {
5102+ outb((u8) (0xA0 | ((u8) i << 4)), pChan->io_ports[IDE_SELECT_OFFSET]);
5103+
5104+ /*
5105+ * Check if card at this address.
5106+ */
5107+ outb(0xAA, pChan->io_ports[IDE_MIDCYL_OFFSET]);
5108+
5109+ /*
5110+ * Check if indentifier can be read back.
5111+ */
5112+ if ((statusByte = inb(pChan->io_ports[IDE_MIDCYL_OFFSET])) != 0xAA)
5113+ {
5114+ printk("AtapiHwInitialize: identifier read back from (%x, %x) = %x\n",
5115+ channel, i, statusByte);
5116+
5117+ /*
5118+ * ***** Dont free it....For later use *****
5119+ * ScsiPortFreeDeviceBase(HwDeviceExtension, ioSpace1);
5120+ */
5121+ continue;
5122+ }
5123+
5124+ printk("AtapiHwInitialize: found ATA device (%x, %x)n", channel, i);
5125+ }
5126+
5127+ }
5128+
5129+ return TRUE;
5130+
5131+} /* end AtapiHwInitialize */
5132+
5133+/************************************************************************
5134+ * Initialize a adapter, return 0 means success.
5135+ ************************************************************************/
5136+static int
5137+iteraid_init(PITE_ADAPTER pAdap, struct pci_dev *pPciDev)
5138+{
5139+
5140+ u8 z;
5141+ u8 i;
5142+ u8 j;
5143+ u8 set_irq;
5144+ unsigned long control_addr; /* Control reg base address */
5145+ unsigned long base_addr; /* IDE I/O port base address */
5146+ unsigned long bm_base_addr; /* Bus Master base address */
5147+ PChannel pChan; /* Use for each channel */
5148+
5149+ dprintk("iteraid_init enter\n");
5150+
5151+ /*
5152+ * Common settings.
5153+ */
5154+ pAdap->pci_bus = pPciDev->bus->number;
5155+ pAdap->devfn = pPciDev->devfn;
5156+ pAdap->irq = pPciDev->irq;
5157+ pAdap->irqOwned = 0;
5158+
5159+ printk(KERN_NOTICE "Found Controller: %s\n", pAdap->name);
5160+
5161+ /*
5162+ * Allocate buffer for IDE channles (One IT8212 supports two channels)
5163+ */
5164+ pAdap->IDEChannel =
5165+ (PChannel)kmalloc(sizeof(Channel) * pAdap->num_channels, GFP_ATOMIC);
5166+
5167+ if (pAdap->IDEChannel == 0)
5168+ {
5169+ printk("iteraid_init: pChan allocate failed.\n");
5170+ return -1;
5171+ }
5172+
5173+ memset(pAdap->IDEChannel, 0, sizeof(Channel) * pAdap->num_channels);
5174+
5175+ set_irq = 1;
5176+ for (i = 0; i < NumAdapters; i++)
5177+ {
5178+ if (ite_adapters[i]->irqOwned == pAdap->irq) set_irq = 0;
5179+ }
5180+
5181+ /*
5182+ * Request the irq (share irq) and hook the interrupt service routine.
5183+ */
5184+ if (set_irq)
5185+ {
5186+ if (request_irq(pAdap->irq, Irq_Handler, SA_SHIRQ, PROC_DIR_NAME, pAdap) < 0)
5187+ {
5188+ printk("iteraid_init: unable to allocate IRQ for %s\n", pAdap->name);
5189+ return -1;
5190+ }
5191+ pAdap->irqOwned = pAdap->irq;
5192+ }
5193+
5194+ /*
5195+ * Get the IDE port and DMA registers.
5196+ */
5197+ for (i = 0; i < pAdap->num_channels; i++)
5198+ {
5199+ pChan = &pAdap->IDEChannel[i];
5200+ /*
5201+ * Reference the book "LINUX DEVICE DRIVER 2nd", Page 484
5202+ * unsigned long pci_resource_start(struct pci_dev *dev, int bar);
5203+ */
5204+ base_addr = pci_resource_start(pPciDev, i * 2);
5205+ control_addr = pci_resource_start(pPciDev, i * 2 + 1);
5206+ bm_base_addr = pci_resource_start(pPciDev, 4);
5207+ pChan->dma_base = bm_base_addr + i * 8;
5208+ for (j = 0; j <= IDE_STATUS_OFFSET; j++)
5209+ {
5210+ pChan->io_ports[j] = base_addr;
5211+ base_addr += 1;
5212+ }
5213+ pChan->io_ports[IDE_CONTROL_OFFSET] = control_addr + 2;
5214+ }
5215+
5216+ /*
5217+ * Initialize channels.
5218+ */
5219+ for (z = 0; z < pAdap->num_channels; z++)
5220+ {
5221+ pChan = &pAdap->IDEChannel[z];
5222+ pChan->pPciDev = pPciDev;
5223+ pChan->channel = z;
5224+
5225+ /*
5226+ * This section should be masked off if BIOS is ready.
5227+ */
5228+# if (MARK_DEBUG_BYPASS_MODE)
5229+ /*
5230+ * BIOS is not ready, so I change to ByPass Mode by myself.
5231+ */
5232+ pAdap->bypass_mode = TRUE;
5233+
5234+ /*
5235+ * Change to bypass mode.
5236+ */
5237+ IT8212InitBypassMode(pPciDev);
5238+# endif
5239+
5240+ /*
5241+ * Hardware initialize.
5242+ */
5243+# if (0)
5244+ AtapiHwInitialize(pAdap, pChan, z);
5245+# endif
5246+
5247+ /*
5248+ * Find and identify the IDE or ATAPI device.
5249+ */
5250+ iteraid_find_device(pChan, z);
5251+
5252+ /*
5253+ * Set the best transfer mode.
5254+ */
5255+# if (MARK_SET_BEST_TRANSFER)
5256+ IT8212SetBestTransferMode(pAdap, pChan, z);
5257+# endif
5258+
5259+ /*
5260+ * Set Scatter/Gather List buffer for the channel.
5261+ */
5262+ IdeSetupDma(pChan, pChan->dma_base, 8);
5263+ }
5264+
5265+ dprintk("iteraid_init exit\n");
5266+ return 0;
5267+
5268+} /* end iteraid_init */
5269+
5270+/************************************************************************
5271+ * This function will find and initialize any cards.
5272+ ************************************************************************/
5273+int
5274+iteraid_detect(Scsi_Host_Template *tpnt)
5275+{
5276+
5277+ u8 i;
5278+ u8 j;
5279+ u8 mode;
5280+ u8 pci_id;
5281+ PChannel pChan;
5282+ PITE_ADAPTER pAdap;
5283+ struct pci_dev * pPciDev;
5284+ dprintk("iteraid_detect enter\n");
5285+
5286+ /*
5287+ * Search ITE IT8212 chip.
5288+ */
5289+ pPciDev = NULL;
5290+ pci_id = 0;
5291+ while ((pPciDev = pci_find_device(ITE_VENDOR_ID, ITE_DEVICE_ID, pPciDev)))
5292+ {
5293+ if (PCI_FUNC(pPciDev->devfn)) continue;
5294+
5295+ /*
5296+ * Allocate memory for Adapter.
5297+ */
5298+ pAdap = (PITE_ADAPTER)kmalloc(sizeof(ITE_ADAPTER), GFP_ATOMIC);
5299+ if (pAdap == NULL)
5300+ {
5301+ printk("iteraid_detect: pAdap allocate failed.\n");
5302+ continue;
5303+ }
5304+
5305+ memset(pAdap, 0, sizeof(ITE_ADAPTER));
5306+ pAdap->name = CONTROLLER_NAME_IT8212;
5307+ pAdap->num_channels = 2;
5308+ pAdap->pci_dev = pPciDev;
5309+
5310+ /*
5311+ * Check if we are in bypass(transparent) or firmware mode.
5312+ */
5313+ pci_read_config_byte(pPciDev, 0x50, &mode);
5314+ if (mode & 1)
5315+ {
5316+ dprintk("Firmware mode in PCI#%d\n", pci_id);
5317+ pAdap->bypass_mode = FALSE;
5318+ }
5319+ else
5320+ {
5321+ dprintk("Transparent mode in PCI#%d\n", pci_id);
5322+ pAdap->bypass_mode = TRUE;
5323+ }
5324+
5325+ if (iteraid_init(pAdap, pPciDev) == 0)
5326+ {
5327+ ite_adapters[NumAdapters++] = pAdap;
5328+ }
5329+ pci_id++;
5330+ }
5331+
5332+ /*
5333+ * Reenable interrupt after initialization. 2003/04/28
5334+ */
5335+ for (i = 0; i < NumAdapters; i++)
5336+ {
5337+ pAdap = ite_adapters[i];
5338+ for (j = 0; j < pAdap->num_channels; j++)
5339+ {
5340+ pChan = &pAdap->IDEChannel[j];
5341+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
5342+ }
5343+ }
5344+
5345+ if (NumAdapters)
5346+ {
5347+ /*
5348+ * Register a virtual host.
5349+ */
5350+ ite_vhost = scsi_register(tpnt, 0);
5351+
5352+ ite_vhost->io_port = 0;
5353+ ite_vhost->n_io_port = 0;
5354+ ite_vhost->max_channel = 0;
5355+ ite_vhost->max_id = MAX_DEVICES;
5356+ ite_vhost->max_lun = 1;
5357+
5358+# if (0)
5359+# if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
5360+ scsi_set_device(ite_vhost, &pPciDev->dev);
5361+# elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,4)
5362+ scsi_set_pci_device(ite_vhost, pPciDev);
5363+# endif
5364+# endif
5365+
5366+ /*
5367+ * Register the driver as a character device, for applications to
5368+ * acess it for ioctls. Ideally, this should go in the init_module()
5369+ * routine, but since it is hidden in the file "scsi_module.c" (
5370+ * included in the end), we define it here. First argument (major)
5371+ * to register_chrdev implies a dynamic major number allocation.
5372+ */
5373+ ite_major = register_chrdev(0, "itedev", &itedev_fops);
5374+
5375+ /*
5376+ * Register the Shutdown Notification hook in the kernel.
5377+ */
5378+ register_reboot_notifier(&ite_notifier);
5379+
5380+ /*
5381+ * Initialize ioctl semphore.
5382+ */
5383+ init_MUTEX(&mimd_entry_mtx);
5384+ }
5385+
5386+ dprintk("iteraid_detect exit\n");
5387+ return 1;
5388+
5389+} /* end iteraid_detect() */
5390+
5391+/************************************************************************
5392+ * Name: iteraid_release
5393+ * Description: Release resources allocated for a single each adapter.
5394+ * Parameters: pshost - Pointer to SCSI command structure.
5395+ * Returns: zero.
5396+ ************************************************************************/
5397+int
5398+iteraid_release(struct Scsi_Host *pshost)
5399+{
5400+
5401+ u8 i;
5402+ PITE_ADAPTER pAdap;
5403+
5404+ /*
5405+ * Unregister the character device.
5406+ */
5407+ if (ite_major > 0)
5408+ {
5409+ unregister_chrdev(ite_major, "itedev");
5410+ ite_major = -1;
5411+ }
5412+
5413+ /*
5414+ * Free irq and memory.
5415+ */
5416+ for (i = 0; i < NumAdapters; i++)
5417+ {
5418+ pAdap = ite_adapters[i];
5419+
5420+ if (pAdap->irqOwned) free_irq(pAdap->irq, pAdap);
5421+ if (pAdap->IDEChannel != NULL) { kfree(pAdap->IDEChannel); }
5422+ if (pAdap != NULL) { kfree(pAdap); }
5423+ }
5424+
5425+ /*
5426+ * Unregister the reboot notifier.
5427+ */
5428+ unregister_reboot_notifier(&ite_notifier);
5429+
5430+ /*
5431+ * Tell kernel scsi-layer we are gone.
5432+ */
5433+ scsi_unregister(pshost);
5434+
5435+ return 0;
5436+
5437+} /* end iteraid_Release */
5438+
5439+/************************************************************************
5440+ * This is the new scsi eh reset function.
5441+ ************************************************************************/
5442+int
5443+iteraid_reset_eh(Scsi_Cmnd *SCpnt)
5444+{
5445+
5446+ u8 i;
5447+ u8 j;
5448+ PChannel pChan;
5449+ PITE_ADAPTER pAdap;
5450+
5451+ if (SCpnt == NULL)
5452+ {
5453+ printk("iteraid_reset_eh: invalid Scsi_Cmnd\n");
5454+ return FAILED;
5455+ }
5456+
5457+ for (i = 0; i < NumAdapters; i++)
5458+ {
5459+ pAdap = ite_adapters[i];
5460+ for (j = 0; j < pAdap->num_channels; j++)
5461+ {
5462+ pChan = &pAdap->IDEChannel[j];
5463+ AtapiResetController(pAdap, pChan);
5464+ }
5465+ }
5466+
5467+ return SUCCESS;
5468+
5469+} /* end iteraid_reset_eh */
5470+
5471+/************************************************************************
5472+ * The new error handling code.
5473+ ************************************************************************/
5474+int
5475+iteraid_abort_eh(Scsi_Cmnd *SCpnt)
5476+{
5477+
5478+ if (SCpnt == NULL)
5479+ {
5480+ printk("iteraid_reset_eh: invalid Scsi_Cmnd\n");
5481+ return FAILED;
5482+ }
5483+
5484+ return SUCCESS;
5485+
5486+} /* end iteraid_abort_eh */
5487+
5488+/************************************************************************
5489+ * Name: iteraid_biosparam
5490+ * Description: Process the biosparam request from the SCSI manager to
5491+ * return C/H/S data.
5492+ * Parameters: disk - Pointer to SCSI disk structure.
5493+ * dev - Major/minor number from kernel.
5494+ * geom - Pointer to integer array to place geometry data.
5495+ * Returns: zero.
5496+ ************************************************************************/
5497+int
5498+iteraid_biosparam
5499+(
5500+ struct scsi_device * sdev,
5501+ struct block_device * bdev,
5502+ sector_t capacity,
5503+ int geom[]
5504+)
5505+{
5506+
5507+ int heads;
5508+ int sectors;
5509+ int cylinders;
5510+
5511+ /*
5512+ * Default heads (64) & sectors (32)
5513+ * Handle extended translation size for logical drives > 1Gb
5514+ */
5515+ if (capacity >= 0x200000)
5516+ {
5517+ heads = 255;
5518+ sectors = 63;
5519+ }
5520+ else
5521+ {
5522+ heads = 64;
5523+ sectors = 32;
5524+ }
5525+
5526+ cylinders = (unsigned long)capacity / (heads * sectors);
5527+
5528+ /*
5529+ * Return result
5530+ */
5531+ geom[0] = heads;
5532+ geom[1] = sectors;
5533+ geom[2] = cylinders;
5534+
5535+ return 0;
5536+
5537+} /* end iteraid_biosparam */
5538+
5539+/************************************************************************
5540+ * Shutdown routine.
5541+ ************************************************************************/
5542+static int
5543+ite_halt(struct notifier_block *nb, ulong event, void *buf)
5544+{
5545+
5546+ if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5547+ {
5548+ return NOTIFY_DONE;
5549+ }
5550+
5551+ unregister_reboot_notifier(&ite_notifier);
5552+
5553+ return NOTIFY_OK;
5554+
5555+} /* end ite_halt */
5556+
5557+/************************************************************************
5558+ * PROC information.
5559+ ************************************************************************/
5560+int
5561+iteraid_proc_info
5562+(
5563+ struct Scsi_Host * shost,
5564+ char * buffer,
5565+ char ** start,
5566+ off_t offset,
5567+ int length,
5568+ int inout
5569+)
5570+{
5571+
5572+ return 0;
5573+
5574+} /* end iteraid_proc_info */
5575+
5576+/************************************************************************
5577+ * IOCTL open entry.
5578+ ************************************************************************/
5579+static int
5580+itedev_open(struct inode *inode, struct file *filep)
5581+{
5582+
5583+ MOD_INC_USE_COUNT;
5584+
5585+ return 0;
5586+
5587+} /* end itedev_open */
5588+
5589+/************************************************************************
5590+ * IOCTL code entry.
5591+ ************************************************************************/
5592+static int
5593+itedev_ioctl_entry
5594+(
5595+ struct inode * inode,
5596+ struct file * filep,
5597+ unsigned int cmd,
5598+ unsigned long arg
5599+)
5600+{
5601+
5602+ int ret = -1;
5603+
5604+ /*
5605+ * We do not allow parallel ioctls to the driver as of now.
5606+ */
5607+ down(&mimd_entry_mtx);
5608+ ret = itedev_ioctl(inode, filep, cmd, arg);
5609+ up(&mimd_entry_mtx);
5610+
5611+ return ret;
5612+
5613+} /* end itedev_ioctl_entry */
5614+
5615+/************************************************************************
5616+ * Real IOCTL function handles ioctl for the character device.
5617+ ************************************************************************/
5618+static int
5619+itedev_ioctl
5620+(
5621+ struct inode * inode,
5622+ struct file * filep,
5623+ unsigned int cmd,
5624+ unsigned long arg
5625+)
5626+{
5627+
5628+ u8 diskArrayId;
5629+ u8 statusByte = 0;
5630+ u8 srbStatus;
5631+ u8 progress = 0;
5632+ u8 status = 0;
5633+ uioctl_t * pioc;
5634+ PITE_ADAPTER pAdap;
5635+ PChannel pChan;
5636+ PRAID_REBUILD_INFO rebuild_info;
5637+ dprintk("itedev_ioctl enter\n");
5638+
5639+ /*
5640+ * Extract the type and number bitfield.
5641+ */
5642+ if (_IOC_TYPE(cmd) != ITE_IOCMAGIC) return -EINVAL;
5643+
5644+ /*
5645+ * Allocate space for ioctl data structure.
5646+ */
5647+ if ((pioc = kmalloc(sizeof(uioctl_t), GFP_KERNEL)) == NULL)
5648+ {
5649+ printk("itedev_ioctl: error kmalloc on ioctl\n");
5650+ return -ENOMEM;
5651+ }
5652+
5653+ /*
5654+ * Get the user ioctl structure.
5655+ */
5656+ if (copy_from_user(pioc, (uioctl_t *)arg, sizeof(uioctl_t)))
5657+ {
5658+ kfree(pioc);
5659+ return -EFAULT;
5660+ }
5661+
5662+ /*
5663+ * Check which command to do.
5664+ */
5665+ switch (cmd)
5666+ {
5667+ case ITE_IOC_GET_PHY_DISK_STATUS:
5668+ dprintk("ITE_IOC_GET_PHY_DISK_STATUS\n");
5669+
5670+ /*
5671+ * Get the physical disk status.
5672+ */
5673+ status = IT8212GetChipStatus(pioc);
5674+ return 0;
5675+
5676+ case ITE_IOC_CREATE_DISK_ARRAY:
5677+ dprintk("ITE_IOC_CREATE_DISK_ARRAY\n");
5678+
5679+ /*
5680+ * Create disk array.
5681+ */
5682+ status = IT8212CreateDiskArray(pioc);
5683+
5684+ if (status != SRB_STATUS_SUCCESS) return status;
5685+
5686+ status = IT8212ErasePartition(pioc);
5687+ return 0;
5688+
5689+ case ITE_IOC_REBUILD_START:
5690+ dprintk("ITE_IOC_REBUILD_START\n");
5691+
5692+ /*
5693+ * Rebuild array.
5694+ */
5695+ status = IT8212Rebuild(pioc);
5696+ put_user(status, (u8 *)pioc->data);
5697+ return 0;
5698+
5699+ case ITE_IOC_GET_REBUILD_STATUS:
5700+ dprintk("ITE_IOC_GET_REBUILD_STATUS\n");
5701+
5702+ pAdap = ite_adapters[0];
5703+
5704+ /*
5705+ * Get the rebuild disk ID.
5706+ */
5707+ rebuild_info = (PRAID_REBUILD_INFO) pioc->data;
5708+ diskArrayId = rebuild_info->DiskArrayId;
5709+
5710+ /*
5711+ * Select channel.
5712+ */
5713+ if (diskArrayId < 2)
5714+ {
5715+ pChan = &pAdap->IDEChannel[0];
5716+ }
5717+ else
5718+ {
5719+ pChan = &pAdap->IDEChannel[1];
5720+ }
5721+
5722+ /*
5723+ * Select device.
5724+ */
5725+ outb(((u8) (diskArrayId << 4) | 0xA0),
5726+ pChan->io_ports[IDE_SELECT_OFFSET]);
5727+
5728+ /*
5729+ * Wait for device ready (not BUSY and not DRQ).
5730+ */
5731+ WaitForDeviceReady(pChan, statusByte);
5732+ if ((statusByte & IDE_STATUS_BUSY) || (statusByte & IDE_STATUS_DRQ) ||
5733+ (statusByte == 0))
5734+ {
5735+ printk("IT8212GetRebuildStatus: Disk[%d] busy. Status=0x%X\n",
5736+ diskArrayId, statusByte);
5737+ srbStatus = SRB_STATUS_BUSY;
5738+ goto exit;
5739+ }
5740+
5741+ /*
5742+ * Disable interrupt to avoid the unexpected interrupt.
5743+ */
5744+ outb(IDE_DC_DISABLE_INTERRUPTS, pChan->io_ports[IDE_CONTROL_OFFSET]);
5745+
5746+ /*
5747+ * Issue command.
5748+ */
5749+ outb(IDE_COMMAND_REBUILD_STATUS, pChan->io_ports[IDE_COMMAND_OFFSET]);
5750+
5751+ /*
5752+ * Check error.
5753+ */
5754+ WaitForCommandComplete(pChan, statusByte);
5755+
5756+ /*
5757+ * Reenable interrupt after command complete.
5758+ */
5759+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]);
5760+
5761+ if (statusByte != IDE_STATUS_IDLE)
5762+ {
5763+ srbStatus = SRB_STATUS_ERROR;
5764+ printk("GetRebuildStatus: ERROR\n");
5765+ goto exit;
5766+ }
5767+
5768+ progress = inb(pChan->io_ports[IDE_NSECTOR_OFFSET]);
5769+ srbStatus = SRB_STATUS_SUCCESS;
5770+
5771+ if (progress != 0xFF) progress = 0x64 - progress;
5772+
5773+ /*
5774+ * Put the rebuild status to user space.
5775+ */
5776+ put_user(progress, (u8 *)pioc->data);
5777+
5778+exit:
5779+ return 0;
5780+
5781+ case ITE_IOC_RESET_ADAPTER:
5782+ dprintk("ITE_IOC_RESET_ADAPTER\n");
5783+
5784+ /*
5785+ * Reset the adapter.
5786+ */
5787+# if (0)
5788+ status = IT8212ResetAdapter();
5789+# endif
5790+
5791+ /*
5792+ * Return TURE or FALSE to user space.
5793+ */
5794+ put_user(status, (u8 *)arg);
5795+ return 0;
5796+
5797+ case ITE_IOC_GET_DRIVER_VERSION:
5798+ dprintk("ITE_IOC_GET_DRIVER_VERSION\n");
5799+
5800+ /*
5801+ * Get the current driver version.
5802+ */
5803+ put_user(driver_ver, (int *)arg);
5804+ return 0;
5805+
5806+ default:
5807+ return -EINVAL;
5808+
5809+ } /* end switch */
5810+
5811+} /* end itedev_ioctl */
5812+
5813+/************************************************************************
5814+ * IOCTL close routine.
5815+ ************************************************************************/
5816+static int
5817+itedev_close(struct inode *inode, struct file *filep)
5818+{
5819+
5820+ MOD_DEC_USE_COUNT;
5821+
5822+ return 0;
5823+
5824+} /* end itedev_close */
5825+
5826+/************************************************************************
5827+ * Scsi_Host_Template Initializer
5828+ ************************************************************************/
5829+static Scsi_Host_Template driver_template =
5830+{
5831+ .proc_name = "IT8212",
5832+ .proc_info = iteraid_proc_info,
5833+ .name = "ITE RAIDExpress133",
5834+ .detect = iteraid_detect,
5835+ .release = iteraid_release,
5836+ .queuecommand = iteraid_queuecommand,
5837+ .eh_abort_handler = iteraid_abort_eh,
5838+ .eh_host_reset_handler = iteraid_reset_eh,
5839+ .bios_param = iteraid_biosparam,
5840+ .can_queue = 1,
5841+ .this_id = -1,
5842+ .sg_tablesize = 32,
5843+ .max_sectors = 256,
5844+ .cmd_per_lun = 1,
5845+ .use_clustering = DISABLE_CLUSTERING,
5846+ .emulated = 1
5847+};
5848+#include "scsi_module.c"
5849diff -Nur --exclude '*.orig' linux-2.6.8.1.org/drivers/scsi/iteraid.h linux-2.6.8.1/drivers/scsi/iteraid.h
5850--- linux-2.6.8.1.org/drivers/scsi/iteraid.h 1970-01-01 01:00:00.000000000 +0100
5851+++ linux-2.6.8.1/drivers/scsi/iteraid.h 2004-05-11 10:09:04.000000000 +0200
5852@@ -0,0 +1,1514 @@
5853+/*
5854+ * linux/drivers/scsi/iteraid.h
5855+ *
5856+ * (C) Copyright 2002-2004 ITE Tech, inc.
5857+ *
5858+ * Nov 11, 2002 Mark Lu file created.
5859+ *
5860+ * This program is free software; you can redistribute it and/or modify it
5861+ * under the terms of the GNU General Public License as published by the
5862+ * Free Software Foundation; either version 2, or (at your option) any
5863+ * later version.
5864+ *
5865+ * This program is distributed in the hope that it will be useful, but
5866+ * WITHOUT ANY WARRANTY; without even the implied warranty of
5867+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
5868+ * General Public License for more details.
5869+ *
5870+ * ITE IT8212 RAID Controller device driver header for Linux.
5871+ */
5872+
5873+#ifndef _ITERAID_H_
5874+#define _ITERAID_H_
5875+
5876+#include <linux/version.h>
5877+#include <linux/types.h>
5878+
5879+#define ITE_VENDOR_ID 0x1283 /* Vendor ID (ITE) */
5880+#define ITE_DEVICE_ID 0x8212 /* Device IF (IT8212) */
5881+#define MAX_ADAPTERS 2 /* Max Board supported */
5882+#define MAX_DEVICES (MAX_ADAPTERS * 4) /* Max Dev supported */
5883+
5884+#define TRUE 1
5885+#define FALSE 0
5886+
5887+/*
5888+ * Undef macros which may conflict
5889+ */
5890+#undef START_STOP
5891+
5892+/************************************************************************
5893+ * Debugging macro
5894+ ************************************************************************/
5895+#ifdef ITE_DEBUG
5896+#define dprintk(msg...) printk(msg)
5897+#else
5898+#define dprintk(msg...) do { } while(0)
5899+#endif
5900+
5901+/************************************************************************
5902+ * Raid level definitions
5903+ ************************************************************************/
5904+#define RAID_LEVEL_0 0
5905+#define RAID_LEVEL_1 1
5906+#define RAID_LEVEL_10 2
5907+#define RAID_LEVEL_JBOD 3
5908+#define RAID_LEVEL_NORMAL 4
5909+#define RAID_LEVEL_NODISK 5
5910+
5911+/************************************************************************
5912+ * Physical disk status definitions
5913+ ************************************************************************/
5914+#define DISK_KEY_OFF 0
5915+#define DISK_OFF_LINE 1
5916+#define DISK_ON_LINE 2
5917+#define DISK_REBUILDING 3
5918+#define DISK_PLUGGING 4
5919+#define DISK_PLUGGING_OK 5
5920+
5921+#define MaximumLBAOf28Bit 0x10000000
5922+
5923+#define DisableChannel 1
5924+#define EnableChannel 2
5925+
5926+#define CABLE_40_PIN 0
5927+#define CABLE_80_PIN 1
5928+
5929+#define RaidActive 0
5930+#define RaidInactive 1
5931+
5932+#define IDE_CLOCK_66 0
5933+#define IDE_CLOCK_50 1
5934+
5935+#define USE_ULTRA_DMA 0
5936+#define USE_MULTIWORD_DMA 1
5937+
5938+/************************************************************************
5939+ * Vendor specific information
5940+ ************************************************************************/
5941+typedef struct _PHYSICAL_DISK_STATUS
5942+{
5943+ u8 ModelNumber[40]; /* Byte 00-39 */
5944+ u32 UserAddressableSectors_LOW; /* Byte 40-43 */
5945+ u32 UserAddressableSectors_HIGH; /* Byte 44-47 */
5946+ u8 MultiWordDMASupport; /* Byte 48 */
5947+ u8 MultiWordDMAActive; /* Byte 49 */
5948+ u8 UltraDMASupport; /* Byte 50 */
5949+ u8 UltraDMAActive; /* Byte 51 */
5950+ u8 RaidType; /* Byte 52 */
5951+ u8 RaidNumber; /* Byte 53 */
5952+ u8 SerialNumber[20]; /* Byte 54-73 */
5953+ u8 DiskStatus; /* Byte 74 */
5954+ u8 DiskOriginalLocation; /* Byte 75 */
5955+ u8 Cable80Pin; /* Byte 76 */
5956+ u8 BootableDisk; /* Byte 77 */
5957+ u8 StorageSize[8]; /* Byte 78-85 */
5958+ u8 Reserved[35]; /* Byte 86-120 */
5959+ u8 UpdateYear; /* Byte 121 */
5960+ u8 UpdateMonth; /* Byte 122 */
5961+ u8 UpdateDay; /* Byte 123 */
5962+ u8 FirmwareVer; /* Byte 124 */
5963+ u8 RebuildStatus; /* Byte 125 */
5964+ u8 StripeSize; /* Byte 126 */
5965+ u8 AutoRebuildEnable; /* Byte 127 */
5966+} PHYSICAL_DISK_STATUS, *PPHYSICAL_DISK_STATUS;
5967+
5968+/************************************************************************
5969+ * vendor specific information
5970+ ************************************************************************/
5971+typedef struct _IT8212_SET_CHIP_STATUS_INFO
5972+{
5973+ u16 RaidType; /* Word 129 */
5974+ u16 ContainingDisks; /* Word 130 */
5975+ u16 UltraDmaTiming01; /* Word 131 */
5976+ u16 UltraDmaTiming23; /* Word 132 */
5977+ u16 UltraDmaTiming45; /* Word 133 */
5978+ u16 UltraDmaTiming6; /* Word 134 */
5979+ u16 MultiWordDmaTiming01; /* Word 135 */
5980+ u16 UltraDmaTiming2; /* Word 136 */
5981+ u16 PioTiming4; /* Word 137 */
5982+ u16 AutoRebuildEnable; /* Word 138 */
5983+ u16 IdeClkUDma01; /* Word 139 */
5984+ u16 IdeClkUDma23; /* Word 140 */
5985+ u16 IdeClkUDma45; /* Word 141 */
5986+ u16 IdeClkUDma6; /* Word 142 */
5987+ u16 IdeClkMDma01; /* Word 143 */
5988+ u16 IdeClkMDma2; /* Word 144 */
5989+ u16 IdeClkPio4; /* Word 145 */
5990+ u16 StripeSize; /* Word 146 */
5991+ u16 BootableDisk; /* Word 147 */
5992+ u16 CheckHotSwapInterval; /* Word 148 */
5993+ u16 TargetSourceDisk; /* Word 149 */
5994+ u16 RebuildBlockSize; /* Word 150 */
5995+ u16 ResetInterval1; /* Word 151 */
5996+ u16 ResetInterval2; /* Word 152 */
5997+ u16 RebuildRetryTimes; /* Word 153 */
5998+ u16 NewlyCreated; /* Word 154 */
5999+} IT8212_SET_CHIP_STATUS_INFO, *PIT8212_SET_CHIP_STATUS_INFO;
6000+
6001+/************************************************************************
6002+ * Serial number written to HDD (20 bytes)
6003+ ************************************************************************/
6004+typedef struct _RAID_SERIAL_NUMBER
6005+{
6006+ u16 Year;
6007+ u8 Month;
6008+ u8 Date;
6009+ u8 Day;
6010+ u8 Hour;
6011+ u8 Minute;
6012+ u8 Second;
6013+ u8 MiniSec;
6014+ u8 RaidType;
6015+ u8 ContainingDisks;
6016+ u8 DontCare[9];
6017+} RAID_SERIAL_NUMBER, *PRAID_SERIAL_NUMBER;
6018+
6019+/************************************************************************
6020+ * Disk array create information
6021+ *
6022+ * Following items index definition
6023+ * 0: Primary Master
6024+ * 1: Secondary Master
6025+ * 2: Primary Slave
6026+ * 3: Secondary Slave
6027+ ************************************************************************/
6028+typedef struct _RAID_CREATE_INFO
6029+{
6030+ u8 DiskArrayId;
6031+ RAID_SERIAL_NUMBER SerialNumber;
6032+ u8 ModelNumber[40];
6033+ u16 RaidType;
6034+ u16 ContainingDisks;
6035+ u16 AutoRebuildEnable;
6036+ u16 StripeSize;
6037+ u16 BootableDisk;
6038+ u16 TargetSourceDisk;
6039+ u8 ErasePartition;
6040+ u8 DMASupported[4];
6041+ u8 UDMASupported[4];
6042+ u8 AddressableSectors[4];
6043+ u8 NewlyCreated;
6044+ u8 Reserved;
6045+} RAID_CREATE_INFO, *PRAID_CREATE_INFO;
6046+
6047+/************************************************************************
6048+ * Rebuild data structure
6049+ ************************************************************************/
6050+typedef struct _RAID_REBUILD_INFO
6051+{
6052+ u8 DiskArrayId; /* Virtual device number (0-3) */
6053+ u8 SrcDisk; /* Source disk (0-3) */
6054+ u8 DestDisk; /* Destination disk (0-3) */
6055+ u8 Resume; /* 1: Resume the last time rebuild */
6056+ /* 0: Rebuild from LBA 0 */
6057+ u8 Status; /* Indicate the status of the current */
6058+ /* rebuild command filled by drivers */
6059+ u8 Reserved[3]; /* For aligement */
6060+} RAID_REBUILD_INFO, *PRAID_REBUILD_INFO;
6061+
6062+/************************************************************************
6063+ * ATA transfer modes
6064+ ************************************************************************/
6065+#define PIO_DEFAULT 0x00
6066+#define PIO_DEFAULT_IORDY_DISABLE 0x01
6067+#define PIO_FLOW_CONTROL 0x08
6068+#define SINGLEWORD_DMA 0x10
6069+#define MULTIWORD_DMA 0x20
6070+#define ULTRA_DMA 0x40
6071+
6072+#define ITE_DRV_SIGNATURE "ITE RAID CONTROLLER"
6073+#define ITE_DRV_BYPASS "ITE BYPASS MODE"
6074+
6075+/************************************************************************
6076+ * Extra IDE commands supported by Accusys
6077+ ************************************************************************/
6078+#define IDE_COMMAND_GET_CHIP_STATUS 0xFA
6079+#define IDE_COMMAND_SET_CHIP_STATUS 0xFB
6080+#define IDE_COMMAND_REBUILD 0xFC
6081+#define IDE_COMMAND_REBUILD_STATUS 0xFD
6082+
6083+#define REBUILD_ERR_WRONG_ARRAY_TYPE 0x01
6084+#define REBUILD_ERR_DISK_TOO_SMALL 0x02
6085+#define REBUILD_ERR_SRC_DISK_LOCATION_INCORRECT 0x03
6086+#define REBUILD_ERR_SRC_DISK_OFFLINE 0x04
6087+#define REBUILD_ERR_DEST_DISK_OFFLINE 0x05
6088+#define REBUILD_ERR_DISK_BUSY 0x10
6089+
6090+/************************************************************************
6091+ * ATA transfer modes
6092+ ************************************************************************/
6093+#define PIO_DEFAULT 0x00
6094+#define PIO_DEFAULT_IORDY_DISABLE 0x01
6095+#define PIO_FLOW_CONTROL 0x08
6096+#define SINGLEWORD_DMA 0x10
6097+#define MULTIWORD_DMA 0x20
6098+#define ULTRA_DMA 0x40
6099+
6100+/************************************************************************
6101+ * IDE registers offset
6102+ ************************************************************************/
6103+#define IDE_NR_PORTS 10
6104+
6105+#define IDE_DATA_OFFSET 0
6106+#define IDE_ERROR_OFFSET 1
6107+#define IDE_NSECTOR_OFFSET 2
6108+#define IDE_LOCYL_OFFSET 3
6109+#define IDE_MIDCYL_OFFSET 4
6110+#define IDE_HCYL_OFFSET 5
6111+#define IDE_SELECT_OFFSET 6
6112+#define IDE_STATUS_OFFSET 7
6113+#define IDE_CONTROL_OFFSET 8
6114+#define IDE_IRQ_OFFSET 9
6115+
6116+#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
6117+#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
6118+#define IDE_ALTERNATE_OFFSET IDE_CONTROL_OFFSET
6119+
6120+/************************************************************************
6121+ * ATAPI registers offset
6122+ ************************************************************************/
6123+#define ATAPI_DATA_OFFSET 0
6124+#define ATAPI_ERROR_OFFSET 1
6125+#define ATAPI_INTREASON_OFFSET 2
6126+#define ATAPI_UNUSED1_OFFSET 3
6127+#define ATAPI_LCYL_OFFSET 4
6128+#define ATAPI_HCYL_OFFSET 5
6129+#define ATAPI_SELECT_OFFSET 6
6130+#define ATAPI_STATUS_OFFSET 7
6131+#define ATAPI_CONTROL_OFFSET 8
6132+
6133+#define ATAPI_COMMAND_OFFSET ATAPI_STATUS_OFFSET
6134+#define ATAPI_FEATURE_OFFSET ATAPI_ERROR_OFFSET
6135+
6136+/************************************************************************
6137+ * Following structures are according to SPC-3 (by Chanel)
6138+ ************************************************************************/
6139+typedef struct _SCSI_MODE_SENSE6
6140+{
6141+ u8 OperationCode;
6142+ u8 Reserved1 : 3;
6143+ u8 Dbd : 1;
6144+ u8 Reserved2 : 4;
6145+ u8 PageCode : 6;
6146+ u8 Pc : 2;
6147+ u8 SubpageCode;
6148+ u8 AllocationLength;
6149+ u8 Control;
6150+} SCSI_MODE_SENSE6, *PSCSI_MODE_SENSE6;
6151+
6152+typedef struct _SCSI_MODE_SENSE10
6153+{
6154+ u8 OperationCode;
6155+ u8 Reserved1 : 3;
6156+ u8 Dbd : 1;
6157+ u8 LLBAA : 1;
6158+ u8 Reserved2 : 3;
6159+ u8 PageCode : 6;
6160+ u8 Pc : 2;
6161+ u8 SubpageCode;
6162+ u8 Reserved3[3];
6163+ u8 AllocationLengthMsb;
6164+ u8 AllocationLengthLsb;
6165+ u8 Control;
6166+} SCSI_MODE_SENSE10, *PSCSI_MODE_SENSE10;
6167+
6168+typedef struct _SCSI_MODE_SELECT6
6169+{
6170+ u8 OperationCode;
6171+ u8 SPBit : 1;
6172+ u8 Reserved1 : 3;
6173+ u8 PFBit : 1;
6174+ u8 Reserved2 : 3;
6175+ u8 Reserved3[2];
6176+ u8 ParameterListLength;
6177+ u8 Control;
6178+} SCSI_MODE_SELECT6, *PSCSI_MODE_SELECT6;
6179+
6180+typedef struct _SCSI_MODE_SELECT10
6181+{
6182+ u8 OperationCode;
6183+ u8 SPBit : 1;
6184+ u8 Reserved1 : 3;
6185+ u8 PFBit : 1;
6186+ u8 Reserved2 : 3;
6187+ u8 Reserved3[5];
6188+ u8 ParameterListLengthMsb;
6189+ u8 ParameterListLengthLsb;
6190+ u8 Control;
6191+} SCSI_MODE_SELECT10, *PSCSI_MODE_SELECT10;
6192+
6193+typedef struct _SCSI_MODE_PARAMETER_HEADER6
6194+{
6195+ u8 ModeDataLength;
6196+ u8 MediumType;
6197+ u8 DeviceSpecificParameter;
6198+ u8 BlockDescriptorLength;
6199+} SCSI_MODE_PARAMETER_HEADER6, *PSCSI_MODE_PARAMETER_HEADER6;
6200+
6201+typedef struct _SCSI_MODE_PARAMETER_HEADER10
6202+{
6203+ u8 ModeDataLengthMsb;
6204+ u8 ModeDataLengthLsb;
6205+ u8 MediumType;
6206+ u8 DeviceSpecificParameter;
6207+ u8 Reserved[2];
6208+ u8 BlockDescriptorLengthMsb;
6209+ u8 BlockDescriptorLengthLsb;
6210+} SCSI_MODE_PARAMETER_HEADER10, *PSCSI_MODE_PARAMETER_HEADER10;
6211+
6212+typedef struct _SCSI_MODE_PARAMTER_BLOCK_DESCRIPTER
6213+{
6214+ u8 DesityCode;
6215+ u8 NumberOfBlocks2;
6216+ u8 NumberOfBlocks1;
6217+ u8 NumberOfBlocks0;
6218+ u8 Reserved;
6219+ u8 BlockLength2;
6220+ u8 BlockLength1;
6221+ u8 BlockLength0;
6222+} SCSI_MODE_PARAMTER_BLOCK_DESCRIPTER, *PSCSI_MODE_PARAMTER_BLOCK_DESCRIPTER;
6223+
6224+/************************************************************************
6225+ * IDE command definitions
6226+ ************************************************************************/
6227+#define IDE_COMMAND_ATAPI_RESET 0x08
6228+#define IDE_COMMAND_RECALIBRATE 0x10
6229+#define IDE_COMMAND_READ_SECTOR 0x20
6230+#define IDE_COMMAND_READ_SECTOR_EXT 0x24
6231+#define IDE_COMMAND_READ_DMA_EXT 0x25
6232+#define IDE_COMMAND_READ_MULTIPLE_EXT 0x29
6233+#define IDE_COMMAND_WRITE_SECTOR 0x30
6234+#define IDE_COMMAND_WRITE_SECTOR_EXT 0x34
6235+#define IDE_COMMAND_WRITE_DMA_EXT 0x35
6236+#define IDE_COMMAND_WRITE_MULTIPLE_EXT 0x39
6237+#define IDE_COMMAND_READ_VERIFY 0x40
6238+#define IDE_COMMAND_READ_VERIFY_EXT 0x42
6239+#define IDE_COMMAND_SEEK 0x70
6240+#define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
6241+#define IDE_COMMAND_ATAPI_PACKET 0xA0
6242+#define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
6243+#define IDE_COMMAND_READ_MULTIPLE 0xC4
6244+#define IDE_COMMAND_WRITE_MULTIPLE 0xC5
6245+#define IDE_COMMAND_SET_MULTIPLE 0xC6
6246+#define IDE_COMMAND_READ_DMA 0xC8
6247+#define IDE_COMMAND_WRITE_DMA 0xCA
6248+#define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
6249+#define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
6250+#define IDE_COMMAND_SET_FEATURE 0xEF
6251+#define IDE_COMMAND_IDENTIFY 0xEC
6252+#define IDE_COMMAND_MEDIA_EJECT 0xED
6253+
6254+/************************************************************************
6255+ * IDE status definitions
6256+ ************************************************************************/
6257+#define IDE_STATUS_ERROR 0x01
6258+#define IDE_STATUS_INDEX 0x02
6259+#define IDE_STATUS_CORRECTED_ERROR 0x04
6260+#define IDE_STATUS_DRQ 0x08
6261+#define IDE_STATUS_DSC 0x10
6262+#define IDE_STATUS_DRDY 0x40
6263+#define IDE_STATUS_IDLE 0x50
6264+#define IDE_STATUS_BUSY 0x80
6265+
6266+/************************************************************************
6267+ * IDE drive control definitions.
6268+ ************************************************************************/
6269+#define IDE_DC_DISABLE_INTERRUPTS 0x02
6270+#define IDE_DC_RESET_CONTROLLER 0x04
6271+#define IDE_DC_REENABLE_CONTROLLER 0x00
6272+
6273+/************************************************************************
6274+ * IDE error definitions.
6275+ ************************************************************************/
6276+#define IDE_ERROR_BAD_BLOCK 0x80
6277+#define IDE_ERROR_DATA_ERROR 0x40
6278+#define IDE_ERROR_MEDIA_CHANGE 0x20
6279+#define IDE_ERROR_ID_NOT_FOUND 0x10
6280+#define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
6281+#define IDE_ERROR_COMMAND_ABORTED 0x04
6282+#define IDE_ERROR_END_OF_MEDIA 0x02
6283+#define IDE_ERROR_ILLEGAL_LENGTH 0x01
6284+
6285+/************************************************************************
6286+ * IDENTIFY data.
6287+ ************************************************************************/
6288+typedef struct _IDENTIFY_DATA
6289+{
6290+ u16 GeneralConfiguration; /* 00 00 */
6291+ u16 NumberOfCylinders; /* 02 1 */
6292+ u16 Reserved1; /* 04 2 */
6293+ u16 NumberOfHeads; /* 06 3 */
6294+ u16 UnformattedBytesPerTrack; /* 08 4 */
6295+ u16 UnformattedBytesPerSector; /* 0A 5 */
6296+ u16 SectorsPerTrack; /* 0C 6 */
6297+ u16 VendorUnique1[3]; /* 0E 7-9 */
6298+ u16 SerialNumber[10]; /* 14 10-19 */
6299+ u16 BufferType; /* 28 20 */
6300+ u16 BufferSectorSize; /* 2A 21 */
6301+ u16 NumberOfEccBytes; /* 2C 22 */
6302+ u16 FirmwareRevision[4]; /* 2E 23-26 */
6303+ u16 ModelNumber[20]; /* 36 27-46 */
6304+ u8 MaximumBlockTransfer; /* 5E 47 */
6305+ u8 VendorUnique2; /* 5F */
6306+ u16 DoubleWordIo; /* 60 48 */
6307+ u16 Capabilities; /* 62 49 */
6308+ u16 Reserved2; /* 64 50 */
6309+ u8 VendorUnique3; /* 66 51 */
6310+ u8 PioCycleTimingMode; /* 67 */
6311+ u8 VendorUnique4; /* 68 52 */
6312+ u8 DmaCycleTimingMode; /* 69 */
6313+ u16 TranslationFieldsValid : 1; /* 6A 53 */
6314+ u16 Reserved3 : 15; /* */
6315+ u16 NumberOfCurrentCylinders; /* 6C 54 */
6316+ u16 NumberOfCurrentHeads; /* 6E 55 */
6317+ u16 CurrentSectorsPerTrack; /* 70 56 */
6318+ u32 CurrentSectorCapacity; /* 72 57-58 */
6319+ u16 CurrentMultiSectorSetting; /* 59 */
6320+ u32 UserAddressableSectors; /* 60-61 */
6321+ u16 SingleWordDMASupport : 8; /* 62 */
6322+ u16 SingleWordDMAActive : 8; /* */
6323+ u16 MultiWordDMASupport : 8; /* 63 */
6324+ u16 MultiWordDMAActive : 8; /* */
6325+ u16 AdvancedPIOModes : 8; /* 64 */
6326+ u16 Reserved4 : 8; /* */
6327+ u16 MinimumMWXferCycleTime; /* 65 */
6328+ u16 RecommendedMWXferCycleTime; /* 66 */
6329+ u16 MinimumPIOCycleTime; /* 67 */
6330+ u16 MinimumPIOCycleTimeIORDY; /* 68 */
6331+ u16 Reserved5[2]; /* 69-70 */
6332+ u16 ReleaseTimeOverlapped; /* 71 */
6333+ u16 ReleaseTimeServiceCommand; /* 72 */
6334+ u16 MajorRevision; /* 73 */
6335+ u16 MinorRevision; /* 74 */
6336+ u16 Reserved6[50]; /* 75-126 */
6337+ u16 SpecialFunctionsEnabled; /* 127 */
6338+ u16 Reserved7[128]; /* 128-255 */
6339+} IDENTIFY_DATA, *PIDENTIFY_DATA;
6340+
6341+/************************************************************************
6342+ * Identify data without the Reserved4.
6343+ ************************************************************************/
6344+typedef struct _IDENTIFY_DATA2
6345+{
6346+ u16 GeneralConfiguration; /* 00 */
6347+ u16 NumberOfCylinders; /* 01 */
6348+ u16 Reserved1; /* 02 */
6349+ u16 NumberOfHeads; /* 03 */
6350+ u16 Reserved2[2]; /* 04-05 */
6351+ u16 SectorsPerTrack; /* 06 */
6352+ u16 Reserved3[3]; /* 07-09 */
6353+ u16 SerialNumber[10]; /* 10-19 */
6354+ u16 Reserved4[3]; /* 20-22 */
6355+ u16 FirmwareRevision[4]; /* 23-26 */
6356+ u16 ModelNumber[20]; /* 27-46 */
6357+ u16 MaximumBlockTransfer; /* 47 */
6358+ u16 Reserved5; /* 48 */
6359+ u16 Capabilities[2]; /* 49-50 */
6360+ u16 Reserved6[2]; /* 51-52 */
6361+ u16 ValidFieldIndicator; /* 53 */
6362+ u16 NumberOfCurrentCylinders; /* 54 */
6363+ u16 NumberOfCurrentHeads; /* 55 */
6364+ u16 CurrentSectorsPerTrack; /* 56 */
6365+ u16 CurrentSectorCapacityLow; /* 57 */
6366+ u16 CurrentSectorCapacityHigh; /* 58 */
6367+ u16 CurrentMultiSectorSetting; /* 59 */
6368+ u32 UserAddressableSectors; /* 60-61 */
6369+ u16 Reserved7; /* 62 */
6370+ u8 MultiWordDMASupport; /* 63 */
6371+ u8 MultiWordDMAActive; /* */
6372+ u16 AdvancedPIOModes; /* 64 */
6373+ u16 MinimumMWXferCycleTime; /* 65 */
6374+ u16 RecommendedMWXferCycleTime; /* 66 */
6375+ u16 MinimumPIOCycleTime; /* 67 */
6376+ u16 MinimumPIOCycleTimeIORDY; /* 68 */
6377+ u16 Reserved8[6]; /* 69-74 */
6378+ u16 QueueDepth; /* 75 */
6379+ u16 Reserved9[4]; /* 76-79 */
6380+ u16 MajorVersionNumber; /* 80 */
6381+ u16 MinorVersionNumber; /* 81 */
6382+ u32 CmdSetSupported; /* 82-83 */
6383+ u16 CmdSetFeatureSupportedExt; /* 84 */
6384+ u16 CmdSetFeatureEnabledLow; /* 85 */
6385+ u16 CmdSetFeatureEnabledHigh; /* 86 */
6386+ u16 CmdSetFeatureDefault; /* 87 */
6387+ u8 UltraDMASupport; /* 88 */
6388+ u8 UltraDMAActive; /* */
6389+ u16 SecurityEraseTime; /* 89 */
6390+ u16 EnhancedSecurityEraseTime; /* 90 */
6391+ u16 PowerManagementValue; /* 91 */
6392+ u16 MasterPasswordRevision; /* 92 */
6393+ u16 HwResetResult; /* 93 */
6394+ u16 Reserved11[6]; /* 94-99 */
6395+ u32 Capacity_48bit_LOW; /* 100-101 */
6396+ u32 Capacity_48bit_HIGH; /* 102-103 */
6397+ u16 Reserved12[24]; /* 104-127 */
6398+ u16 SecurityStatus; /* 128 */
6399+ u16 Reserved13[31]; /* 129-159 vendor spec */
6400+ u16 Reserved14[96]; /* 160-255 */
6401+} IDENTIFY_DATA2, *PIDENTIFY_DATA2;
6402+
6403+#define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
6404+
6405+/************************************************************************
6406+ * IDENTIFY capability bit definitions.
6407+ ************************************************************************/
6408+#define IDENTIFY_CAPABILITIES_DMA_SUPPORTED 0x0100
6409+#define IDENTIFY_CAPABILITIES_LBA_SUPPORTED 0x0200
6410+
6411+/************************************************************************
6412+ * IDENTIFY DMA timing cycle modes.
6413+ ************************************************************************/
6414+#define IDENTIFY_DMA_CYCLES_MODE_0 0x00
6415+#define IDENTIFY_DMA_CYCLES_MODE_1 0x01
6416+#define IDENTIFY_DMA_CYCLES_MODE_2 0x02
6417+
6418+typedef struct _SENSE_DATA
6419+{
6420+ u8 ErrorCode:7;
6421+ u8 Valid:1;
6422+ u8 SegmentNumber;
6423+ u8 SenseKey:4;
6424+ u8 Reserved:1;
6425+ u8 IncorrectLength:1;
6426+ u8 EndOfMedia:1;
6427+ u8 FileMark:1;
6428+ u8 Information[4];
6429+ u8 AdditionalSenseLength;
6430+ u8 CommandSpecificInformation[4];
6431+ u8 AdditionalSenseCode;
6432+ u8 AdditionalSenseCodeQualifier;
6433+ u8 FieldReplaceableUnitCode;
6434+ u8 SenseKeySpecific[3];
6435+} SENSE_DATA, *PSENSE_DATA;
6436+
6437+/************************************************************************
6438+ * Sense codes
6439+ ************************************************************************/
6440+#define SCSI_SENSE_NO_SENSE 0x00
6441+#define SCSI_SENSE_RECOVERED_ERROR 0x01
6442+#define SCSI_SENSE_NOT_READY 0x02
6443+#define SCSI_SENSE_MEDIUM_ERROR 0x03
6444+#define SCSI_SENSE_HARDWARE_ERROR 0x04
6445+#define SCSI_SENSE_ILLEGAL_REQUEST 0x05
6446+#define SCSI_SENSE_UNIT_ATTENTION 0x06
6447+#define SCSI_SENSE_DATA_PROTECT 0x07
6448+#define SCSI_SENSE_BLANK_CHECK 0x08
6449+#define SCSI_SENSE_UNIQUE 0x09
6450+#define SCSI_SENSE_COPY_ABORTED 0x0A
6451+#define SCSI_SENSE_ABORTED_COMMAND 0x0B
6452+#define SCSI_SENSE_EQUAL 0x0C
6453+#define SCSI_SENSE_VOL_OVERFLOW 0x0D
6454+#define SCSI_SENSE_MISCOMPARE 0x0E
6455+#define SCSI_SENSE_RESERVED 0x0F
6456+
6457+/************************************************************************
6458+ * Additional Sense codes
6459+ ************************************************************************/
6460+#define SCSI_ADSENSE_NO_SENSE 0x00
6461+#define SCSI_ADSENSE_MAN_INTERV 0x03
6462+#define SCSI_ADSENSE_LUN_NOT_READY 0x04
6463+#define SCSI_ADSENSE_ILLEGAL_COMMAND 0x20
6464+#define SCSI_ADSENSE_ILLEGAL_BLOCK 0x21
6465+#define SCSI_ADSENSE_INVALID_LUN 0x25
6466+#define SCSI_ADSENSE_SELECT_TIMEOUT 0x45
6467+#define SCSI_ADSENSE_MUSIC_AREA 0xA0
6468+#define SCSI_ADSENSE_DATA_AREA 0xA1
6469+#define SCSI_ADSENSE_VOLUME_OVERFLOW 0xA7
6470+
6471+#define SCSI_ADSENSE_NO_MEDIA_IN_DEVICE 0x3A
6472+#define SCSI_ADWRITE_PROTECT 0x27
6473+#define SCSI_ADSENSE_MEDIUM_CHANGED 0x28
6474+#define SCSI_ADSENSE_BUS_RESET 0x29
6475+#define SCSI_ADSENSE_TRACK_ERROR 0x14
6476+#define SCSI_ADSENSE_SEEK_ERROR 0x15
6477+#define SCSI_ADSENSE_REC_DATA_NOECC 0x17
6478+#define SCSI_ADSENSE_REC_DATA_ECC 0x18
6479+#define SCSI_ADSENSE_ILLEGAL_MODE 0x64
6480+#define SCSI_ADSENSE_BAD_CDB 0x24
6481+#define SCSI_ADSENSE_BAD_PARM_LIST 0x26
6482+#define SCSI_ADSENSE_CANNOT_READ_MEDIUM 0x30
6483+
6484+#define SCSISTAT_CHECK_CONDITION 0x02
6485+
6486+/************************************************************************
6487+ * Inquiry buffer structure. This is the data returned from the target
6488+ * after it receives an inquiry.
6489+ *
6490+ * This structure may be extended by the number of bytes specified
6491+ * in the field AdditionalLength. The defined size constant only
6492+ * includes fields through ProductRevisionLevel.
6493+ *
6494+ * The NT SCSI drivers are only interested in the first 36 bytes of data.
6495+ ************************************************************************/
6496+
6497+#define INQUIRYDATABUFFERSIZE 36
6498+
6499+typedef struct _INQUIRYDATA
6500+{
6501+ u8 DeviceType : 5;
6502+ u8 DeviceTypeQualifier : 3;
6503+ u8 DeviceTypeModifier : 7;
6504+ u8 RemovableMedia : 1;
6505+ u8 Versions;
6506+ u8 ResponseDataFormat;
6507+ u8 AdditionalLength;
6508+ u8 Reserved[2];
6509+ u8 SoftReset : 1;
6510+ u8 CommandQueue : 1;
6511+ u8 Reserved2 : 1;
6512+ u8 LinkedCommands : 1;
6513+ u8 Synchronous : 1;
6514+ u8 Wide16Bit : 1;
6515+ u8 Wide32Bit : 1;
6516+ u8 RelativeAddressing : 1;
6517+ u8 VendorId[8];
6518+ u8 ProductId[16];
6519+ u8 ProductRevisionLevel[4];
6520+ u8 VendorSpecific[20];
6521+ u8 Reserved3[40];
6522+} INQUIRYDATA, *PINQUIRYDATA;
6523+
6524+#define DIRECT_ACCESS_DEVICE 0x00 /* Disks */
6525+
6526+/************************************************************************
6527+ * Read Capacity Data - returned in Big Endian format
6528+ ************************************************************************/
6529+typedef struct _READ_CAPACITY_DATA
6530+{
6531+ u32 LogicalBlockAddress;
6532+ u32 BytesPerBlock;
6533+} READ_CAPACITY_DATA, *PREAD_CAPACITY_DATA;
6534+
6535+#define MAXIMUM_CDB_SIZE 12
6536+
6537+/************************************************************************
6538+ * CDB (Command Descriptor Block)
6539+ ************************************************************************/
6540+typedef union _CDB
6541+{
6542+ /*
6543+ * Standard 6-byte CDB
6544+ */
6545+ struct _CDB6READWRITE
6546+ {
6547+ u8 OperationCode; /* Opcode */
6548+ u8 LogicalBlockMsb1 : 5; /* Logical block MSB 5-bit */
6549+ u8 LogicalUnitNumber : 3; /* LUN */
6550+ u8 LogicalBlockMsb0; /* Logical block MSB 8-bit */
6551+ u8 LogicalBlockLsb; /* Logical block LSB 8-bit */
6552+ u8 TransferBlocks; /* Data length */
6553+ u8 Control; /* Control byte */
6554+ } CDB6READWRITE, *PCDB6READWRITE;
6555+
6556+ /*
6557+ * Standard 10-byte CDB
6558+ */
6559+ struct _CDB10
6560+ {
6561+ u8 OperationCode;
6562+ u8 Reserved1 : 5;
6563+ u8 LogicalUnitNumber : 3;
6564+ u8 LogicalBlockByte0;
6565+ u8 LogicalBlockByte1;
6566+ u8 LogicalBlockByte2;
6567+ u8 LogicalBlockByte3;
6568+ u8 Reserved2;
6569+ u8 TransferBlocksMsb;
6570+ u8 TransferBlocksLsb;
6571+ u8 Control;
6572+ } CDB10, *PCDB10;
6573+
6574+ struct _START_STOP
6575+ {
6576+ u8 OperationCode;
6577+ u8 Immediate: 1;
6578+ u8 Reserved1 : 4;
6579+ u8 LogicalUnitNumber : 3;
6580+ u8 Reserved2[2];
6581+ u8 Start : 1;
6582+ u8 LoadEject : 1;
6583+ u8 Reserved3 : 6;
6584+ u8 Control;
6585+ } START_STOP, *PSTART_STOP;
6586+
6587+} CDB, *PCDB;
6588+
6589+/************************************************************************
6590+ * SCSI CDB operation codes
6591+ ************************************************************************/
6592+#define SCSIOP_TEST_UNIT_READY 0x00
6593+#define SCSIOP_REZERO_UNIT 0x01
6594+#define SCSIOP_REWIND 0x01
6595+#define SCSIOP_REQUEST_BLOCK_ADDR 0x02
6596+#define SCSIOP_REQUEST_SENSE 0x03
6597+#define SCSIOP_FORMAT_UNIT 0x04
6598+#define SCSIOP_READ_BLOCK_LIMITS 0x05
6599+#define SCSIOP_REASSIGN_BLOCKS 0x07
6600+#define SCSIOP_READ6 0x08
6601+#define SCSIOP_RECEIVE 0x08
6602+#define SCSIOP_WRITE6 0x0A
6603+#define SCSIOP_PRINT 0x0A
6604+#define SCSIOP_SEND 0x0A
6605+#define SCSIOP_SEEK6 0x0B
6606+#define SCSIOP_TRACK_SELECT 0x0B
6607+#define SCSIOP_SLEW_PRINT 0x0B
6608+#define SCSIOP_SEEK_BLOCK 0x0C
6609+#define SCSIOP_PARTITION 0x0D
6610+#define SCSIOP_READ_REVERSE 0x0F
6611+#define SCSIOP_WRITE_FILEMARKS 0x10
6612+#define SCSIOP_FLUSH_BUFFER 0x10
6613+#define SCSIOP_SPACE 0x11
6614+#define SCSIOP_INQUIRY 0x12
6615+#define SCSIOP_VERIFY6 0x13
6616+#define SCSIOP_RECOVER_BUF_DATA 0x14
6617+#define SCSIOP_MODE_SELECT 0x15
6618+#define SCSIOP_RESERVE_UNIT 0x16
6619+#define SCSIOP_RELEASE_UNIT 0x17
6620+#define SCSIOP_COPY 0x18
6621+#define SCSIOP_ERASE 0x19
6622+#define SCSIOP_MODE_SENSE 0x1A
6623+#define SCSIOP_START_STOP_UNIT 0x1B
6624+#define SCSIOP_STOP_PRINT 0x1B
6625+#define SCSIOP_LOAD_UNLOAD 0x1B
6626+#define SCSIOP_RECEIVE_DIAGNOSTIC 0x1C
6627+#define SCSIOP_SEND_DIAGNOSTIC 0x1D
6628+#define SCSIOP_MEDIUM_REMOVAL 0x1E
6629+#define SCSIOP_READ_CAPACITY 0x25
6630+#define SCSIOP_READ 0x28
6631+#define SCSIOP_WRITE 0x2A
6632+#define SCSIOP_SEEK 0x2B
6633+#define SCSIOP_LOCATE 0x2B
6634+#define SCSIOP_WRITE_VERIFY 0x2E
6635+#define SCSIOP_VERIFY 0x2F
6636+#define SCSIOP_SEARCH_DATA_HIGH 0x30
6637+#define SCSIOP_SEARCH_DATA_EQUAL 0x31
6638+#define SCSIOP_SEARCH_DATA_LOW 0x32
6639+#define SCSIOP_SET_LIMITS 0x33
6640+#define SCSIOP_READ_POSITION 0x34
6641+#define SCSIOP_SYNCHRONIZE_CACHE 0x35
6642+#define SCSIOP_COMPARE 0x39
6643+#define SCSIOP_COPY_COMPARE 0x3A
6644+#define SCSIOP_WRITE_DATA_BUFF 0x3B
6645+#define SCSIOP_READ_DATA_BUFF 0x3C
6646+#define SCSIOP_CHANGE_DEFINITION 0x40
6647+#define SCSIOP_READ_SUB_CHANNEL 0x42
6648+#define SCSIOP_READ_TOC 0x43
6649+#define SCSIOP_READ_HEADER 0x44
6650+#define SCSIOP_PLAY_AUDIO 0x45
6651+#define SCSIOP_PLAY_AUDIO_MSF 0x47
6652+#define SCSIOP_PLAY_TRACK_INDEX 0x48
6653+#define SCSIOP_PLAY_TRACK_RELATIVE 0x49
6654+#define SCSIOP_PAUSE_RESUME 0x4B
6655+#define SCSIOP_LOG_SELECT 0x4C
6656+#define SCSIOP_LOG_SENSE 0x4D
6657+#define SCSIOP_MODE_SELECT10 0x55
6658+#define SCSIOP_MODE_SENSE10 0x5A
6659+#define SCSIOP_LOAD_UNLOAD_SLOT 0xA6
6660+#define SCSIOP_MECHANISM_STATUS 0xBD
6661+#define SCSIOP_READ_CD 0xBE
6662+
6663+#define DRIVER_NAME "Device Driver for IT8212 RAID Controller"
6664+#define COMPANY_NAME "Integrated Technology Express, Inc."
6665+#define CONTROLLER_NAME_IT8212 "IT8212 UDMA/ATA133 RAID Controller"
6666+#define PROC_DIR_NAME "it8212"
6667+#define ITE_MAX_CMDS 124
6668+
6669+#define PCI_IOSEN 0x01 /* Enable IO space */
6670+#define PCI_BMEN 0x04 /* Enable IDE bus master */
6671+
6672+/************************************************************************
6673+ * PRD (Physical Region Descriptor) = Scatter-gather table
6674+ *
6675+ * | byte3 | byte2 | byte1 | byte0 |
6676+ * +--------------------------------------------+
6677+ * | Memory Region Physical Base Address[31:1] |
6678+ * +----+----------------+----------------------+
6679+ * |EOT | reserved | Byte count[15:1] |
6680+ * +----+----------------+----------------------+
6681+ ************************************************************************/
6682+typedef struct _PRD_TABLE_ENTRY
6683+{
6684+ u32 PhysicalBaseAddress; /* Byte0 - Byte3 */
6685+ u16 ByteCount; /* Byte4 - Byte5 */
6686+ u16 EndOfTable; /* Byte6 - Byte7 */
6687+} PRD_TABLE_ENTRY, *PPRD_TABLE_ENTRY;
6688+
6689+#define SG_FLAG_EOT 0x8000 /* End of PRD */
6690+#define MAX_SG_DESCRIPTORS 17 /* 17 -- maximum 64K */
6691+
6692+#define NUM_OF_PRD_TABLE_ENTRY 0x10
6693+
6694+/************************************************************************
6695+ * Bus master register bits definition
6696+ ************************************************************************/
6697+#define BM_CMD_FLG_START 0x01
6698+#define BM_CMD_FLG_WRTTOMEM 0x08
6699+#define BM_CMD_FLG_WRTTODSK 0x00
6700+
6701+#define BM_STAT_FLG_ACTIVE 0x01
6702+#define BM_STAT_FLG_ERR 0x02
6703+#define BM_STAT_FLG_INT 0x04
6704+#define BM_DRV0_DMA_CAPABLE 0x20
6705+#define BM_DRV1_DMA_CAPABLE 0x40
6706+
6707+#define BM_PRD_FLG_EOT 0x8000
6708+
6709+/************************************************************************
6710+ * SRB Functions
6711+ ************************************************************************/
6712+#define SRB_FUNCTION_EXECUTE_SCSI 0x00
6713+#define SRB_FUNCTION_IO_CONTROL 0x02
6714+#define SRB_FUNCTION_SHUTDOWN 0x07
6715+#define SRB_FUNCTION_FLUSH 0x08
6716+
6717+/************************************************************************
6718+ * SRB Status
6719+ ************************************************************************/
6720+#define SRB_STATUS_PENDING 0x00
6721+#define SRB_STATUS_SUCCESS 0x01
6722+#define SRB_STATUS_ABORTED 0x02
6723+#define SRB_STATUS_ABORT_FAILED 0x03
6724+#define SRB_STATUS_ERROR 0x04
6725+#define SRB_STATUS_BUSY 0x05
6726+#define SRB_STATUS_INVALID_REQUEST 0x06
6727+#define SRB_STATUS_INVALID_PATH_ID 0x07
6728+#define SRB_STATUS_NO_DEVICE 0x08
6729+#define SRB_STATUS_TIMEOUT 0x09
6730+#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
6731+#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
6732+#define SRB_STATUS_MESSAGE_REJECTED 0x0D
6733+#define SRB_STATUS_BUS_RESET 0x0E
6734+#define SRB_STATUS_PARITY_ERROR 0x0F
6735+#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
6736+#define SRB_STATUS_NO_HBA 0x11
6737+#define SRB_STATUS_DATA_OVERRUN 0x12
6738+#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
6739+#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
6740+#define SRB_STATUS_REQUEST_FLUSHED 0x16
6741+#define SRB_STATUS_INVALID_LUN 0x20
6742+#define SRB_STATUS_INVALID_TARGET_ID 0x21
6743+#define SRB_STATUS_BAD_FUNCTION 0x22
6744+#define SRB_STATUS_ERROR_RECOVERY 0x23
6745+#define SRB_STATUS_NEED_REQUEUE 0x24
6746+
6747+/************************************************************************
6748+ * SRB Status Masks
6749+ ************************************************************************/
6750+#define SRB_STATUS_QUEUE_FROZEN 0x40
6751+#define SRB_STATUS_AUTOSENSE_VALID 0x80
6752+
6753+#define SRB_STATUS(Status) \
6754+ (Status & ~(SRB_STATUS_AUTOSENSE_VALID | SRB_STATUS_QUEUE_FROZEN))
6755+
6756+/************************************************************************
6757+ * SRB Flag Bits
6758+ ************************************************************************/
6759+#define SRB_FLAGS_DATA_IN 0x00000040
6760+#define SRB_FLAGS_DATA_OUT 0x00000080
6761+
6762+/************************************************************************
6763+ * SRB Working flags define area
6764+ ************************************************************************/
6765+#define SRB_WFLAGS_USE_INTERNAL_BUFFER 0x00000001
6766+#define SRB_WFLAGS_IGNORE_ARRAY 0x00000002
6767+#define SRB_WFLAGS_HAS_CALL_BACK 0x00000004
6768+#define SRB_WFLAGS_MUST_DONE 0x00000008
6769+#define SRB_WFLAGS_ON_MIRROR_DISK 0x00000010
6770+#define SRB_WFLAGS_ON_SOURCE_DISK 0x00000020
6771+#define SRB_WFLAGS_ARRAY_IO_STARTED 0x10000000
6772+#define SRB_WFLAGS_WATCHTIMER_CALLED 0x20000000
6773+#define SRB_WFLAGS_USE_SG 0x40000000
6774+
6775+/************************************************************************
6776+ * SCSI I/O Request Block
6777+ ************************************************************************/
6778+typedef struct _SCSI_REQUEST_BLOCK
6779+{
6780+ u16 Length;
6781+ u8 Function;
6782+ u8 SrbStatus;
6783+ u8 ScsiStatus;
6784+ u8 TargetId;
6785+ u8 Lun;
6786+ u8 CdbLength;
6787+ u8 SenseInfoBufferLength;
6788+ u8 UseSg;
6789+ u8 reseved[2];
6790+ u32 WorkingFlags;
6791+ u32 SrbFlags;
6792+ u32 DataTransferLength;
6793+ u32 TimeOutValue;
6794+ void * DataBuffer;
6795+ void * SenseInfoBuffer;
6796+ u8 Cdb[16];
6797+ Scsi_Cmnd * pREQ;
6798+} SCSI_REQUEST_BLOCK, *PSCSI_REQUEST_BLOCK;
6799+
6800+#define SCSI_REQUEST_BLOCK_SIZE sizeof(SCSI_REQUEST_BLOCK)
6801+
6802+/************************************************************************
6803+ * Second device flags
6804+ ***********************************************************************/
6805+#define DFLAGS_REDUCE_MODE 0x00010000
6806+#define DFLAGS_DEVICE_DISABLED 0x00020000
6807+#define DFLAGS_BOOTABLE_DEVICE 0x00080000
6808+#define DFLAGS_BOOT_MARK 0x00100000
6809+#define DFLAGS_NEW_ADDED 0x40000000
6810+#define DFLAGS_REMAINED_MEMBER 0x80000000
6811+
6812+/************************************************************************
6813+ * Device Extension Device Flags
6814+ ************************************************************************/
6815+/*
6816+ * Indicates that some device is present.
6817+ */
6818+#define DFLAGS_DEVICE_PRESENT 0x0001
6819+
6820+/*
6821+ * Indicates whether ATAPI commands can be used.
6822+ */
6823+#define DFLAGS_ATAPI_DEVICE 0x0002
6824+
6825+/*
6826+ * Indicates whether this is a tape device.
6827+ */
6828+#define DFLAGS_TAPE_DEVICE 0x0004
6829+
6830+/*
6831+ * Indicates whether device interrupts as DRQ is set after
6832+ * receiving Atapi Packet Command.
6833+ */
6834+#define DFLAGS_INT_DRQ 0x0008
6835+
6836+/*
6837+ * Indicates that the drive has the 'removable' bit set in
6838+ * identify data (offset 128)
6839+ */
6840+#define DFLAGS_REMOVABLE_DRIVE 0x0010
6841+
6842+/*
6843+ * Media status notification enabled.
6844+ */
6845+#define DFLAGS_MEDIA_STATUS_ENABLED 0x0020
6846+
6847+/*
6848+ * Indicates atapi 2.5 changer present.
6849+ */
6850+#define DFLAGS_ATAPI_CHANGER 0x0040
6851+
6852+/*
6853+ * Indicates multi-platter device, not conforming to the 2.5 spec.
6854+ */
6855+#define DFLAGS_SANYO_ATAPI_CHANGER 0x0080
6856+
6857+/*
6858+ * Indicates that the init path for changers has already been done.
6859+ */
6860+#define DFLAGS_CHANGER_INITED 0x0100
6861+#define DFLAGS_CONFIG_CHANGED 0x0200
6862+
6863+#define UDMA_MODE_5_6 0x80
6864+
6865+/************************************************************************
6866+ * Used to disable 'advanced' features.
6867+ ************************************************************************/
6868+#define MAX_ERRORS 4
6869+
6870+/************************************************************************
6871+ * ATAPI command definitions
6872+ ************************************************************************/
6873+#define ATAPI_MODE_SENSE 0x5A
6874+#define ATAPI_MODE_SELECT 0x55
6875+#define ATAPI_FORMAT_UNIT 0x24
6876+
6877+/************************************************************************
6878+ * User IOCTL structure
6879+ * Notes:
6880+ * (1) Data transfers are limited to PAGE_SIZE (4k on i386, 8k for alpha)
6881+ ************************************************************************/
6882+typedef struct _uioctl_t
6883+{
6884+ u16 inlen; /* Length of data written to device */
6885+ u16 outlen; /* Length of data read from device */
6886+ void * data; /* Data read from devic starts here */
6887+ u8 status; /* Status return from driver */
6888+ u8 reserved[3]; /* For 4-byte alignment */
6889+} uioctl_t;
6890+
6891+/************************************************************************
6892+ * IOCTL commands for RAID
6893+ ************************************************************************/
6894+#define ITE_IOCMAGIC 't'
6895+
6896+#define ITE_IOC_GET_PHY_DISK_STATUS _IO(ITE_IOCMAGIC, 1)
6897+#define ITE_IOC_CREATE_DISK_ARRAY _IO(ITE_IOCMAGIC, 2)
6898+#define ITE_IOC_REBUILD_START _IO(ITE_IOCMAGIC, 3)
6899+#define ITE_IOC_GET_REBUILD_STATUS _IO(ITE_IOCMAGIC, 4)
6900+#define ITE_IOC_RESET_ADAPTER _IO(ITE_IOCMAGIC, 5)
6901+#define ITE_IOC_GET_DRIVER_VERSION _IO(ITE_IOCMAGIC, 6)
6902+
6903+/************************************************************************
6904+ * _Channel
6905+ ************************************************************************/
6906+typedef struct _Channel
6907+{
6908+ /*
6909+ * IDE (ATAPI) io port address.
6910+ */
6911+ unsigned long io_ports[IDE_NR_PORTS];
6912+
6913+ /*
6914+ * DMA base address.
6915+ */
6916+ unsigned long dma_base;
6917+
6918+ /*
6919+ * Flags word for each possible device.
6920+ */
6921+ u16 DeviceFlags[2];
6922+
6923+ /*
6924+ * Indicates number of platters on changer-ish devices.
6925+ */
6926+ u32 DiscsPresent[2];
6927+
6928+ /*
6929+ * Indicates expecting an interrupt.
6930+ */
6931+ u8 ExpectingInterrupt;
6932+
6933+ /*
6934+ * Indicate last tape command was DSC Restrictive.
6935+ */
6936+ u8 RDP;
6937+
6938+ /*
6939+ * Interrupt level.
6940+ */
6941+ u8 InterruptLevel;
6942+
6943+ /*
6944+ * Placeholder for status register after a GET_MEDIA_STATUS command.
6945+ */
6946+ u8 ReturningMediaStatus;
6947+
6948+ /*
6949+ * Remember the channel number (0, 1)
6950+ */
6951+ u8 channel;
6952+
6953+ /*
6954+ * Indicates cable status.
6955+ */
6956+ u8 Cable80[2];
6957+
6958+ /*
6959+ * Reserved for alignment.
6960+ */
6961+ u8 reserved1[0];
6962+
6963+ /*
6964+ * Data buffer pointer.
6965+ */
6966+ unsigned short * DataBuffer;
6967+
6968+ /*
6969+ * Data words left.
6970+ */
6971+ u32 WordsLeft;
6972+
6973+ /*
6974+ * Retry count.
6975+ */
6976+ u32 RetryCount;
6977+
6978+ /*
6979+ * Keep DMA type (MULTIWORD_DMA or ULTRA_DMA) for each device.
6980+ */
6981+ u8 DmaType[2];
6982+
6983+ /*
6984+ * Keep UDMA timing for each device.
6985+ */
6986+ u8 UdmaTiming[2];
6987+
6988+ /*
6989+ * Keep PIO/DMA timing for each channel. PioDmaTiming[clock][channel]
6990+ */
6991+ u8 PioDmaTiming[2];
6992+
6993+ /*
6994+ * Keep IDE clock (50 MHz or 66 MHz) for each device.
6995+ */
6996+ u8 IdeClock[2];
6997+
6998+ /*
6999+ * Keep the active device for each channel.
7000+ */
7001+ u8 ActiveDevice;
7002+
7003+ /*
7004+ * Indicate whether we should perform DMA mode switch on this channel?
7005+ */
7006+ u8 DoSwitch;
7007+
7008+ /*
7009+ * ???
7010+ */
7011+ u8 ConvertCdb;
7012+
7013+ /*
7014+ * Use or do not use DMA.
7015+ */
7016+ u8 UseDma[2];
7017+
7018+ /*
7019+ * Reserved for alignment.
7020+ */
7021+ u8 reserved2[3];
7022+
7023+ /*
7024+ * Identify data for device.
7025+ */
7026+ IDENTIFY_DATA FullIdentifyData;
7027+ IDENTIFY_DATA2 IdentifyData[2];
7028+
7029+ /*
7030+ * DMA PRD table physical address.
7031+ */
7032+ dma_addr_t dmatable_dma;
7033+
7034+ /*
7035+ * DMA PRD table virtual address.
7036+ */
7037+ unsigned long * dmatable_cpu;
7038+
7039+ /*
7040+ * Point to SCATTER/GATHER data buffer.
7041+ */
7042+ struct scatterlist * sg_table;
7043+
7044+ /*
7045+ * DMA read or write.
7046+ */
7047+ int sg_dma_direction;
7048+
7049+ /*
7050+ * Current request on controller.
7051+ */
7052+ PSCSI_REQUEST_BLOCK CurrentSrb;
7053+
7054+ /*
7055+ * Original request on controller.
7056+ */
7057+ PSCSI_REQUEST_BLOCK OriginalSrb;
7058+
7059+ /*
7060+ * Internal SRB.
7061+ */
7062+ SCSI_REQUEST_BLOCK _Srb;
7063+
7064+ /*
7065+ * Remember the PCI device.
7066+ */
7067+ struct pci_dev * pPciDev;
7068+
7069+ /*
7070+ * Placeholder for CDB.
7071+ */
7072+ u8 TempCdb[MAXIMUM_CDB_SIZE];
7073+} Channel, *PChannel;
7074+
7075+/************************************************************************
7076+ * _Adapter
7077+ ************************************************************************/
7078+typedef struct _Adapter
7079+{
7080+ char * name; /* Adapter's name */
7081+ u8 num_channels; /* How many channels support */
7082+ u8 irq; /* irq number */
7083+ u8 irqOwned; /* If any irq is use */
7084+ u8 pci_bus; /* PCI bus number */
7085+ u8 devfn; /* Device and function number */
7086+ u8 offline; /* On line or off line */
7087+ u8 bypass_mode; /* bypass or firware mode */
7088+ u8 reserved2[1]; /* Reserved for alignment */
7089+ Channel * IDEChannel; /* IT8212 supports two channels */
7090+ struct pci_dev * pci_dev; /* For PCI device */
7091+}
7092+ITE_ADAPTER, *PITE_ADAPTER;
7093+
7094+/************************************************************************
7095+ * Beautification macros
7096+ ************************************************************************/
7097+#define ScheduleRetryProcess(pChan) do { \
7098+ pChan->retry_timer->expires = jiffies + 10; \
7099+ add_timer(pChan->retry_timer); \
7100+ } while (0)
7101+
7102+#define CancelRetryProcess(pChan) del_timer(pChan->retry_timer)
7103+
7104+#define GetStatus(pChan, Status) \
7105+ Status = inb(pChan->io_ports[IDE_CONTROL_OFFSET]);
7106+
7107+#define GetBaseStatus(pChan, Status) \
7108+ Status = inb(pChan->io_ports[IDE_COMMAND_OFFSET]);
7109+
7110+#define GetError(pChan, Error) \
7111+ Error = inb(pChan->io_ports[IDE_ERROR_OFFSET]);
7112+
7113+#define ReadBuffer(pChan, Buffer, Count) \
7114+ insw(pChan->io_ports[IDE_DATA_OFFSET], Buffer, Count);
7115+
7116+#define WriteCommand(BaseIoAddress, Command) \
7117+ outb(pChan->io_ports[IDE_COMMAND_OFFSET], Command);
7118+
7119+#define WriteBuffer(pChan, Buffer, Count) \
7120+ outsw(pChan->io_ports[IDE_DATA_OFFSET], Buffer, Count);
7121+
7122+#define WaitOnBusy(pChan, Status) \
7123+{ \
7124+ int i; \
7125+ for (i = 0; i < 20000; i++) \
7126+ { \
7127+ GetStatus(pChan, Status); \
7128+ if (Status & IDE_STATUS_BUSY) \
7129+ { \
7130+ udelay(150); \
7131+ continue; \
7132+ } \
7133+ else \
7134+ { \
7135+ break; \
7136+ } \
7137+ } \
7138+}
7139+
7140+#define WaitOnBaseBusy(pChan, Status) \
7141+{ \
7142+ int i; \
7143+ for (i = 0; i < 20000; i++) \
7144+ { \
7145+ GetBaseStatus(pChan, Status); \
7146+ if (Status & IDE_STATUS_BUSY) \
7147+ { \
7148+ udelay(150); \
7149+ continue; \
7150+ } \
7151+ else \
7152+ { \
7153+ break; \
7154+ } \
7155+ } \
7156+}
7157+
7158+#define WaitForDrq(pChan, Status) \
7159+{ \
7160+ int i; \
7161+ for (i = 0; i < 1000; i++) \
7162+ { \
7163+ GetStatus(pChan, Status); \
7164+ if (Status & IDE_STATUS_BUSY) \
7165+ { \
7166+ udelay(100); \
7167+ } \
7168+ else if (Status & IDE_STATUS_DRQ) \
7169+ { \
7170+ break; \
7171+ } \
7172+ else \
7173+ { \
7174+ udelay(200); \
7175+ } \
7176+ } \
7177+}
7178+
7179+#define WaitForBaseDrq(pChan, Status) \
7180+{ \
7181+ int i; \
7182+ for (i = 0; i < 50000; i++) \
7183+ { \
7184+ GetBaseStatus(pChan, Status); \
7185+ if (Status & IDE_STATUS_BUSY) \
7186+ { \
7187+ udelay(100); \
7188+ } \
7189+ else if (Status & IDE_STATUS_DRQ) \
7190+ { \
7191+ break; \
7192+ } \
7193+ else \
7194+ { \
7195+ udelay(200); \
7196+ } \
7197+ } \
7198+}
7199+
7200+#define CheckBusyDrq(pChan, Status) \
7201+{ \
7202+ int i; \
7203+ for (i = 0; i < 50000; i++) \
7204+ { \
7205+ GetBaseStatus(pChan, Status); \
7206+ if ((Status & IDE_STATUS_BUSY) || \
7207+ !(Status & IDE_STATUS_DRQ)) \
7208+ { \
7209+ udelay(200); \
7210+ } \
7211+ else \
7212+ { \
7213+ break; \
7214+ } \
7215+ } \
7216+}
7217+
7218+#define WaitShortForDrq(pChan, Status) \
7219+{ \
7220+ int i; \
7221+ for (i = 0; i < 2; i++) \
7222+ { \
7223+ GetStatus(pChan, Status); \
7224+ if (Status & IDE_STATUS_BUSY) \
7225+ { \
7226+ udelay(100); \
7227+ } \
7228+ else if (Status & IDE_STATUS_DRQ) \
7229+ { \
7230+ break; \
7231+ } \
7232+ else \
7233+ { \
7234+ udelay(100); \
7235+ } \
7236+ } \
7237+}
7238+
7239+#define WaitForDeviceReady(pChan, Status) \
7240+{ \
7241+ int i; \
7242+ for (i = 0; i < 50000; i++) \
7243+ { \
7244+ GetStatus(pChan, Status); \
7245+ if (Status == 0) \
7246+ { \
7247+ break; \
7248+ } \
7249+ if ((Status & IDE_STATUS_BUSY) || (Status & IDE_STATUS_DRQ)) \
7250+ { \
7251+ udelay(200); \
7252+ continue; \
7253+ } \
7254+ else \
7255+ { \
7256+ break; \
7257+ } \
7258+ } \
7259+}
7260+
7261+#define WaitForCommandComplete(pChan, Status) \
7262+{ \
7263+ int i; \
7264+ for (i = 0; i < 50000; i++) \
7265+ { \
7266+ GetStatus(pChan, Status); \
7267+ if ((Status == 0) || (Status & IDE_STATUS_ERROR) \
7268+ || (Status == IDE_STATUS_IDLE)) \
7269+ { \
7270+ break; \
7271+ } \
7272+ udelay(200); \
7273+ continue; \
7274+ } \
7275+}
7276+
7277+#define WaitForBaseCommandComplete(pChan, Status) \
7278+{ \
7279+ int i; \
7280+ for (i = 0; i < 50000; i++) \
7281+ { \
7282+ GetBaseStatus(pChan, Status); \
7283+ if ((Status == 0) || (Status & IDE_STATUS_ERROR) \
7284+ || (Status == IDE_STATUS_IDLE)) \
7285+ { \
7286+ break; \
7287+ } \
7288+ udelay(200); \
7289+ continue; \
7290+ } \
7291+}
7292+
7293+#define AtapiSoftReset(pChan, DevNum) \
7294+{ \
7295+ unsigned char statusByte; \
7296+ outb((unsigned char)(((DevNum & 0x1) << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]); \
7297+ udelay(500); \
7298+ outb(IDE_COMMAND_ATAPI_RESET, pChan->io_ports[IDE_COMMAND_OFFSET]); \
7299+ mdelay(1000); \
7300+ outb((unsigned char)(((DevNum & 0x1) << 4) | 0xA0), pChan->io_ports[IDE_SELECT_OFFSET]); \
7301+ WaitOnBusy(pChan, statusByte); \
7302+ udelay(500); \
7303+}
7304+
7305+#define IdeHardReset(pChan, result) \
7306+{ \
7307+ unsigned char statusByte; \
7308+ int i; \
7309+ outb(IDE_DC_RESET_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]); \
7310+ mdelay(50); \
7311+ outb(IDE_DC_REENABLE_CONTROLLER, pChan->io_ports[IDE_CONTROL_OFFSET]); \
7312+ for (i = 0; i < 1000 * 1000; i++) \
7313+ { \
7314+ statusByte = inb(pChan->io_ports[IDE_CONTROL_OFFSET]); \
7315+ if (statusByte != IDE_STATUS_IDLE && statusByte != 0x0) \
7316+ { \
7317+ udelay(30); \
7318+ } \
7319+ else \
7320+ { \
7321+ break; \
7322+ } \
7323+ } \
7324+ if (i == 1000 * 1000) \
7325+ { \
7326+ printk("IdeHardReset Fail!\n"); \
7327+ result = FALSE; \
7328+ } \
7329+ else \
7330+ { \
7331+ dprintk("IdeHardReset Success!\n"); \
7332+ result = TRUE; \
7333+ } \
7334+}
7335+
7336+/************************************************************************
7337+ * Function prototypes
7338+ ************************************************************************/
7339+const char * iteraid_info (struct Scsi_Host *);
7340+int iteraid_detect (Scsi_Host_Template *);
7341+int iteraid_release (struct Scsi_Host *);
7342+int iteraid_command (Scsi_Cmnd *);
7343+int iteraid_queuecommand (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
7344+int iteraid_biosparam (struct scsi_device *, struct block_device *, sector_t , int *);
7345+int iteraid_proc_info (struct Scsi_Host *, char *buffer, char **start, off_t offset,
7346+ int length, int inout);
7347+
7348+static void TaskStart(PChannel, Scsi_Cmnd *);
7349+static void TaskQueue(void);
7350+static void TaskDone(PChannel, PSCSI_REQUEST_BLOCK);
7351+static u32 IdeSendCommand(PChannel, PSCSI_REQUEST_BLOCK);
7352+static void IdeMediaStatus(u8, PChannel, u8);
7353+static void IdeSetupDma(PChannel, unsigned long, unsigned short);
7354+static void MapRequest(Scsi_Cmnd *, PSCSI_REQUEST_BLOCK);
7355+static u8 IssueIdentify(PChannel, u8, u8);
7356+static u8 IT8212ResetAdapter(PITE_ADAPTER);
7357+static void AtapiStartIo(PChannel, PSCSI_REQUEST_BLOCK);
7358+static u8 AtapiInterrupt(PChannel);
7359+static void AtapiResetController(PITE_ADAPTER pAdap, PChannel pChan);
7360+
7361+static int itedev_open(struct inode *, struct file *);
7362+static int itedev_ioctl_entry(struct inode *, struct file *, unsigned int, unsigned long);
7363+static int itedev_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
7364+static int itedev_close(struct inode *, struct file *);
7365+
7366+#endif /* #ifndef _ITERAID_H_ */
7367diff -Nur --exclude '*.orig' linux-2.6.8.1.org/drivers/scsi/Kconfig linux-2.6.8.1/drivers/scsi/Kconfig
7368--- linux-2.6.8.1.org/drivers/scsi/Kconfig 2004-10-22 13:05:11.701669856 +0200
7369+++ linux-2.6.8.1/drivers/scsi/Kconfig 2004-10-22 13:16:18.963230680 +0200
7370@@ -239,6 +239,12 @@
7371 Please read the comments at the top of
7372 <file:drivers/scsi/3w-xxxx.c>.
7373
7374+config BLK_DEV_IT82XX_RAID
7375+ tristate "ITE IT8212F/8211F RAID support"
7376+ depends on PCI && SCSI
7377+ help
7378+
7379+
7380 config SCSI_3W_9XXX
7381 tristate "3ware 9xxx SATA-RAID support"
7382 depends on PCI && SCSI
7383diff -Nur --exclude '*.orig' linux-2.6.8.1.org/drivers/scsi/Makefile linux-2.6.8.1/drivers/scsi/Makefile
7384--- linux-2.6.8.1.org/drivers/scsi/Makefile 2004-08-14 12:55:59.000000000 +0200
7385+++ linux-2.6.8.1/drivers/scsi/Makefile 2004-10-22 13:17:11.259280472 +0200
7386@@ -108,6 +108,7 @@
7387 obj-$(CONFIG_SCSI_PLUTO) += pluto.o
7388 obj-$(CONFIG_SCSI_DECNCR) += NCR53C9x.o dec_esp.o
7389 obj-$(CONFIG_BLK_DEV_3W_XXXX_RAID) += 3w-xxxx.o
7390+obj-$(CONFIG_BLK_DEV_IT82XX_RAID) += iteraid.o
7391 obj-$(CONFIG_SCSI_3W_9XXX) += 3w-9xxx.o
7392 obj-$(CONFIG_SCSI_PPA) += ppa.o
7393 obj-$(CONFIG_SCSI_IMM) += imm.o
The Linux kernel (the core of the Linux operating system)
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