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Commit | Line | Data |
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19e434b9 TP |
1 | --- SVGATextMode-1.10/XFREE/riva128_clock.c.orig Tue Mar 18 12:07:39 2003 |
2 | +++ SVGATextMode-1.10/XFREE/riva128_clock.c Tue Mar 18 12:24:24 2003 | |
3 | @@ -83,6 +83,33 @@ | |
b1c07dca TP |
4 | #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C |
5 | #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D | |
6 | #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 | |
82beb398 TP |
7 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 |
8 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 | |
9 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 0x0110 | |
10 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 0x0111 | |
11 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 | |
12 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 | |
13 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 | |
19e434b9 TP |
14 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 |
15 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 0x0201 | |
16 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 0x0202 | |
17 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX460 0x0170 | |
18 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440 0x0171 | |
19 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420 0x0172 | |
20 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE 0x0173 | |
21 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440GO 0x0174 | |
22 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420GO 0x0175 | |
23 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420GO32 0x0176 | |
24 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO 0x0177 | |
25 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO64 0x0179 | |
26 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410GO16 0x017D | |
27 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x 0x0181 | |
28 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x 0x0182 | |
29 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x 0x0183 | |
30 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 0x0280 | |
31 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x 0x0281 | |
32 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE 0x0282 | |
33 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO 0x0286 | |
b1c07dca TP |
34 | |
35 | vgaPCIInformation *vgaPCIInfo; | |
36 | ||
19e434b9 | 37 | @@ -92,14 +119,15 @@ |
82beb398 TP |
38 | #define PRAMDAC_PLL_COEFF 0x00000508 |
39 | #define PRAMDAC_PLL_COEFF_SELECT 0x0000050C | |
40 | ||
41 | +#define PEXTDEV_BASE 0x00101000 | |
42 | + | |
43 | #define NV3_MIN_CLOCK_IN_KHZ 25000 // Not sure about this, but it seems reasonable | |
44 | #define NV3_MAX_CLOCK_IN_KHZ 230000 | |
45 | #define NV4_MAX_CLOCK_IN_KHZ 350000 | |
46 | ||
47 | static int max_clock, is_nv3, pll_coeff; | |
48 | ||
49 | -/* NTSC cards have approx 14.3Mhz. Need to detect, but leave for now*/ | |
50 | -#define PLL_INPUT_FREQ 13500 | |
51 | +static int PLL_INPUT_FREQ; | |
52 | #define M_MIN 7 | |
53 | #define M_MAX 13 | |
54 | ||
19e434b9 | 55 | @@ -176,7 +204,7 @@ |
82beb398 TP |
56 | // Set the clock to the given speed (in KHz) |
57 | Bool RIVA128ClockSelect( int clockspeed ) | |
58 | { | |
59 | - int *ptr; | |
60 | + int *ptr, *ptr2; | |
61 | ||
62 | int out; | |
63 | int m, n, p, value; | |
19e434b9 | 64 | @@ -205,7 +233,34 @@ |
b1c07dca TP |
65 | pcr->_device == PCI_DEVICE_ID_NVIDIA_UTNT2 || |
66 | pcr->_device == PCI_DEVICE_ID_NVIDIA_VTNT2 || | |
67 | pcr->_device == PCI_DEVICE_ID_NVIDIA_UVTNT2 || | |
68 | - pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2) | |
69 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2 || | |
82beb398 TP |
70 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR || |
71 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR || | |
72 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 || | |
73 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 || | |
74 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS || | |
75 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 || | |
19e434b9 TP |
76 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA || |
77 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3 || | |
78 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 || | |
79 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 || | |
80 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX460 || | |
81 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440 || | |
82 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420 || | |
83 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE || | |
84 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_440GO || | |
85 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420GO || | |
86 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420GO32 || | |
87 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO || | |
88 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO64 || | |
89 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_410GO16 || | |
90 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x || | |
91 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x || | |
92 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x || | |
93 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 || | |
94 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x || | |
95 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE || | |
96 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO) | |
b1c07dca TP |
97 | { |
98 | is_nv3 = 0; | |
99 | pll_coeff = 0x00010700; | |
19e434b9 | 100 | @@ -249,6 +304,24 @@ |
82beb398 TP |
101 | return FALSE; |
102 | } | |
19e434b9 | 103 | |
82beb398 TP |
104 | + ptr2 = (int*)mmap(0, 0x1000,PROT_READ|PROT_WRITE,MAP_SHARED, fd, (off_t)(pcr->_base0) + PEXTDEV_BASE); |
105 | + | |
106 | + if( ptr2 == (int*)-1 ) | |
107 | + { | |
108 | + PERROR(( "Error mmap'ing /dev/mem" )); | |
109 | + return FALSE; | |
110 | + } | |
111 | + | |
112 | + if(is_nv3) | |
113 | + { | |
114 | + PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x20) ? 13500 : 14318; | |
115 | + } | |
116 | + else | |
117 | + { | |
118 | + PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x40) ? 14318 : 13500; | |
119 | + } | |
120 | + munmap(ptr2, 0x1000); | |
19e434b9 | 121 | + |
82beb398 TP |
122 | close( fd ); |
123 | #else | |
19e434b9 | 124 | ptr=(int*) malloc(0x4000); |