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[packages/kernel.git] / 2.6.x-TGA-fbdev-lkml.patch
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e1b172c5 1diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/Kconfig fbdev-2.6/drivers/video/logo/Kconfig
2--- linus-2.6/drivers/video/logo/Kconfig 2004-02-18 20:59:12.000000000 -0800
3+++ fbdev-2.6/drivers/video/logo/Kconfig 2004-02-18 20:10:03.000000000 -0800
4@@ -25,7 +25,7 @@
5
6 config LOGO_DEC_CLUT224
7 bool "224-color Digital Equipment Corporation Linux logo"
8- depends on LOGO && DECSTATION
9+ depends on LOGO && (DECSTATION || ALPHA)
10 default y
11
12 config LOGO_MAC_CLUT224
13diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/logo.c fbdev-2.6/drivers/video/logo/logo.c
14--- linus-2.6/drivers/video/logo/logo.c 2004-02-18 20:59:12.000000000 -0800
15+++ fbdev-2.6/drivers/video/logo/logo.c 2004-02-18 20:10:04.000000000 -0800
16@@ -65,9 +65,14 @@
17 logo = &logo_linux_clut224;
18 #endif
19 #ifdef CONFIG_LOGO_DEC_CLUT224
20+# if defined(CONFIG_MIPS) || defined(CONFIG_MIPS64)
21 /* DEC Linux logo on MIPS/MIPS64 */
22 if (mips_machgroup == MACH_GROUP_DEC)
23 logo = &logo_dec_clut224;
24+# else
25+ /* Assume DEC Linux logo on ALPHA */
26+ logo = &logo_dec_clut224;
27+# endif
28 #endif
29 #ifdef CONFIG_LOGO_MAC_CLUT224
30 /* Macintosh Linux logo on m68k */
31diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/tgafb.c fbdev-2.6/drivers/video/tgafb.c
32--- linus-2.6/drivers/video/tgafb.c 2004-02-18 20:59:10.000000000 -0800
33+++ fbdev-2.6/drivers/video/tgafb.c 2004-02-18 20:53:34.000000000 -0800
34@@ -24,7 +24,7 @@
35 #include <linux/fb.h>
36 #include <linux/pci.h>
37 #include <asm/io.h>
38-#include <video/tgafb.h>
39+#include <video/tga.h>
c9d1c54c 40 #include <linux/selection.h>
e1b172c5 41
42 /*
e1b172c5 43@@ -41,6 +41,7 @@
44 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
45 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
46 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
47+static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
48
49 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
50 #ifdef MODULE
51@@ -49,7 +50,6 @@
52
53 static const char *mode_option = "640x480@60";
54
55-
56 /*
57 * Frame buffer operations
58 */
59@@ -60,6 +60,7 @@
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63+ .fb_pan_display = tgafb_pan_display,
64 .fb_fillrect = tgafb_fillrect,
65 .fb_copyarea = tgafb_copyarea,
66 .fb_imageblit = tgafb_imageblit,
67@@ -127,10 +128,10 @@
68 tgafb_set_par(struct fb_info *info)
69 {
70 static unsigned int const deep_presets[4] = {
71- 0x00014000,
72- 0x0001440d,
73+ 0x00004000,
74+ 0x0000440d,
75 0xffffffff,
76- 0x0001441d
77+ 0x0000441d
78 };
79 static unsigned int const rasterop_presets[4] = {
80 0x00000003,
81@@ -154,7 +155,7 @@
82 struct tga_par *par = (struct tga_par *) info->par;
83 u32 htimings, vtimings, pll_freq;
84 u8 tga_type;
85- int i, j;
86+ int i;
87
88 /* Encode video timings. */
89 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
90@@ -192,7 +193,8 @@
91 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
92 continue;
93 mb();
94- TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
95+ TGA_WRITE_REG(par, deep_presets[tga_type] |
96+ (par->sync_on_green ? 0x0 : 0x00010000), TGA_DEEP_REG);
97 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
98 continue;
99 mb();
100@@ -225,37 +227,13 @@
101 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
102 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
103
104- /* Fill palette registers. */
105- BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
106- TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
107-
108- for (i = 0; i < 16; i++) {
109- j = color_table[i];
110- TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
111- TGA_RAMDAC_REG);
112- TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
113- TGA_RAMDAC_REG);
114- TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
115- TGA_RAMDAC_REG);
116- }
117- for (i = 0; i < 240*3; i += 4) {
118- TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
119- TGA_RAMDAC_REG);
120- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
121- TGA_RAMDAC_REG);
122- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
123- TGA_RAMDAC_REG);
124- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
125- TGA_RAMDAC_REG);
126- }
127-
128 } else { /* 24-plane or 24plusZ */
129
130 /* Init BT463 registers. */
131 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
132 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
133 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
134- (par->sync_on_green ? 0x80 : 0x40));
135+ (par->sync_on_green ? 0xc0 : 0x40));
136
137 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
138 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
139@@ -267,30 +245,6 @@
140 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
141 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
142
143- /* Fill the palette. */
144- BT463_LOAD_ADDR(par, 0x0000);
145- TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
146-
147- for (i = 0; i < 16; i++) {
148- j = color_table[i];
149- TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
150- TGA_RAMDAC_REG);
151- TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
152- TGA_RAMDAC_REG);
153- TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
154- TGA_RAMDAC_REG);
155- }
156- for (i = 0; i < 512*3; i += 4) {
157- TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
158- TGA_RAMDAC_REG);
159- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
160- TGA_RAMDAC_REG);
161- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
162- TGA_RAMDAC_REG);
163- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
164- TGA_RAMDAC_REG);
165- }
166-
167 /* Fill window type table after start of vertical retrace. */
168 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
169 continue;
170@@ -314,6 +268,9 @@
171
172 }
173
174+ /* Init the palette. */
175+ fb_set_cmap(fb_default_cmap(16), 1, info);
176+
177 /* Finally, enable video scan (and pray for the monitor... :-) */
178 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
179
180@@ -509,16 +466,8 @@
181 * Acceleration.
182 */
183
184-/**
185- * tgafb_imageblit - REQUIRED function. Can use generic routines if
186- * non acclerated hardware and packed pixel based.
187- * Copies a image from system memory to the screen.
188- *
189- * @info: frame buffer structure that represents a single frame buffer
190- * @image: structure defining the image.
191- */
192 static void
193-tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
194+tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
195 {
196 static unsigned char const bitrev[256] = {
197 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
198@@ -562,6 +511,17 @@
199 const unsigned char *data;
200 void *regs_base, *fb_base;
201
202+ is8bpp = info->var.bits_per_pixel == 8;
203+
204+ /* For copies that aren't pixel expansion, there's little we
205+ can do better than the generic code. */
206+ /* ??? There is a DMA write mode; I wonder if that could be
207+ made to pull the data from the image buffer... */
208+ if (image->depth > 1) {
209+ cfb_imageblit(info, image);
210+ return;
211+ }
212+
213 dx = image->dx;
214 dy = image->dy;
215 width = image->width;
216@@ -579,18 +539,8 @@
217 if (dy + height > vyres)
218 height = vyres - dy;
219
220- /* For copies that aren't pixel expansion, there's little we
221- can do better than the generic code. */
222- /* ??? There is a DMA write mode; I wonder if that could be
223- made to pull the data from the image buffer... */
224- if (image->depth > 1) {
225- cfb_imageblit(info, image);
226- return;
227- }
228-
229 regs_base = par->tga_regs_base;
230 fb_base = par->tga_fb_base;
231- is8bpp = info->var.bits_per_pixel == 8;
232
233 /* Expand the color values to fill 32-bits. */
234 /* ??? Would be nice to notice colour changes elsewhere, so
235@@ -768,6 +718,86 @@
236 regs_base + TGA_MODE_REG);
237 }
238
239+static void
240+tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
241+{
242+ struct tga_par *par = (struct tga_par *) info->par;
243+ u32 color, dx, dy, width, height, vxres, vyres;
244+ u32 *palette = ((u32 *)info->pseudo_palette);
245+ unsigned long pos, line_length;
246+ unsigned long i, j;
247+ const unsigned char *data;
248+ void *regs_base, *fb_base;
249+
250+ dx = image->dx;
251+ dy = image->dy;
252+ width = image->width;
253+ height = image->height;
254+ vxres = info->var.xres_virtual;
255+ vyres = info->var.yres_virtual;
256+ line_length = info->fix.line_length;
257+
258+ /* Crop the image to the screen. */
259+ if (dx > vxres || dy > vyres)
260+ return;
261+ if (dx + width > vxres)
262+ width = vxres - dx;
263+ if (dy + height > vyres)
264+ height = vyres - dy;
265+
266+ regs_base = par->tga_regs_base;
267+ fb_base = par->tga_fb_base;
268+
269+ pos = dy * line_length + (dx * 4);
270+ data = image->data;
271+
272+ /* Now copy the image, color_expanding via the palette. */
273+ for (i = 0; i < height; i++) {
274+ for (j = 0; j < width; j++) {
275+ color = palette[*data++];
276+ __raw_writel(color, fb_base + pos + j*4);
277+ }
278+ pos += line_length;
279+ }
280+}
281+
282+/**
283+ * tgafb_imageblit - REQUIRED function. Can use generic routines if
284+ * non acclerated hardware and packed pixel based.
285+ * Copies a image from system memory to the screen.
286+ *
287+ * @info: frame buffer structure that represents a single frame buffer
288+ * @image: structure defining the image.
289+ */
290+static void
291+tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
292+{
293+ unsigned int is8bpp = info->var.bits_per_pixel == 8;
294+
295+ /* If a mono image, regardless of FB depth, go do it. */
296+ if (image->depth == 1) {
297+ tgafb_mono_imageblit(info, image);
298+ return;
299+ }
300+
301+ /* For copies that aren't pixel expansion, there's little we
302+ can do better than the generic code. */
303+ /* ??? There is a DMA write mode; I wonder if that could be
304+ made to pull the data from the image buffer... */
305+ if (image->depth == info->var.bits_per_pixel) {
306+ cfb_imageblit(info, image);
307+ return;
308+ }
309+
310+ /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
311+ if (!is8bpp && image->depth == 8) {
312+ tgafb_clut_imageblit(info, image);
313+ return;
314+ }
315+
316+ /* Silently return... */
317+}
318+
319 /**
320 * tgafb_fillrect - REQUIRED function. Can use generic routines if
321 * non acclerated hardware and packed pixel based.
322@@ -1360,6 +1390,31 @@
323 info->fix.ywrapstep = 0;
324
325 info->fix.accel = FB_ACCEL_DEC_TGA;
326+
327+ /*
328+ * These are needed by fb_set_logo_truepalette(), so we
329+ * set them here for 24-plane cards.
330+ */
331+ if (tga_type != TGA_TYPE_8PLANE) {
332+ info->var.red.length = 8;
333+ info->var.green.length = 8;
334+ info->var.blue.length = 8;
335+ info->var.red.offset = 16;
336+ info->var.green.offset = 8;
337+ info->var.blue.offset = 0;
338+ }
339+}
340+
341+static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
342+{
343+ /* We just use this to catch switches out of
344+ * graphics mode.
345+ */
346+ tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
347+
348+ if (var->xoffset || var->yoffset || var->vmode)
349+ return -EINVAL;
350+ return 0;
351 }
352
353 static __devinit int
354@@ -1371,15 +1426,10 @@
355 0xffffffff,
356 TGA_24PLUSZ_FB_OFFSET
357 };
358-
359- struct all_info {
360- struct fb_info info;
361- struct tga_par par;
362- u32 pseudo_palette[16];
363- } *all;
364-
365- void *mem_base;
366 unsigned long bar0_start, bar0_len;
367+ struct fb_info *info;
368+ struct tga_par *par;
369+ void *mem_base;
370 u8 tga_type;
371 int ret;
372
373@@ -1390,13 +1440,12 @@
374 }
375
376 /* Allocate the fb and par structures. */
377- all = kmalloc(sizeof(*all), GFP_KERNEL);
378- if (!all) {
379+ info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
380+ if (!info) {
381 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
382 return -ENOMEM;
383 }
384- memset(all, 0, sizeof(*all));
385- pci_set_drvdata(pdev, all);
386+ pci_set_drvdata(pdev, info);
387
388 /* Request the mem regions. */
389 bar0_start = pci_resource_start(pdev, 0);
c9d1c54c 390@@ -1416,25 +1465,23 @@
e1b172c5 391
392 /* Grab info about the card. */
393 tga_type = (readl(mem_base) >> 12) & 0x0f;
394- all->par.pdev = pdev;
395- all->par.tga_mem_base = mem_base;
396- all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
397- all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
398- all->par.tga_type = tga_type;
399- pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
400+ par = info->par;
401+ par->tga_mem_base = mem_base;
402+ par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
403+ par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
404+ par->tga_type = tga_type;
405+ pci_read_config_byte(pdev, PCI_REVISION_ID, par->tga_chip_rev);
406
407 /* Setup framebuffer. */
c9d1c54c
AM		 408- all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
409- FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
e1b172c5 410- all->info.fbops = &tgafb_ops;
411- all->info.screen_base = (char *) all->par.tga_fb_base;
412- all->info.currcon = -1;
413- all->info.par = &all->par;
414- all->info.pseudo_palette = all->pseudo_palette;
c9d1c54c
AM		 415+ info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
416+ FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
e1b172c5 417+ info->fbops = &tgafb_ops;
418+ info->screen_base = (char *) par->tga_fb_base;
419+ info->pseudo_palette = par->pseudo_palette;
420
421 /* This should give a reasonable default video mode. */
422
423- ret = fb_find_mode(&all->info.var, &all->info, mode_option,
424+ ret = fb_find_mode(&info->var, info, mode_option,
425 NULL, 0, NULL,
426 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
427 if (ret == 0 || ret == 4) {
428@@ -1442,35 +1489,34 @@
429 goto err1;
430 }
431
432- if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
433+ if (fb_alloc_cmap(&info->cmap, 256, 0)) {
434 printk(KERN_ERR "tgafb: Could not allocate color map\n");
435 ret = -ENOMEM;
436 goto err1;
437 }
438
439- tgafb_set_par(&all->info);
440- tgafb_init_fix(&all->info);
441+ tgafb_init_fix(info);
442
443- if (register_framebuffer(&all->info) < 0) {
444+ if (register_framebuffer(info) < 0) {
445 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
446 ret = -EINVAL;
447 goto err1;
448 }
449
450 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
451- all->par.tga_chip_rev);
452+ par->tga_chip_rev);
453 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
454 pdev->bus->number, PCI_SLOT(pdev->devfn),
455 PCI_FUNC(pdev->devfn));
456 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
457- all->info.node, all->info.fix.id, bar0_start);
458+ info->node, info->fix.id, bar0_start);
459
460 return 0;
461
462 err1:
463 release_mem_region(bar0_start, bar0_len);
464 err0:
465- kfree(all);
466+ framebuffer_release(info);
467 return ret;
468 }
469
470@@ -1493,7 +1539,7 @@
471 iounmap(par->tga_mem_base);
472 release_mem_region(pci_resource_start(pdev, 0),
473 pci_resource_len(pdev, 0));
474- kfree(info);
475+ framebuffer_release(info);
476 }
477
478 static void __exit
479diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tga.h fbdev-2.6/include/video/tga.h
480--- linus-2.6/include/video/tga.h 1969-12-31 16:00:00.000000000 -0800
481+++ fbdev-2.6/include/video/tga.h 2004-02-18 20:53:12.000000000 -0800
482@@ -0,0 +1,241 @@
483+/*
484+ * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
485+ *
486+ * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
487+ *
488+ * $Id$
489+ *
490+ * This file is subject to the terms and conditions of the GNU General Public
491+ * License. See the file COPYING in the main directory of this archive for
492+ * more details.
493+ */
494+
495+#ifndef TGAFB_H
496+#define TGAFB_H
497+
498+/*
499+ * TGA hardware description (minimal)
500+ */
501+
502+#define TGA_TYPE_8PLANE 0
503+#define TGA_TYPE_24PLANE 1
504+#define TGA_TYPE_24PLUSZ 3
505+
506+/*
507+ * Offsets within Memory Space
508+ */
509+
510+#define TGA_ROM_OFFSET 0x0000000
511+#define TGA_REGS_OFFSET 0x0100000
512+#define TGA_8PLANE_FB_OFFSET 0x0200000
513+#define TGA_24PLANE_FB_OFFSET 0x0804000
514+#define TGA_24PLUSZ_FB_OFFSET 0x1004000
515+
516+#define TGA_FOREGROUND_REG 0x0020
517+#define TGA_BACKGROUND_REG 0x0024
518+#define TGA_PLANEMASK_REG 0x0028
519+#define TGA_PIXELMASK_ONESHOT_REG 0x002c
520+#define TGA_MODE_REG 0x0030
521+#define TGA_RASTEROP_REG 0x0034
522+#define TGA_PIXELSHIFT_REG 0x0038
523+#define TGA_DEEP_REG 0x0050
524+#define TGA_PIXELMASK_REG 0x005c
525+#define TGA_CURSOR_BASE_REG 0x0060
526+#define TGA_HORIZ_REG 0x0064
527+#define TGA_VERT_REG 0x0068
528+#define TGA_BASE_ADDR_REG 0x006c
529+#define TGA_VALID_REG 0x0070
530+#define TGA_CURSOR_XY_REG 0x0074
531+#define TGA_INTR_STAT_REG 0x007c
532+#define TGA_DATA_REG 0x0080
533+#define TGA_RAMDAC_SETUP_REG 0x00c0
534+#define TGA_BLOCK_COLOR0_REG 0x0140
535+#define TGA_BLOCK_COLOR1_REG 0x0144
536+#define TGA_BLOCK_COLOR2_REG 0x0148
537+#define TGA_BLOCK_COLOR3_REG 0x014c
538+#define TGA_BLOCK_COLOR4_REG 0x0150
539+#define TGA_BLOCK_COLOR5_REG 0x0154
540+#define TGA_BLOCK_COLOR6_REG 0x0158
541+#define TGA_BLOCK_COLOR7_REG 0x015c
542+#define TGA_COPY64_SRC 0x0160
543+#define TGA_COPY64_DST 0x0164
544+#define TGA_CLOCK_REG 0x01e8
545+#define TGA_RAMDAC_REG 0x01f0
546+#define TGA_CMD_STAT_REG 0x01f8
547+
548+
549+/*
550+ * Useful defines for managing the registers
551+ */
552+
553+#define TGA_HORIZ_ODD 0x80000000
554+#define TGA_HORIZ_POLARITY 0x40000000
555+#define TGA_HORIZ_ACT_MSB 0x30000000
556+#define TGA_HORIZ_BP 0x0fe00000
557+#define TGA_HORIZ_SYNC 0x001fc000
558+#define TGA_HORIZ_FP 0x00007c00
559+#define TGA_HORIZ_ACT_LSB 0x000001ff
560+
561+#define TGA_VERT_SE 0x80000000
562+#define TGA_VERT_POLARITY 0x40000000
563+#define TGA_VERT_RESERVED 0x30000000
564+#define TGA_VERT_BP 0x0fc00000
565+#define TGA_VERT_SYNC 0x003f0000
566+#define TGA_VERT_FP 0x0000f800
567+#define TGA_VERT_ACTIVE 0x000007ff
568+
569+#define TGA_VALID_VIDEO 0x01
570+#define TGA_VALID_BLANK 0x02
571+#define TGA_VALID_CURSOR 0x04
572+
573+#define TGA_MODE_SBM_8BPP 0x000
574+#define TGA_MODE_SBM_24BPP 0x300
575+
576+#define TGA_MODE_SIMPLE 0x00
577+#define TGA_MODE_SIMPLEZ 0x10
578+#define TGA_MODE_OPAQUE_STIPPLE 0x01
579+#define TGA_MODE_OPAQUE_FILL 0x21
580+#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
581+#define TGA_MODE_TRANSPARENT_FILL 0x23
582+#define TGA_MODE_BLOCK_STIPPLE 0x0d
583+#define TGA_MODE_BLOCK_FILL 0x2d
584+#define TGA_MODE_COPY 0x07
585+#define TGA_MODE_DMA_READ_COPY_ND 0x17
586+#define TGA_MODE_DMA_READ_COPY_D 0x37
587+#define TGA_MODE_DMA_WRITE_COPY 0x1f
588+
589+
590+/*
591+ * Useful defines for managing the ICS1562 PLL clock
592+ */
593+
594+#define TGA_PLL_BASE_FREQ 14318 /* .18 */
595+#define TGA_PLL_MAX_FREQ 230000
596+
597+
598+/*
599+ * Useful defines for managing the BT485 on the 8-plane TGA
600+ */
601+
602+#define BT485_READ_BIT 0x01
603+#define BT485_WRITE_BIT 0x00
604+
605+#define BT485_ADDR_PAL_WRITE 0x00
606+#define BT485_DATA_PAL 0x02
607+#define BT485_PIXEL_MASK 0x04
608+#define BT485_ADDR_PAL_READ 0x06
609+#define BT485_ADDR_CUR_WRITE 0x08
610+#define BT485_DATA_CUR 0x0a
611+#define BT485_CMD_0 0x0c
612+#define BT485_ADDR_CUR_READ 0x0e
613+#define BT485_CMD_1 0x10
614+#define BT485_CMD_2 0x12
615+#define BT485_STATUS 0x14
616+#define BT485_CMD_3 0x14
617+#define BT485_CUR_RAM 0x16
618+#define BT485_CUR_LOW_X 0x18
619+#define BT485_CUR_HIGH_X 0x1a
620+#define BT485_CUR_LOW_Y 0x1c
621+#define BT485_CUR_HIGH_Y 0x1e
622+
623+
624+/*
625+ * Useful defines for managing the BT463 on the 24-plane TGAs
626+ */
627+
628+#define BT463_ADDR_LO 0x0
629+#define BT463_ADDR_HI 0x1
630+#define BT463_REG_ACC 0x2
631+#define BT463_PALETTE 0x3
632+
633+#define BT463_CUR_CLR_0 0x0100
634+#define BT463_CUR_CLR_1 0x0101
635+
636+#define BT463_CMD_REG_0 0x0201
637+#define BT463_CMD_REG_1 0x0202
638+#define BT463_CMD_REG_2 0x0203
639+
640+#define BT463_READ_MASK_0 0x0205
641+#define BT463_READ_MASK_1 0x0206
642+#define BT463_READ_MASK_2 0x0207
643+#define BT463_READ_MASK_3 0x0208
644+
645+#define BT463_BLINK_MASK_0 0x0209
646+#define BT463_BLINK_MASK_1 0x020a
647+#define BT463_BLINK_MASK_2 0x020b
648+#define BT463_BLINK_MASK_3 0x020c
649+
650+#define BT463_WINDOW_TYPE_BASE 0x0300
651+
652+#ifdef __KERNEL__
653+
654+/*
655+ * The framebuffer driver private data.
656+ */
657+
658+struct tga_par {
659+ /* PCI device. */
660+ struct pci_dev *pdev;
661+
662+ /* Device dependent information. */
663+ void *tga_mem_base;
664+ void *tga_fb_base;
665+ void *tga_regs_base;
666+ u8 tga_type; /* TGA_TYPE_XXX */
667+ u8 tga_chip_rev; /* dc21030 revision */
668+
669+ /* Remember blank mode. */
670+ u8 vesa_blanked;
671+
672+ /* Define the video mode. */
673+ u32 xres, yres; /* resolution in pixels */
674+ u32 htimings; /* horizontal timing register */
675+ u32 vtimings; /* vertical timing register */
676+ u32 pll_freq; /* pixclock in mhz */
677+ u32 bits_per_pixel; /* bits per pixel */
678+ u32 sync_on_green; /* set if sync is on green */
679+};
680+
681+
682+/*
683+ * Macros for reading/writing TGA and RAMDAC registers
684+ */
685+
686+static inline void
687+TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
688+{
689+ writel(v, par->tga_regs_base +r);
690+}
691+
692+static inline u32
693+TGA_READ_REG(struct tga_par *par, u32 r)
694+{
695+ return readl(par->tga_regs_base +r);
696+}
697+
698+static inline void
699+BT485_WRITE(struct tga_par *par, u8 v, u8 r)
700+{
701+ TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
702+ TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
703+}
704+
705+static inline void
706+BT463_LOAD_ADDR(struct tga_par *par, u16 a)
707+{
708+ TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
709+ TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
710+ TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
711+ TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
712+}
713+
714+static inline void
715+BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
716+{
717+ BT463_LOAD_ADDR(par, a);
718+ TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
719+ TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
720+}
721+#endif /* __KERNEL__ */
722+
723+#endif /* TGAFB_H */
724diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tgafb.h fbdev-2.6/include/video/tgafb.h
725--- linus-2.6/include/video/tgafb.h 2004-02-18 21:01:55.000000000 -0800
726+++ fbdev-2.6/include/video/tgafb.h 1969-12-31 16:00:00.000000000 -0800
727@@ -1,238 +0,0 @@
728-/*
729- * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
730- *
731- * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
732- *
733- * $Id$
734- *
735- * This file is subject to the terms and conditions of the GNU General Public
736- * License. See the file COPYING in the main directory of this archive for
737- * more details.
738- */
739-
740-#ifndef TGAFB_H
741-#define TGAFB_H
742-
743-/*
744- * TGA hardware description (minimal)
745- */
746-
747-#define TGA_TYPE_8PLANE 0
748-#define TGA_TYPE_24PLANE 1
749-#define TGA_TYPE_24PLUSZ 3
750-
751-/*
752- * Offsets within Memory Space
753- */
754-
755-#define TGA_ROM_OFFSET 0x0000000
756-#define TGA_REGS_OFFSET 0x0100000
757-#define TGA_8PLANE_FB_OFFSET 0x0200000
758-#define TGA_24PLANE_FB_OFFSET 0x0804000
759-#define TGA_24PLUSZ_FB_OFFSET 0x1004000
760-
761-#define TGA_FOREGROUND_REG 0x0020
762-#define TGA_BACKGROUND_REG 0x0024
763-#define TGA_PLANEMASK_REG 0x0028
764-#define TGA_PIXELMASK_ONESHOT_REG 0x002c
765-#define TGA_MODE_REG 0x0030
766-#define TGA_RASTEROP_REG 0x0034
767-#define TGA_PIXELSHIFT_REG 0x0038
768-#define TGA_DEEP_REG 0x0050
769-#define TGA_PIXELMASK_REG 0x005c
770-#define TGA_CURSOR_BASE_REG 0x0060
771-#define TGA_HORIZ_REG 0x0064
772-#define TGA_VERT_REG 0x0068
773-#define TGA_BASE_ADDR_REG 0x006c
774-#define TGA_VALID_REG 0x0070
775-#define TGA_CURSOR_XY_REG 0x0074
776-#define TGA_INTR_STAT_REG 0x007c
777-#define TGA_DATA_REG 0x0080
778-#define TGA_RAMDAC_SETUP_REG 0x00c0
779-#define TGA_BLOCK_COLOR0_REG 0x0140
780-#define TGA_BLOCK_COLOR1_REG 0x0144
781-#define TGA_BLOCK_COLOR2_REG 0x0148
782-#define TGA_BLOCK_COLOR3_REG 0x014c
783-#define TGA_BLOCK_COLOR4_REG 0x0150
784-#define TGA_BLOCK_COLOR5_REG 0x0154
785-#define TGA_BLOCK_COLOR6_REG 0x0158
786-#define TGA_BLOCK_COLOR7_REG 0x015c
787-#define TGA_COPY64_SRC 0x0160
788-#define TGA_COPY64_DST 0x0164
789-#define TGA_CLOCK_REG 0x01e8
790-#define TGA_RAMDAC_REG 0x01f0
791-#define TGA_CMD_STAT_REG 0x01f8
792-
793-
794-/*
795- * Useful defines for managing the registers
796- */
797-
798-#define TGA_HORIZ_ODD 0x80000000
799-#define TGA_HORIZ_POLARITY 0x40000000
800-#define TGA_HORIZ_ACT_MSB 0x30000000
801-#define TGA_HORIZ_BP 0x0fe00000
802-#define TGA_HORIZ_SYNC 0x001fc000
803-#define TGA_HORIZ_FP 0x00007c00
804-#define TGA_HORIZ_ACT_LSB 0x000001ff
805-
806-#define TGA_VERT_SE 0x80000000
807-#define TGA_VERT_POLARITY 0x40000000
808-#define TGA_VERT_RESERVED 0x30000000
809-#define TGA_VERT_BP 0x0fc00000
810-#define TGA_VERT_SYNC 0x003f0000
811-#define TGA_VERT_FP 0x0000f800
812-#define TGA_VERT_ACTIVE 0x000007ff
813-
814-#define TGA_VALID_VIDEO 0x01
815-#define TGA_VALID_BLANK 0x02
816-#define TGA_VALID_CURSOR 0x04
817-
818-#define TGA_MODE_SBM_8BPP 0x000
819-#define TGA_MODE_SBM_24BPP 0x300
820-
821-#define TGA_MODE_SIMPLE 0x00
822-#define TGA_MODE_SIMPLEZ 0x10
823-#define TGA_MODE_OPAQUE_STIPPLE 0x01
824-#define TGA_MODE_OPAQUE_FILL 0x21
825-#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
826-#define TGA_MODE_TRANSPARENT_FILL 0x23
827-#define TGA_MODE_BLOCK_STIPPLE 0x0d
828-#define TGA_MODE_BLOCK_FILL 0x2d
829-#define TGA_MODE_COPY 0x07
830-#define TGA_MODE_DMA_READ_COPY_ND 0x17
831-#define TGA_MODE_DMA_READ_COPY_D 0x37
832-#define TGA_MODE_DMA_WRITE_COPY 0x1f
833-
834-
835-/*
836- * Useful defines for managing the ICS1562 PLL clock
837- */
838-
839-#define TGA_PLL_BASE_FREQ 14318 /* .18 */
840-#define TGA_PLL_MAX_FREQ 230000
841-
842-
843-/*
844- * Useful defines for managing the BT485 on the 8-plane TGA
845- */
846-
847-#define BT485_READ_BIT 0x01
848-#define BT485_WRITE_BIT 0x00
849-
850-#define BT485_ADDR_PAL_WRITE 0x00
851-#define BT485_DATA_PAL 0x02
852-#define BT485_PIXEL_MASK 0x04
853-#define BT485_ADDR_PAL_READ 0x06
854-#define BT485_ADDR_CUR_WRITE 0x08
855-#define BT485_DATA_CUR 0x0a
856-#define BT485_CMD_0 0x0c
857-#define BT485_ADDR_CUR_READ 0x0e
858-#define BT485_CMD_1 0x10
859-#define BT485_CMD_2 0x12
860-#define BT485_STATUS 0x14
861-#define BT485_CMD_3 0x14
862-#define BT485_CUR_RAM 0x16
863-#define BT485_CUR_LOW_X 0x18
864-#define BT485_CUR_HIGH_X 0x1a
865-#define BT485_CUR_LOW_Y 0x1c
866-#define BT485_CUR_HIGH_Y 0x1e
867-
868-
869-/*
870- * Useful defines for managing the BT463 on the 24-plane TGAs
871- */
872-
873-#define BT463_ADDR_LO 0x0
874-#define BT463_ADDR_HI 0x1
875-#define BT463_REG_ACC 0x2
876-#define BT463_PALETTE 0x3
877-
878-#define BT463_CUR_CLR_0 0x0100
879-#define BT463_CUR_CLR_1 0x0101
880-
881-#define BT463_CMD_REG_0 0x0201
882-#define BT463_CMD_REG_1 0x0202
883-#define BT463_CMD_REG_2 0x0203
884-
885-#define BT463_READ_MASK_0 0x0205
886-#define BT463_READ_MASK_1 0x0206
887-#define BT463_READ_MASK_2 0x0207
888-#define BT463_READ_MASK_3 0x0208
889-
890-#define BT463_BLINK_MASK_0 0x0209
891-#define BT463_BLINK_MASK_1 0x020a
892-#define BT463_BLINK_MASK_2 0x020b
893-#define BT463_BLINK_MASK_3 0x020c
894-
895-#define BT463_WINDOW_TYPE_BASE 0x0300
896-
897-/*
898- * The framebuffer driver private data.
899- */
900-
901-struct tga_par {
902- /* PCI device. */
903- struct pci_dev *pdev;
904-
905- /* Device dependent information. */
906- void *tga_mem_base;
907- void *tga_fb_base;
908- void *tga_regs_base;
909- u8 tga_type; /* TGA_TYPE_XXX */
910- u8 tga_chip_rev; /* dc21030 revision */
911-
912- /* Remember blank mode. */
913- u8 vesa_blanked;
914-
915- /* Define the video mode. */
916- u32 xres, yres; /* resolution in pixels */
917- u32 htimings; /* horizontal timing register */
918- u32 vtimings; /* vertical timing register */
919- u32 pll_freq; /* pixclock in mhz */
920- u32 bits_per_pixel; /* bits per pixel */
921- u32 sync_on_green; /* set if sync is on green */
922-};
923-
924-
925-/*
926- * Macros for reading/writing TGA and RAMDAC registers
927- */
928-
929-static inline void
930-TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
931-{
932- writel(v, par->tga_regs_base +r);
933-}
934-
935-static inline u32
936-TGA_READ_REG(struct tga_par *par, u32 r)
937-{
938- return readl(par->tga_regs_base +r);
939-}
940-
941-static inline void
942-BT485_WRITE(struct tga_par *par, u8 v, u8 r)
943-{
944- TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
945- TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
946-}
947-
948-static inline void
949-BT463_LOAD_ADDR(struct tga_par *par, u16 a)
950-{
951- TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
952- TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
953- TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
954- TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
955-}
956-
957-static inline void
958-BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
959-{
960- BT463_LOAD_ADDR(par, a);
961- TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
962- TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
963-}
964-
965-#endif /* TGAFB_H */
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