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- [2.4.2x, 2.6.x] don't recursively crash in die() on CHRP/PReP machines
[packages/kernel.git] / 2.6.0-sensors-chip-update-2of4-lkml.patch
CommitLineData
1d9df89a 1--- linux-2.6.0-test11-mmh/drivers/i2c/chips/w83781d.c.old 2003-12-14 17:22:51.307815925 -0500
2+++ linux-2.6.0-test11-mmh/drivers/i2c/chips/w83781d.c 2003-12-14 17:20:35.000000000 -0500
3@@ -208,72 +208,6 @@
4 return ((u8) i);
5 }
6
7-/* Initial limits */
8-#define W83781D_INIT_IN_0 (vid == 3500 ? 280 : vid / 10)
9-#define W83781D_INIT_IN_1 (vid == 3500 ? 280 : vid / 10)
10-#define W83781D_INIT_IN_2 330
11-#define W83781D_INIT_IN_3 (((500) * 100) / 168)
12-#define W83781D_INIT_IN_4 (((1200) * 10) / 38)
13-#define W83781D_INIT_IN_5 (((-1200) * -604) / 2100)
14-#define W83781D_INIT_IN_6 (((-500) * -604) / 909)
15-#define W83781D_INIT_IN_7 (((500) * 100) / 168)
16-#define W83781D_INIT_IN_8 300
17-/* Initial limits for 782d/783s negative voltages */
18-/* Note level shift. Change min/max below if you change these. */
19-#define W83782D_INIT_IN_5 ((((-1200) + 1491) * 100)/514)
20-#define W83782D_INIT_IN_6 ((( (-500) + 771) * 100)/314)
21-
22-#define W83781D_INIT_IN_PERCENTAGE 10
23-#define W83781D_INIT_IN_MIN(val) (val - val * W83781D_INIT_IN_PERCENTAGE / 100)
24-#define W83781D_INIT_IN_MAX(val) (val + val * W83781D_INIT_IN_PERCENTAGE / 100)
25-
26-#define W83781D_INIT_IN_MIN_0 W83781D_INIT_IN_MIN(W83781D_INIT_IN_0)
27-#define W83781D_INIT_IN_MAX_0 W83781D_INIT_IN_MAX(W83781D_INIT_IN_0)
28-#define W83781D_INIT_IN_MIN_1 W83781D_INIT_IN_MIN(W83781D_INIT_IN_1)
29-#define W83781D_INIT_IN_MAX_1 W83781D_INIT_IN_MAX(W83781D_INIT_IN_1)
30-#define W83781D_INIT_IN_MIN_2 W83781D_INIT_IN_MIN(W83781D_INIT_IN_2)
31-#define W83781D_INIT_IN_MAX_2 W83781D_INIT_IN_MAX(W83781D_INIT_IN_2)
32-#define W83781D_INIT_IN_MIN_3 W83781D_INIT_IN_MIN(W83781D_INIT_IN_3)
33-#define W83781D_INIT_IN_MAX_3 W83781D_INIT_IN_MAX(W83781D_INIT_IN_3)
34-#define W83781D_INIT_IN_MIN_4 W83781D_INIT_IN_MIN(W83781D_INIT_IN_4)
35-#define W83781D_INIT_IN_MAX_4 W83781D_INIT_IN_MAX(W83781D_INIT_IN_4)
36-#define W83781D_INIT_IN_MIN_5 W83781D_INIT_IN_MIN(W83781D_INIT_IN_5)
37-#define W83781D_INIT_IN_MAX_5 W83781D_INIT_IN_MAX(W83781D_INIT_IN_5)
38-#define W83781D_INIT_IN_MIN_6 W83781D_INIT_IN_MIN(W83781D_INIT_IN_6)
39-#define W83781D_INIT_IN_MAX_6 W83781D_INIT_IN_MAX(W83781D_INIT_IN_6)
40-#define W83781D_INIT_IN_MIN_7 W83781D_INIT_IN_MIN(W83781D_INIT_IN_7)
41-#define W83781D_INIT_IN_MAX_7 W83781D_INIT_IN_MAX(W83781D_INIT_IN_7)
42-#define W83781D_INIT_IN_MIN_8 W83781D_INIT_IN_MIN(W83781D_INIT_IN_8)
43-#define W83781D_INIT_IN_MAX_8 W83781D_INIT_IN_MAX(W83781D_INIT_IN_8)
44-
45-/* Initial limits for 782d/783s negative voltages */
46-/* These aren't direct multiples because of level shift */
47-/* Beware going negative - check */
48-#define W83782D_INIT_IN_MIN_5_TMP \
49- (((-1200 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514)
50-#define W83782D_INIT_IN_MIN_5 \
51- ((W83782D_INIT_IN_MIN_5_TMP > 0) ? W83782D_INIT_IN_MIN_5_TMP : 0)
52-#define W83782D_INIT_IN_MAX_5 \
53- (((-1200 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514)
54-#define W83782D_INIT_IN_MIN_6_TMP \
55- ((( -500 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314)
56-#define W83782D_INIT_IN_MIN_6 \
57- ((W83782D_INIT_IN_MIN_6_TMP > 0) ? W83782D_INIT_IN_MIN_6_TMP : 0)
58-#define W83782D_INIT_IN_MAX_6 \
59- ((( -500 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314)
60-
61-#define W83781D_INIT_FAN_MIN_1 3000
62-#define W83781D_INIT_FAN_MIN_2 3000
63-#define W83781D_INIT_FAN_MIN_3 3000
64-
65-/* temp = value / 100 */
66-#define W83781D_INIT_TEMP_OVER 6000
67-#define W83781D_INIT_TEMP_HYST 12700 /* must be 127 for ALARM to work */
68-#define W83781D_INIT_TEMP2_OVER 6000
69-#define W83781D_INIT_TEMP2_HYST 5000
70-#define W83781D_INIT_TEMP3_OVER 6000
71-#define W83781D_INIT_TEMP3_HYST 5000
72-
73 /* There are some complications in a module like this. First off, W83781D chips
74 may be both present on the SMBus and the ISA bus, and we have to handle
75 those cases separately at some places. Second, there might be several
76@@ -1688,113 +1622,6 @@
77 #endif /* W83781D_RT */
78
79 if (init) {
80- w83781d_write_value(client, W83781D_REG_IN_MIN(0),
81- IN_TO_REG(W83781D_INIT_IN_MIN_0));
82- w83781d_write_value(client, W83781D_REG_IN_MAX(0),
83- IN_TO_REG(W83781D_INIT_IN_MAX_0));
84- if (type != w83783s && type != w83697hf) {
85- w83781d_write_value(client, W83781D_REG_IN_MIN(1),
86- IN_TO_REG(W83781D_INIT_IN_MIN_1));
87- w83781d_write_value(client, W83781D_REG_IN_MAX(1),
88- IN_TO_REG(W83781D_INIT_IN_MAX_1));
89- }
90-
91- w83781d_write_value(client, W83781D_REG_IN_MIN(2),
92- IN_TO_REG(W83781D_INIT_IN_MIN_2));
93- w83781d_write_value(client, W83781D_REG_IN_MAX(2),
94- IN_TO_REG(W83781D_INIT_IN_MAX_2));
95- w83781d_write_value(client, W83781D_REG_IN_MIN(3),
96- IN_TO_REG(W83781D_INIT_IN_MIN_3));
97- w83781d_write_value(client, W83781D_REG_IN_MAX(3),
98- IN_TO_REG(W83781D_INIT_IN_MAX_3));
99- w83781d_write_value(client, W83781D_REG_IN_MIN(4),
100- IN_TO_REG(W83781D_INIT_IN_MIN_4));
101- w83781d_write_value(client, W83781D_REG_IN_MAX(4),
102- IN_TO_REG(W83781D_INIT_IN_MAX_4));
103- if (type == w83781d || type == as99127f) {
104- w83781d_write_value(client, W83781D_REG_IN_MIN(5),
105- IN_TO_REG(W83781D_INIT_IN_MIN_5));
106- w83781d_write_value(client, W83781D_REG_IN_MAX(5),
107- IN_TO_REG(W83781D_INIT_IN_MAX_5));
108- } else {
109- w83781d_write_value(client, W83781D_REG_IN_MIN(5),
110- IN_TO_REG(W83782D_INIT_IN_MIN_5));
111- w83781d_write_value(client, W83781D_REG_IN_MAX(5),
112- IN_TO_REG(W83782D_INIT_IN_MAX_5));
113- }
114- if (type == w83781d || type == as99127f) {
115- w83781d_write_value(client, W83781D_REG_IN_MIN(6),
116- IN_TO_REG(W83781D_INIT_IN_MIN_6));
117- w83781d_write_value(client, W83781D_REG_IN_MAX(6),
118- IN_TO_REG(W83781D_INIT_IN_MAX_6));
119- } else {
120- w83781d_write_value(client, W83781D_REG_IN_MIN(6),
121- IN_TO_REG(W83782D_INIT_IN_MIN_6));
122- w83781d_write_value(client, W83781D_REG_IN_MAX(6),
123- IN_TO_REG(W83782D_INIT_IN_MAX_6));
124- }
125- if ((type == w83782d) || (type == w83627hf) ||
126- (type == w83697hf)) {
127- w83781d_write_value(client, W83781D_REG_IN_MIN(7),
128- IN_TO_REG(W83781D_INIT_IN_MIN_7));
129- w83781d_write_value(client, W83781D_REG_IN_MAX(7),
130- IN_TO_REG(W83781D_INIT_IN_MAX_7));
131- w83781d_write_value(client, W83781D_REG_IN_MIN(8),
132- IN_TO_REG(W83781D_INIT_IN_MIN_8));
133- w83781d_write_value(client, W83781D_REG_IN_MAX(8),
134- IN_TO_REG(W83781D_INIT_IN_MAX_8));
135- w83781d_write_value(client, W83781D_REG_VBAT,
136- (w83781d_read_value
137- (client,
138- W83781D_REG_VBAT) | 0x01));
139- }
140- w83781d_write_value(client, W83781D_REG_FAN_MIN(1),
141- FAN_TO_REG(W83781D_INIT_FAN_MIN_1, 2));
142- w83781d_write_value(client, W83781D_REG_FAN_MIN(2),
143- FAN_TO_REG(W83781D_INIT_FAN_MIN_2, 2));
144- if (type != w83697hf) {
145- w83781d_write_value(client, W83781D_REG_FAN_MIN(3),
146- FAN_TO_REG(W83781D_INIT_FAN_MIN_3,
147- 2));
148- }
149-
150- w83781d_write_value(client, W83781D_REG_TEMP_OVER(1),
151- TEMP_TO_REG(W83781D_INIT_TEMP_OVER));
152- w83781d_write_value(client, W83781D_REG_TEMP_HYST(1),
153- TEMP_TO_REG(W83781D_INIT_TEMP_HYST));
154-
155- if (type == as99127f) {
156- w83781d_write_value(client, W83781D_REG_TEMP_OVER(2),
157- AS99127_TEMP_ADD_TO_REG
158- (W83781D_INIT_TEMP2_OVER));
159- w83781d_write_value(client, W83781D_REG_TEMP_HYST(2),
160- AS99127_TEMP_ADD_TO_REG
161- (W83781D_INIT_TEMP2_HYST));
162- } else {
163- w83781d_write_value(client, W83781D_REG_TEMP_OVER(2),
164- TEMP_ADD_TO_REG
165- (W83781D_INIT_TEMP2_OVER));
166- w83781d_write_value(client, W83781D_REG_TEMP_HYST(2),
167- TEMP_ADD_TO_REG
168- (W83781D_INIT_TEMP2_HYST));
169- }
170- w83781d_write_value(client, W83781D_REG_TEMP2_CONFIG, 0x00);
171-
172- if (type == as99127f) {
173- w83781d_write_value(client, W83781D_REG_TEMP_OVER(3),
174- AS99127_TEMP_ADD_TO_REG
175- (W83781D_INIT_TEMP3_OVER));
176- w83781d_write_value(client, W83781D_REG_TEMP_HYST(3),
177- AS99127_TEMP_ADD_TO_REG
178- (W83781D_INIT_TEMP3_HYST));
179- } else if (type != w83783s && type != w83697hf) {
180- w83781d_write_value(client, W83781D_REG_TEMP_OVER(3),
181- TEMP_ADD_TO_REG
182- (W83781D_INIT_TEMP3_OVER));
183- w83781d_write_value(client, W83781D_REG_TEMP_HYST(3),
184- TEMP_ADD_TO_REG
185- (W83781D_INIT_TEMP3_HYST));
186- }
187 if (type != w83783s && type != w83697hf) {
188 w83781d_write_value(client, W83781D_REG_TEMP3_CONFIG,
189 0x00);
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