]> git.pld-linux.org Git - packages/beignet.git/commitdiff
Add support for some newer Skylake CPUs auto/th/beignet-1.3.1-2
authorJacek Konieczny <jajcus@jajcus.net>
Wed, 14 Jun 2017 15:39:27 +0000 (17:39 +0200)
committerJacek Konieczny <jajcus@jajcus.net>
Wed, 14 Jun 2017 15:39:27 +0000 (17:39 +0200)
Release: 2

beignet.spec
new_SKL_ids.patch [new file with mode: 0644]

index a5a111afb60133d5bde3eee9f57a6ccc322b5966..ed8adc4b111b4d7a19056c93fc58b7449f69714f 100644 (file)
@@ -2,13 +2,14 @@ Summary:      Open source implementation of the OpenCL specification for Intel GPUs
 Summary(pl.UTF-8):     Mająca otwarte źródła implementacja specyfikacji OpenCL dla GPU formy Intel
 Name:          beignet
 Version:       1.3.1
-Release:       1
+Release:       2
 License:       LGPL v2+
 Group:         Libraries
 Source0:       https://01.org/sites/default/files/beignet-%{version}-source.tar.gz
 # Source0-md5: 850886a71a34672ca26a42046d0bb442
 Patch0:                cflags.patch
 Patch1:                static_llvm.patch
+Patch2:                new_SKL_ids.patch
 URL:           http://www.freedesktop.org/wiki/Software/Beignet/
 BuildRequires: Mesa-libgbm-devel
 BuildRequires: Mesa-libGL-devel >= 13.0.0
@@ -54,6 +55,7 @@ poleceń, jądra i programów oraz uruchamia je na GPU.
 %setup -qn Beignet-%{version}-Source
 %patch0 -p1
 %patch1 -p1
+%patch2 -p1
 
 %build
 install -d build
diff --git a/new_SKL_ids.patch b/new_SKL_ids.patch
new file mode 100644 (file)
index 0000000..cbdb9df
--- /dev/null
@@ -0,0 +1,39 @@
+diff --git a/src/cl_device_data.h b/src/cl_device_data.h
+index c3d6c45..123b619 100644
+--- a/src/cl_device_data.h
++++ b/src/cl_device_data.h
+@@ -247,7 +247,9 @@
+ /* SKL */
+ #define PCI_CHIP_SKYLAKE_ULT_GT1      0x1906   /* Intel(R) Skylake ULT - GT1 */
+ #define PCI_CHIP_SKYLAKE_ULT_GT2      0x1916   /* Intel(R) Skylake ULT - GT2 */
+-#define PCI_CHIP_SKYLAKE_ULT_GT3      0x1926   /* Intel(R) Skylake ULT - GT3 */
++#define PCI_CHIP_SKYLAKE_ULT_GT3      0x1923   /* Intel(R) Skylake ULT - GT3 */
++#define PCI_CHIP_SKYLAKE_ULT_GT3E1    0x1926   /* Intel(R) Skylake ULT - GT3E */
++#define PCI_CHIP_SKYLAKE_ULT_GT3E2    0x1927   /* Intel(R) Skylake ULT - GT3E */
+ #define PCI_CHIP_SKYLAKE_ULT_GT2F     0x1921   /* Intel(R) Skylake ULT - GT2F */
+ #define PCI_CHIP_SKYLAKE_ULX_GT1      0x190E   /* Intel(R) Skylake ULX - GT1 */
+ #define PCI_CHIP_SKYLAKE_ULX_GT2      0x191E   /* Intel(R) Skylake ULX - GT2 */
+@@ -284,6 +286,8 @@
+ #define IS_SKL_GT3(devid)               \
+   (devid == PCI_CHIP_SKYLAKE_ULT_GT3 ||   \
++   devid == PCI_CHIP_SKYLAKE_ULT_GT3E1 ||   \
++   devid == PCI_CHIP_SKYLAKE_ULT_GT3E2 ||   \
+    devid == PCI_CHIP_SKYLAKE_HALO_GT3 || \
+    devid == PCI_CHIP_SKYLAKE_SRV_GT3 || \
+    devid == PCI_CHIP_SKYLAKE_MEDIA_SRV_GT3)
+diff --git a/src/cl_device_id.c b/src/cl_device_id.c
+index 76549a4..b9a60bb 100644
+--- a/src/cl_device_id.c
++++ b/src/cl_device_id.c
+@@ -605,6 +605,10 @@ skl_gt2_break:
+     case PCI_CHIP_SKYLAKE_ULT_GT3:
+       DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, name, "Intel(R) HD Graphics Skylake ULT GT3");
++    case PCI_CHIP_SKYLAKE_ULT_GT3E1:
++      DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, name, "Intel(R) HD Graphics Skylake ULT GT3E");
++    case PCI_CHIP_SKYLAKE_ULT_GT3E2:
++      DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, name, "Intel(R) HD Graphics Skylake ULT GT3E");
+     case PCI_CHIP_SKYLAKE_HALO_GT3:
+       DECL_INFO_STRING(skl_gt3_break, intel_skl_gt3_device, name, "Intel(R) HD Graphics Skylake Halo GT3");
+     case PCI_CHIP_SKYLAKE_SRV_GT3:
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