x32.patch

   1 diff -ur qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/build/config/compiler/BUILD.gn qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/build/config/compiler/BUILD.gn
   2 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/build/config/compiler/BUILD.gn      2018-06-15 09:47:20.000000000 +0200
   3 +++ qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/build/config/compiler/BUILD.gn  2018-08-13 01:44:53.799249439 +0200
   4 @@ -661,14 +661,7 @@
   5    if (is_posix && !(is_mac || is_ios)) {
   6      # CPU architecture. We may or may not be doing a cross compile now, so for
   7      # simplicity we always explicitly set the architecture.
   8 -    if (current_cpu == "x64") {
   9 -      cflags += [
  10 -        "-m64",
  11 -      ]
  12 -      ldflags += [ "-m64" ]
  13 -    } else if (current_cpu == "x86") {
  14 -      cflags += [ "-m32" ]
  15 -      ldflags += [ "-m32" ]
  16 +    if (current_cpu == "x86") {
  17        if (!is_nacl) {
  18          cflags += [
  19            "-msse2",
  20 diff -ur qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/third_party/boringssl/src/crypto/fipsmodule/rand/urandom.c qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/third_party/boringssl/src/crypto/fipsmodule/rand/urandom.c
  21 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/third_party/boringssl/src/crypto/fipsmodule/rand/urandom.c  2018-06-15 09:47:20.000000000 +0200
  22 +++ qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/third_party/boringssl/src/crypto/fipsmodule/rand/urandom.c      2018-08-13 01:55:47.227682313 +0200
  23 @@ -47,7 +47,11 @@
  24  #if defined(OPENSSL_LINUX)
  25
  26  #if defined(OPENSSL_X86_64)
  27 +#if defined(__ILP32__)
  28 +#define EXPECTED_NR_getrandom (__X32_SYSCALL_BIT + 318)
  29 +#else
  30  #define EXPECTED_NR_getrandom 318
  31 +#endif
  32  #elif defined(OPENSSL_X86)
  33  #define EXPECTED_NR_getrandom 355
  34  #elif defined(OPENSSL_AARCH64)
  35 diff -ur qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/v8/src/objects/bigint.cc qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/v8/src/objects/bigint.cc
  36 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/v8/src/objects/bigint.cc    2018-06-15 09:47:20.000000000 +0200
  37 +++ qtwebengine-everywhere-src-5.11.1-x32/src/3rdparty/chromium/v8/src/objects/bigint.cc        2018-08-13 02:15:32.443103386 +0200
  38 @@ -2162,7 +2162,7 @@
  39  BigInt::digit_t MutableBigInt::digit_div(digit_t high, digit_t low,
  40                                           digit_t divisor, digit_t* remainder) {
  41    DCHECK(high < divisor);
  42 -#if V8_TARGET_ARCH_X64 && (__GNUC__ || __clang__)
  43 +#if V8_TARGET_ARCH_X64 && (__GNUC__ || __clang__) && !defined(__ILP32__)
  44    digit_t quotient;
  45    digit_t rem;
  46    __asm__("divq  %[divisor]"
  47 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/v8/src/compiler/instruction-selector.cc.orig        2018-06-15 09:47:20.000000000 +0200
  48 +++ qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/v8/src/compiler/instruction-selector.cc     2018-08-14 09:18:33.177100945 +0200
  49 @@ -1927,7 +1927,7 @@
  50  }
  51
  52  // 32 bit targets do not implement the following instructions.
  53 -#if V8_TARGET_ARCH_32_BIT
  54 +#if V8_TARGET_ARCH_32_BIT && !V8_TARGET_ARCH_X64
  55
  56  void InstructionSelector::VisitWord64And(Node* node) { UNIMPLEMENTED(); }
  57
  58 @@ -2081,7 +2081,7 @@
  59  #endif  // V8_TARGET_ARCH_32_BIT
  60
  61  // 64 bit targets do not implement the following instructions.
  62 -#if V8_TARGET_ARCH_64_BIT
  63 +#if V8_TARGET_ARCH_64_BIT || V8_TARGET_ARCH_X64
  64  void InstructionSelector::VisitInt32PairAdd(Node* node) { UNIMPLEMENTED(); }
  65
  66  void InstructionSelector::VisitInt32PairSub(Node* node) { UNIMPLEMENTED(); }
  67 --- qtwebengine-everywhere-src-5.11.1.clean/src/3rdparty/chromium/build/build_config.h~ 2018-06-15 09:47:20.000000000 +0200
  68 +++ qtwebengine-everywhere-src-5.11.1.clean/src/3rdparty/chromium/build/build_config.h  2018-08-14 09:23:40.756276384 +0200
  69 @@ -106,7 +106,11 @@
  70  #if defined(_M_X64) || defined(__x86_64__)
  71  #define ARCH_CPU_X86_FAMILY 1
  72  #define ARCH_CPU_X86_64 1
  73 +#ifdef __ILP32__
  74 +#define ARCH_CPU_32_BITS 1
  75 +#else
  76  #define ARCH_CPU_64_BITS 1
  77 +#endif
  78  #define ARCH_CPU_LITTLE_ENDIAN 1
  79  #elif defined(_M_IX86) || defined(__i386__)
  80  #define ARCH_CPU_X86_FAMILY 1
  81 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/base/allocator/partition_allocator/address_space_randomization.cc~  2018-06-15 09:47:20.000000000 +0200
  82 +++ qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/base/allocator/partition_allocator/address_space_randomization.cc   2018-08-14 09:27:44.678865071 +0200
  83 @@ -77,7 +77,7 @@
  84  void* GetRandomPageBase() {
  85    uintptr_t random = static_cast<uintptr_t>(ranval(s_ranctx.Pointer()));
  86
  87 -#if defined(ARCH_CPU_64_BITS)
  88 +#if defined(ARCH_CPU_64_BITS) && !defined(__ILP32__)
  89    random <<= 32ULL;
  90    random |= static_cast<uintptr_t>(ranval(s_ranctx.Pointer()));
  91
  92 --- qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/base/debug/stack_trace_posix.cc~    2018-06-15 09:47:20.000000000 +0200
  93 +++ qtwebengine-everywhere-src-5.11.1/src/3rdparty/chromium/base/debug/stack_trace_posix.cc     2018-08-14 09:46:02.035829506 +0200
  94 @@ -340,7 +340,7 @@
  95      const char* label;
  96      greg_t value;
  97    } registers[] = {
  98 -#if ARCH_CPU_32_BITS
  99 +#if ARCH_CPU_32_BITS && !defined(__ILP32__)
 100      { "  gs: ", context->uc_mcontext.gregs[REG_GS] },
 101      { "  fs: ", context->uc_mcontext.gregs[REG_FS] },
 102      { "  es: ", context->uc_mcontext.gregs[REG_ES] },
 103 @@ -360,7 +360,7 @@
 104      { " efl: ", context->uc_mcontext.gregs[REG_EFL] },
 105      { " usp: ", context->uc_mcontext.gregs[REG_UESP] },
 106      { "  ss: ", context->uc_mcontext.gregs[REG_SS] },
 107 -#elif ARCH_CPU_64_BITS
 108 +#elif ARCH_CPU_64_BITS || defined(__ILP32__)
 109      { "  r8: ", context->uc_mcontext.gregs[REG_R8] },
 110      { "  r9: ", context->uc_mcontext.gregs[REG_R9] },
 111      { " r10: ", context->uc_mcontext.gregs[REG_R10] },
 112 @@ -387,9 +387,9 @@
 113  #endif  // ARCH_CPU_32_BITS
 114    };
 115
 116 -#if ARCH_CPU_32_BITS
 117 +#if ARCH_CPU_32_BITS && !defined(__ILP32__)
 118    const int kRegisterPadding = 8;
 119 -#elif ARCH_CPU_64_BITS
 120 +#elif ARCH_CPU_64_BITS || defined(__ILP32__)
 121    const int kRegisterPadding = 16;
 122  #endif
 123