- qemu patches for 0.9.1 (needed for coreboot aka linuxbios)

Changed files:
    qemu-isa-bios-ram.patch -> 1.1.2.1
    qemu-piix-ram-size.patch -> 1.1.2.1

diff --git a/qemu-isa-bios-ram.patch b/qemu-isa-bios-ram.patch
new file mode 100644 (file)
index 0000000..589084f
--- /dev/null
+++ b/qemu-isa-bios-ram.patch
@@ -0,0 +1,24 @@
+Index: qemu-snapshot-2007-02-09_05/hw/pc.c
+===================================================================
+--- qemu-snapshot-2007-02-09_05.orig/hw/pc.c
++++ qemu-snapshot-2007-02-09_05/hw/pc.c
+@@ -522,15 +522,13 @@ static void pc_init1(int ram_size, int v
+     cpu_register_physical_memory(0xc0000, 0x10000, 
+                                  vga_bios_offset | IO_MEM_ROM);
+ 
+-    /* map the last 128KB of the BIOS in ISA space */
++    /* copy the last 128KB of the BIOS to ISA space */
+     isa_bios_size = bios_size;
+     if (isa_bios_size > (128 * 1024))
+         isa_bios_size = 128 * 1024;
+-    cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
+-                                 IO_MEM_UNASSIGNED);
+-    cpu_register_physical_memory(0x100000 - isa_bios_size,
+-                                 isa_bios_size,
+-                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
++    memcpy(phys_ram_base + 0x100000 - isa_bios_size,
++           phys_ram_base + bios_offset + bios_size - isa_bios_size,
++           isa_bios_size);
+ 
+     {
+         ram_addr_t option_rom_offset;

diff --git a/qemu-piix-ram-size.patch b/qemu-piix-ram-size.patch
new file mode 100644 (file)
index 0000000..220b62b
--- /dev/null
+++ b/qemu-piix-ram-size.patch
@@ -0,0 +1,50 @@
+Index: qemu-snapshot-2007-02-09_05/hw/piix_pci.c
+===================================================================
+--- qemu-snapshot-2007-02-09_05.orig/hw/piix_pci.c
++++ qemu-snapshot-2007-02-09_05/hw/piix_pci.c
+@@ -155,7 +155,7 @@ static int i440fx_load(QEMUFile* f, void
+     return 0;
+ }
+ 
+-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
++PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic, int ram_size)
+ {
+     PCIBus *b;
+     PCIDevice *d;
+@@ -186,6 +186,10 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_
+     d->config[0x0a] = 0x00; // class_sub = host2pci
+     d->config[0x0b] = 0x06; // class_base = PCI_bridge
+     d->config[0x0e] = 0x00; // header_type
++    ram_size = ram_size / 8 / 1024 / 1024;
++    if (ram_size > 255)
++        ram_size = 255;
++    d->config[0x57] = ram_size;
+ 
+     d->config[0x72] = 0x02; /* SMRAM */
+ 
+Index: qemu-snapshot-2007-02-09_05/hw/pc.c
+===================================================================
+--- qemu-snapshot-2007-02-09_05.orig/hw/pc.c
++++ qemu-snapshot-2007-02-09_05/hw/pc.c
+@@ -623,7 +623,7 @@ static void pc_init1(int ram_size, int v
+     }
+ 
+     if (pci_enabled) {
+-        pci_bus = i440fx_init(&i440fx_state, i8259);
++        pci_bus = i440fx_init(&i440fx_state, i8259, ram_size);
+         piix3_devfn = piix3_init(pci_bus, -1);
+     } else {
+         pci_bus = NULL;
+Index: qemu-snapshot-2007-02-09_05/hw/pc.h
+===================================================================
+--- qemu-snapshot-2007-02-09_05.orig/hw/pc.h
++++ qemu-snapshot-2007-02-09_05/hw/pc.h
+@@ -841,7 +841,7 @@ PCIBus *pci_apb_init(target_ulong specia
+ PCIBus *pci_vpb_init(void *pic, int irq, int realview);
+ 
+ /* piix_pci.c */
+-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
++PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic, int ram_size);
+ void i440fx_set_smm(PCIDevice *d, int val);
+ int piix3_init(PCIBus *bus, int devfn);
+ void i440fx_init_memory_mappings(PCIDevice *d);