tahoe9xx-2.6.2.patch

   1 --- linux/drivers/net/wan/Makefile      2003-03-06 14:56:13.000000000 +0100
   2 +++ linux/drivers/net/wan/Makefile      2003-03-30 22:37:04.000000000 +0200
   3 @@ -66,6 +66,7 @@
   4  endif
   5  obj-$(CONFIG_N2)               += n2.o
   6  obj-$(CONFIG_C101)             += c101.o
   7 +obj-$(CONFIG_TAHOE9XX)         += tahoe9xx.o
   8  obj-$(CONFIG_WANXL)            += wanxl.o
   9  obj-$(CONFIG_PCI200SYN)                += pci200syn.o
  10
  11 --- linux/drivers/net/wan/tahoe9xx.c    2003-04-07 14:18:45.000000000 +0200
  12 +++ linux/drivers/net/wan/tahoe9xx.c    2003-04-07 13:47:45.000000000 +0200
  13 @@ -0,0 +1,805 @@
  14 +/*
  15 + * Tahoe 9xx synchronous serial card driver for Linux
  16 + *
  17 + * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl>
  18 + * Copyright (C) 2003 Piotr Kaczmarzyk <piotr@tahoe.pl>
  19 + *
  20 + * This program is free software; you can redistribute it and/or modify it
  21 + * under the terms of version 2 of the GNU General Public License
  22 + * as published by the Free Software Foundation.
  23 + *
  24 + * For information see http://hq.pm.waw.pl/hdlc/
  25 + *
  26 + * Sources of information:
  27 + *    Hitachi HD64570 SCA User's Manual
  28 + *    PLX Technology Inc. PCI9052 Data Book
  29 + *    Dallas Semiconductor DS21554 Datasheet
  30 + */
  31 +
  32 +#include <linux/config.h>
  33 +#include <linux/module.h>
  34 +#include <linux/kernel.h>
  35 +#include <linux/slab.h>
  36 +#include <linux/sched.h>
  37 +#include <linux/types.h>
  38 +#include <linux/fcntl.h>
  39 +#include <linux/in.h>
  40 +#include <linux/string.h>
  41 +#include <linux/errno.h>
  42 +#include <linux/init.h>
  43 +#include <linux/ioport.h>
  44 +#include <linux/netdevice.h>
  45 +#include <linux/hdlc.h>
  46 +#include <linux/pci.h>
  47 +#include <asm/delay.h>
  48 +#include <asm/io.h>
  49 +
  50 +#include "hd64570.h"
  51 +
  52 +static const char* version = "Tahoe 9xx driver version: 1.14t";
  53 +static const char* devname = "TAHOE9XX";
  54 +
  55 +#define        TAHOE9XX_PLX_SIZE       0x80    /* PLX control window size (128b) */
  56 +#define        TAHOE9XX_SCA_SIZE       0x100   /* SCA window size (256b) */
  57 +#define ALL_PAGES_ALWAYS_MAPPED
  58 +#define NEED_DETECT_RAM
  59 +#define NEED_SCA_MSCI_INTR
  60 +#define MAX_TX_BUFFERS         10
  61 +
  62 +#define CLOCK_BASE 9216000
  63 +
  64 +#define G703_AMI               0
  65 +#define G703_HDB3              1
  66 +
  67 +#define DEFAULT_LICR    0x80
  68 +
  69 +#define PCI_VENDOR_ID_TAHOE            0x8246
  70 +#define PCI_DEVICE_ID_TAHOE931 0x0931
  71 +#define PCI_DEVICE_ID_TAHOE932 0x0932
  72 +#define PCI_DEVICE_ID_TAHOE971 0x0971
  73 +#define PCI_DEVICE_ID_TAHOE972 0x0972
  74 +
  75 +/*
  76 + *      PLX PCI9052 local configuration and shared runtime registers.
  77 + *     This structure can be used to access 9052 registers (memory mapped).
  78 + */
  79 +typedef struct {
  80 +       u32 loc_addr_range[4];  /* 00-0Ch : Local Address Ranges */
  81 +       u32 loc_rom_range;      /* 10h : Local ROM Range */
  82 +       u32 loc_addr_base[4];   /* 14-20h : Local Address Base Addrs */
  83 +       u32 loc_rom_base;       /* 24h : Local ROM Base */
  84 +       u32 loc_bus_descr[4];   /* 28-34h : Local Bus Descriptors */
  85 +       u32 rom_bus_descr;      /* 38h : ROM Bus Descriptor */
  86 +       u32 cs_base[4];         /* 3C-48h : Chip Select Base Addrs */
  87 +       u32 intr_ctrl_stat;     /* 4Ch : Interrupt Control/Status */
  88 +       u32 init_ctrl;          /* 50h : EEPROM ctrl, Init Ctrl, etc */
  89 +}plx9052;
  90 +
  91 +
  92 +
  93 +
  94 +
  95 +typedef struct ds21554_s {
  96 +       u8      vcr1;           /* Counter:     Violation Error */
  97 +       u8      vcr2;
  98 +       u8      crccr1;         /* Counter:     CRC4 Error */
  99 +       u8      crccr2;
 100 +       u8      ebcr1;          /* Counter:     E-bit Error (FEBE) */
 101 +       u8      ebcr2;
 102 +       u8      sr1;            /* Status:      Status Register 1 */
 103 +       u8      sr2;            /* Status:      Status Register 2 */
 104 +       u8      rir;            /* Status:      Receive Information */
 105 +       u8      reserved1[6];
 106 +       u8      idr;            /* Misc:        Device Indentification */
 107 +       u8      rcr1;           /* Control:     Receive Control 1 */
 108 +       u8      rcr2;           /* Control:     Receive Control 2 */
 109 +       u8      tcr1;           /* Control:     Transmit Control 1 */
 110 +       u8      tcr2;           /* Control:     Transmit Control 2 */
 111 +       u8      ccr1;           /* Control:     Common Control 1 */
 112 +       u8      test1;
 113 +       u8      imr1;           /* Interrupt Mask 1 */
 114 +       u8      imr2;           /* Interrupt Mask 2 */
 115 +       u8      licr;           /* Control: Line interface */
 116 +       u8      test2;
 117 +       u8      ccr2;           /* Control: Common Control 2 */
 118 +       u8      ccr3;           /* Control: Common Control 3 */
 119 +       u8      tsacr;          /* Control: Transmit Sa bit */
 120 +       u8      ccr6;           /* Control: Common Control 6 */
 121 +       u8      ssr;            /* Status:      Synchronizer Status */
 122 +       u8      rnaf;           /* Receive non-align frame */
 123 +       u8      taf;            /* Transmit align frame */
 124 +       u8      tnaf;           /* Transmit non-align frame */
 125 +       u8      tcbr1;          /* Transmit channel blocking */
 126 +       u8      tcbr2;
 127 +       u8      tcbr3;
 128 +       u8      tcbr4;
 129 +       u8      tir1;           /* Transmit idle */
 130 +       u8      tir2;
 131 +       u8      tir3;
 132 +       u8      tir4;
 133 +       u8      tidr;           /* Transmit idle definition */
 134 +       u8      rcbr1;          /* Receive channel blocking */
 135 +       u8      rcbr2;
 136 +       u8      rcbr3;
 137 +       u8      rcbr4;
 138 +       u8      raf;            /* Receive align frame */
 139 +       u8      rs1;            /* Receive signalling */
 140 +       u8      rs2;
 141 +       u8      rs3;
 142 +       u8      rs4;
 143 +       u8      rs5;
 144 +       u8      rs6;
 145 +       u8      rs7;
 146 +       u8      rs8;
 147 +       u8      rs9;
 148 +       u8      rs10;
 149 +       u8      rs11;
 150 +       u8      rs12;
 151 +       u8      rs13;
 152 +       u8      rs14;
 153 +       u8      rs15;
 154 +       u8      rs16;
 155 +       u8      ts1;            /* Transmit signaling */
 156 +       u8      ts2;
 157 +       u8      ts3;
 158 +       u8      ts4;
 159 +       u8      ts5;
 160 +       u8      ts6;
 161 +       u8      ts7;
 162 +       u8      ts8;
 163 +       u8      ts9;
 164 +       u8      ts10;
 165 +       u8      ts11;
 166 +       u8      ts12;
 167 +       u8      ts13;
 168 +       u8      ts14;
 169 +       u8      ts15;
 170 +       u8      ts16;
 171 +       u8      tsiaf;          /* Transmit Si Bits Align Frame */
 172 +       u8      tsinaf;         /* Transmit Si Bits Non-align Frame */
 173 +       u8      tra;            /* Transmit Remote Alarm Bits */
 174 +       u8      tsa4;           /* Transmit Sa Bits */
 175 +       u8      tsa5;
 176 +       u8      tsa6;
 177 +       u8      tsa7;
 178 +       u8      tsa8;
 179 +       u8      rsiaf;          /* Receive Si Bits Align Frame */
 180 +       u8      rsinaf;         /* Receive Si Bits Non-Align Frame */
 181 +       u8      rra;            /* Receive Remote Alarm Bits */
 182 +       u8      rsa4;           /* Receive Sa Bits */
 183 +       u8      rsa5;
 184 +       u8      rsa6;
 185 +       u8      rsa7;
 186 +       u8      rsa8;
 187 +       u8      tc1;            /* Transmit channel */
 188 +       u8      tc2;
 189 +       u8      tc3;
 190 +       u8      tc4;
 191 +       u8      tc5;
 192 +       u8      tc6;
 193 +       u8      tc7;
 194 +       u8      tc8;
 195 +       u8      tc9;
 196 +       u8      tc10;
 197 +       u8      tc11;
 198 +       u8      tc12;
 199 +       u8      tc13;
 200 +       u8      tc14;
 201 +       u8      tc15;
 202 +       u8      tc16;
 203 +       u8      tc17;
 204 +       u8      tc18;
 205 +       u8      tc19;
 206 +       u8      tc20;
 207 +       u8      tc21;
 208 +       u8      tc22;
 209 +       u8      tc23;
 210 +       u8      tc24;
 211 +       u8      tc25;
 212 +       u8      tc26;
 213 +       u8      tc27;
 214 +       u8      tc28;
 215 +       u8      tc29;
 216 +       u8      tc30;
 217 +       u8      tc31;
 218 +       u8      tc32;
 219 +       u8      rc1;            /* Receive channel */
 220 +       u8      rc2;
 221 +       u8      rc3;
 222 +       u8      rc4;
 223 +       u8      rc5;
 224 +       u8      rc6;
 225 +       u8      rc7;
 226 +       u8      rc8;
 227 +       u8      rc9;
 228 +       u8      rc10;
 229 +       u8      rc11;
 230 +       u8      rc12;
 231 +       u8      rc13;
 232 +       u8      rc14;
 233 +       u8      rc15;
 234 +       u8      rc16;
 235 +       u8      rc17;
 236 +       u8      rc18;
 237 +       u8      rc19;
 238 +       u8      rc20;
 239 +       u8      rc21;
 240 +       u8      rc22;
 241 +       u8      rc23;
 242 +       u8      rc24;
 243 +       u8      rc25;
 244 +       u8      rc26;
 245 +       u8      rc27;
 246 +       u8      rc28;
 247 +       u8      rc29;
 248 +       u8      rc30;
 249 +       u8      rc31;
 250 +       u8      rc32;
 251 +       u8      tcc1;           /* Transmit channel control */
 252 +       u8      tcc2;
 253 +       u8      tcc3;
 254 +       u8      tcc4;
 255 +       u8      rcc1;           /* Receive channel control */
 256 +       u8      rcc2;
 257 +       u8      rcc3;
 258 +       u8      rcc4;
 259 +       u8      ccr4;           /* Control:     Common Control 4 */
 260 +       u8      tds0m;          /* Transmit DS0 Monitor */
 261 +       u8      ccr5;           /* Control:     Common Control 5 */
 262 +       u8      rds0m;          /* Receive DS0 Monitor */
 263 +       u8      test3;
 264 +       u8      reserved2[3];
 265 +       u8      hcr;            /* HDLC Control */
 266 +       u8      hsr;            /* HDLC Status */
 267 +       u8      himr;           /* HDLC Interrupt Mask */
 268 +       u8      rhir;           /* Receive HDLC Information */
 269 +       u8      rhfr;           /* Receive HDLC FIFO */
 270 +       u8      ibo;            /* Interleave Bus Operation */
 271 +       u8      thir;           /* Transmit HDLC Information */
 272 +       u8      thfr;           /* Transmit HDLC FIFO */
 273 +       u8      rdc1;           /* Receive HDLC DS0 Control 1 */
 274 +       u8      rdc2;           /* Receive HDLC DS0 Control 2 */
 275 +       u8      tdc1;           /* Transmit HDLC DS0 Control 1 */
 276 +       u8      tdc2;           /* Transmit HDLC DS0 Control 2 */
 277 +       u8      reserved3[4];
 278 +} ds21554_t;
 279 +
 280 +typedef struct port_s {
 281 +       hdlc_device hdlc;       /* HDLC device struct - must be first */
 282 +       struct card_s *card;
 283 +       spinlock_t lock;        /* TX lock */
 284 +       te1_settings settings;
 285 +       int rxpart;             /* partial frame received, next frame invalid*/
 286 +       unsigned short encoding;
 287 +       unsigned short parity;
 288 +       u16 rxin;               /* rx ring buffer 'in' pointer */
 289 +       u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
 290 +       u16 txlast;
 291 +       u8 rxs, txs, tmc;       /* SCA registers */
 292 +       u8 phy_node;            /* physical port # - 0 or 1 */
 293 +       u32 dsphys;                     /* DS21544 memory base (physical) */
 294 +       ds21554_t* dsbase;      /* DS21544 memory base (virtual) */
 295 +       u8      g703_on;                /* Enable/disable G.703 transceiver */
 296 +       u8      g703_coding;    /* G.703 line coding */
 297 +       u8      g703_idlecode;  /* G.703 idle timeslots contents */
 298 +}port_t;
 299 +
 300 +typedef struct card_s {
 301 +       u32 ramphys;            /* buffer memory base (physical) */
 302 +       u8* rambase;            /* buffer memory base (virtual) */
 303 +       u32 ramsize;            /* buffer memory size */
 304 +       u32 scaphys;            /* SCA memory base (physical) */
 305 +       u8* scabase;            /* SCA memory base (virtual) */
 306 +       u32 plxphys;            /* PLX registers memory base (physical) */
 307 +       plx9052* plxbase;       /* PLX registers memory base (virtual) */
 308 +       u16 rx_ring_buffers;    /* number of buffers in a ring */
 309 +       u16 tx_ring_buffers;
 310 +       u16 buff_offset;        /* offset of first buffer of first channel */
 311 +       u8 irq;                         /* interrupt request level */
 312 +       u8 no_ports;            /* number of ports */
 313 +       char dev_name[10];      /* device name */
 314 +       port_t ports[2];
 315 +}card_t;
 316 +
 317 +#define sca_in(reg, card)           readb(card->scabase + (reg))
 318 +#define sca_out(value, reg, card)    writeb(value, card->scabase + (reg))
 319 +#define sca_inw(reg, card)          readw(card->scabase + (reg))
 320 +#define sca_outw(value, reg, card)   writew(value, card->scabase + (reg))
 321 +#define sca_inl(reg, card)          readl(card->scabase + (reg))
 322 +#define sca_outl(value, reg, card)   writel(value, card->scabase + (reg))
 323 +
 324 +#define port_to_card(port)          (port->card)
 325 +#define log_node(port)              (port->phy_node)
 326 +#define phy_node(port)              (port->phy_node)
 327 +#define winbase(card)               (card->rambase)
 328 +#define get_port(card, port)        (&card->ports[port])
 329 +#define sca_flush(card)                     (sca_in(IER0, card));
 330 +
 331 +static inline void new_memcpy_toio(char *dest, char *src, int length)
 332 +{
 333 +       int len;
 334 +
 335 +       do {
 336 +               len = length > 64 ? 64 : length; /* 32 */
 337 +               memcpy_toio(dest, src, len);
 338 +               dest += len;
 339 +               src += len;
 340 +               length -= len;
 341 +               readb(dest);
 342 +       } while (len);
 343 +}
 344 +
 345 +#undef memcpy_toio
 346 +#define memcpy_toio new_memcpy_toio
 347 +
 348 +#include "hd6457x.c"
 349 +
 350 +void init_ds21554(port_t *port);
 351 +
 352 +static void t9xx_set_iface(port_t *port)
 353 +{
 354 +       card_t *card = port->card;
 355 +       u8 msci = get_msci(port);
 356 +       u8 rxs = port->rxs & CLK_BRG_MASK;
 357 +       u8 txs = port->txs & CLK_BRG_MASK;
 358 +
 359 +       if (port->dsbase) {
 360 +               init_ds21554(port);
 361 +       }
 362 +
 363 +       rxs |= CLK_LINE_RX; /* RXC input */
 364 +       txs |= CLK_LINE_TX; /* TXC input */
 365 +
 366 +       port->rxs = rxs;
 367 +       port->txs = txs;
 368 +       sca_out(rxs, msci + RXS, card);
 369 +       sca_out(txs, msci + TXS, card);
 370 +       sca_set_port(port);
 371 +}
 372 +
 373 +
 374 +
 375 +static int t9xx_open(struct net_device *dev)
 376 +{
 377 +       hdlc_device *hdlc = dev_to_hdlc(dev);
 378 +       port_t *port = hdlc_to_port(hdlc);
 379 +       int     result;
 380 +
 381 +       if (!try_module_get(THIS_MODULE))
 382 +               return -EFAULT; /* rmmod in progress */
 383 +
 384 +       result = hdlc_open(hdlc);
 385 +
 386 +       if (result) {
 387 +               module_put(THIS_MODULE);
 388 +               return result;
 389 +       }
 390 +
 391 +       sca_open(hdlc);
 392 +       t9xx_set_iface(port);
 393 +       sca_flush(port_to_card(port));
 394 +       return 0;
 395 +}
 396 +
 397 +
 398 +
 399 +static int t9xx_close(struct net_device *dev)
 400 +{
 401 +       hdlc_device *hdlc = dev_to_hdlc(dev);
 402 +
 403 +       sca_close(hdlc);
 404 +       sca_flush(port_to_card(dev_to_port(dev)));
 405 +       hdlc_close(hdlc);
 406 +       module_put(THIS_MODULE);
 407 +       return 0;
 408 +}
 409 +
 410 +
 411 +
 412 +static int t9xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 413 +{
 414 +       const size_t size = sizeof(te1_settings);
 415 +       te1_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.te1;
 416 +       hdlc_device *hdlc = dev_to_hdlc(dev);
 417 +       port_t *port = hdlc_to_port(hdlc);
 418 +
 419 +#ifdef CONFIG_HDLC_DEBUG_RINGS
 420 +       if (cmd == SIOCDEVPRIVATE) {
 421 +               sca_dump_rings(hdlc);
 422 +               return 0;
 423 +       }
 424 +#endif
 425 +       if (cmd != SIOCWANDEV)
 426 +               return hdlc_ioctl(dev, ifr, cmd);
 427 +
 428 +       switch(ifr->ifr_settings.type) {
 429 +       case IF_GET_IFACE:
 430 +               if (port->dsbase)
 431 +                       ifr->ifr_settings.type = IF_IFACE_E1;
 432 +               else
 433 +                       ifr->ifr_settings.type = IF_IFACE_V35;
 434 +               if (ifr->ifr_settings.size < size) {
 435 +                       ifr->ifr_settings.size = size; /* data size wanted */
 436 +                       return -ENOBUFS;
 437 +               }
 438 +               if (copy_to_user(line, &port->settings, size))
 439 +                       return -EFAULT;
 440 +               return 0;
 441 +
 442 +       case IF_IFACE_E1:
 443 +       case IF_IFACE_V35:
 444 +               if (!capable(CAP_NET_ADMIN))
 445 +                       return -EPERM;
 446 +
 447 +               if (copy_from_user(&new_line, line, size))
 448 +                       return -EFAULT;
 449 +
 450 +               if (new_line.clock_type != CLOCK_EXT)
 451 +                       return -EINVAL; /* No such clock setting */
 452 +
 453 +               if (new_line.loopback > 3)
 454 +                       return -EINVAL;
 455 +
 456 +               memcpy(&port->settings, &new_line, size); /* Update settings */
 457 +               t9xx_set_iface(port);
 458 +               sca_flush(port_to_card(port));
 459 +               return 0;
 460 +
 461 +       default:
 462 +               return hdlc_ioctl(dev, ifr, cmd);
 463 +       }
 464 +}
 465 +
 466 +
 467 +
 468 +static void t9xx_pci_remove_one(struct pci_dev *pdev)
 469 +{
 470 +       int i, ports;
 471 +        card_t *card = pci_get_drvdata(pdev);
 472 +
 473 +       if ((pdev->subsystem_device == PCI_DEVICE_ID_TAHOE932) ||
 474 +           (pdev->subsystem_device == PCI_DEVICE_ID_TAHOE972))
 475 +               ports = 2;
 476 +       else
 477 +               ports = 1;
 478 +       for(i = 0; i < ports; i++)
 479 +               if (card->ports[i].card)
 480 +                       unregister_hdlc_device(&card->ports[i].hdlc);
 481 +
 482 +       if (card->irq)
 483 +               free_irq(card->irq, card);
 484 +       iounmap(card->rambase);
 485 +       iounmap(card->scabase);
 486 +       iounmap(card->plxbase);
 487 +        pci_release_regions(pdev);
 488 +       kfree(card);
 489 +}
 490 +
 491 +static void ds21554_update_licr(port_t *port)
 492 +{
 493 +       port->dsbase->licr = DEFAULT_LICR | (port->settings.egl << 4) | (port->g703_on == 0);
 494 +}
 495 +
 496 +static void ds21554_update_registers(port_t *port)
 497 +{
 498 +       ds21554_t       *ds = port->dsbase;
 499 +
 500 +       if (port->settings.slot_map == 0xffffffff) {
 501 +               /* Unframed */
 502 +               ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2);
 503 +               ds->tcr1 = 0x40;
 504 +               ds->tcr2 = 0x00;
 505 +               ds->ccr2 = 0x80; //84
 506 +               ds->tir1 = 0; ds->tir2 = 0; ds->tir3 = 0; ds->tir4 = 0;
 507 +               ds->tcc1 = 0; ds->tcc2 = 0; ds->tcc3 = 0; ds->tcc4 = 0;
 508 +               ds->rcc1 = 0; ds->rcc2 = 0; ds->rcc3 = 0; ds->rcc4 = 0;
 509 +               ds->rcbr1 = 0xff; ds->rcbr2 = 0xff;
 510 +               ds->rcbr3 = 0xff; ds->rcbr4 = 0xff;
 511 +               ds->tcbr1 = 0xff; ds->tcbr2 = 0xff;
 512 +               ds->tcbr3 = 0xff; ds->tcbr4 = 0xff;
 513 +               ds->tsacr = 0x00;
 514 +               ds->tdc1 = 0x00;
 515 +
 516 +               ds->rcr2 = 0x04;
 517 +               ds->ccr3 = 0x02;
 518 +
 519 +               ds->ccr6 = 0x03;        /* elastic buffers reset */
 520 +               udelay(1000);
 521 +               ds->ccr6 = 0x00;        /* elastic buffers reset */
 522 +
 523 +               ds->ccr5 = 0x60;        /* elastic buffers align */
 524 +               udelay(1000);
 525 +               ds->ccr5 = 0x00;
 526 +       } else {
 527 +               ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2)
 528 +                               | (port->settings.crc4 << 4) | (port->settings.crc4);
 529 +               ds->tcr1 = 0x00;
 530 +               ds->ccr2 = 0x94;        /* Automatic alarm generation */
 531 +
 532 +               /* Receive channels */
 533 +               ds->rcbr1 = port->settings.slot_map & 0xff;
 534 +               ds->rcbr2 = (port->settings.slot_map >> 8) & 0xff;
 535 +               ds->rcbr3 = (port->settings.slot_map >> 16) & 0xff;
 536 +               ds->rcbr4 = (port->settings.slot_map >> 24) & 0xff;
 537 +
 538 +               /* Transmit channels */
 539 +               ds->tcbr1 = port->settings.slot_map & 0xff;
 540 +               ds->tcbr2 = (port->settings.slot_map >> 8) & 0xff;
 541 +               ds->tcbr3 = (port->settings.slot_map >> 16) & 0xff;
 542 +               ds->tcbr4 = (port->settings.slot_map >> 24) & 0xff;
 543 +
 544 +               /* Transmit idle */
 545 +               /* (remaining timeslots are filled with idle code) */
 546 +               ds->tir1 = ~port->settings.slot_map & 0xfe;     /* Slot 0 is never idle */
 547 +               ds->tir2 = (~port->settings.slot_map >> 8) & 0xff;
 548 +               ds->tir3 = (~port->settings.slot_map >> 16) & 0xff;
 549 +               ds->tir4 = (~port->settings.slot_map >> 24) & 0xff;
 550 +               ds->rcr2 = 0x06;        /* RSYSCLK = 2048, rx elastic store enabled */
 551 +               ds->ccr3 = 0x82;        /* TSYSCLK = 2048, tx elastic store enabled */
 552 +
 553 +               ds->ccr6 = 0x07;        /* elastic buffers reset */
 554 +               udelay(1000);
 555 +               ds->ccr6 = 0x04;        /* elastic buffers reset */
 556 +
 557 +               ds->ccr5 = 0x60;        /* elastic buffers align */
 558 +               udelay(1000);
 559 +               ds->ccr5 = 0x00;
 560 +       }
 561 +}
 562 +
 563 +void init_ds21554(port_t *port)
 564 +{
 565 +       ds21554_t       *ds = port->dsbase;
 566 +
 567 +       ds->ccr2 = 0x04;
 568 +       udelay(1000);
 569 +       ds->ccr5 = 0x80;        /* Line Interface Reset */
 570 +       udelay(1000);
 571 +
 572 +       ds->ccr5 = 0xe0;        /* Elastic Buffers Reset */
 573 +       udelay(1000);
 574 +       ds->ccr5 = 0x00;
 575 +       ds->ccr6 = 0x04;        /* TCLK from RCLK */
 576 +       ds->tcr2 = 0x00;
 577 +       ds21554_update_licr(port);
 578 +
 579 +       /* Setup HDB3, CRC4, CAS/CCS, G.802 */
 580 +       ds21554_update_registers(port);
 581 +
 582 +       ds->ccr2 = 0x94;        /* Automatic alarm generation */
 583 +
 584 +       ds->taf = 0x1b;
 585 +       ds->tnaf = 0x40;
 586 +
 587 +       ds21554_update_registers(port);
 588 +
 589 +       ds->tidr = port->g703_idlecode;
 590 +
 591 +//     ds->ccr4 |= 0x40;
 592 +}
 593 +
 594 +
 595 +static int __devinit t9xx_pci_init_one(struct pci_dev *pdev,
 596 +                                        const struct pci_device_id *ent)
 597 +{
 598 +       card_t *card;
 599 +       u8 rev_id, tahoe97x = 0;
 600 +       u32 *p;
 601 +       int i;
 602 +
 603 +#ifndef MODULE
 604 +        static int printed_version;
 605 +        if (!printed_version++)
 606 +                printk(KERN_INFO "%s\n", version);
 607 +#endif
 608 +
 609 +       i = pci_enable_device(pdev);
 610 +       if (i)
 611 +               return i;
 612 +
 613 +        i = pci_request_regions(pdev, "Tahoe9xx");
 614 +       if (i)
 615 +                return i;
 616 +
 617 +       card = kmalloc(sizeof(card_t), GFP_KERNEL);
 618 +       if (card == NULL) {
 619 +               printk(KERN_ERR "%s: unable to allocate memory\n", card->dev_name);
 620 +               return -ENOBUFS;
 621 +       }
 622 +       memset(card, 0, sizeof(card_t));
 623 +       pci_set_drvdata(pdev, card);
 624 +
 625 +       sprintf(card->dev_name, "Tahoe");
 626 +       switch (pdev->subsystem_device) {
 627 +               case PCI_DEVICE_ID_TAHOE931:
 628 +                       strcat(card->dev_name, "931");
 629 +                       card->no_ports = 1;
 630 +                       break;
 631 +               case PCI_DEVICE_ID_TAHOE932:
 632 +                       strcat(card->dev_name, "932");
 633 +                       card->no_ports = 2;
 634 +                       break;
 635 +               case PCI_DEVICE_ID_TAHOE971:
 636 +                       strcat(card->dev_name, "971");
 637 +                       tahoe97x = 1;
 638 +                       card->no_ports = 1;
 639 +                       break;
 640 +               case PCI_DEVICE_ID_TAHOE972:
 641 +                       strcat(card->dev_name, "972");
 642 +                       tahoe97x = 1;
 643 +                       card->no_ports = 2;
 644 +                       break;
 645 +               default:
 646 +                       strcat(card->dev_name, "9xx");
 647 +                       card->no_ports = 0;
 648 +                       break;
 649 +       }
 650 +
 651 +       pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
 652 +       if (pci_resource_len(pdev, 0) != TAHOE9XX_PLX_SIZE ||
 653 +           pci_resource_len(pdev, 2) != TAHOE9XX_SCA_SIZE ||
 654 +           pci_resource_len(pdev, 3) < 16384) {
 655 +               printk(KERN_ERR "%s: invalid card EEPROM parameters\n", card->dev_name);
 656 +               kfree(card);
 657 +               return -EFAULT;
 658 +       }
 659 +
 660 +       card->plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
 661 +       card->plxbase = ioremap(card->plxphys, TAHOE9XX_PLX_SIZE);
 662 +
 663 +       card->scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
 664 +       card->scabase = ioremap(card->scaphys, TAHOE9XX_SCA_SIZE);
 665 +
 666 +       card->ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
 667 +       card->rambase = ioremap(card->ramphys, pci_resource_len(pdev,3));
 668 +
 669 +       if (tahoe97x) {
 670 +               for (i=0; i < card->no_ports; i++) {
 671 +                       card->ports[i].dsphys = pci_resource_start(pdev,4+i) & PCI_BASE_ADDRESS_MEM_MASK;
 672 +                       card->ports[i].dsbase = (ds21554_t *)ioremap(card->ports[i].dsphys, pci_resource_len(pdev,4+i));
 673 +               }
 674 +       } else {
 675 +               for (i=0; i < card->no_ports; i++)
 676 +                       card->ports[i].dsbase = (ds21554_t *)0;
 677 +       }
 678 +
 679 +       /* Reset PLX */
 680 +       p = &card->plxbase->init_ctrl;
 681 +       writel(readl(p) | 0x40000000, p);
 682 +       readl(p);               /* Flush the write - do not use sca_flush */
 683 +       udelay(1);
 684 +
 685 +       writel(readl(p) & ~0x40000000, p);
 686 +       readl(p);               /* Flush the write - do not use sca_flush */
 687 +       udelay(1);
 688 +
 689 +       card->ramsize = sca_detect_ram(card, card->rambase,
 690 +                                      pci_resource_len(pdev,3));
 691 +
 692 +       /* number of TX + RX buffers for one port - this is dual port card */
 693 +       i = card->ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
 694 +       card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
 695 +       card->rx_ring_buffers = i - card->tx_ring_buffers;
 696 +
 697 +       card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
 698 +                                                   card->rx_ring_buffers);
 699 +
 700 +       printk(KERN_INFO "%s: %u KB RAM at 0x%x, IRQ%u, using %u TX +"
 701 +              " %u RX packets rings\n", card->dev_name, card->ramsize / 1024,
 702 +              card->ramphys, pdev->irq,
 703 +              card->tx_ring_buffers, card->rx_ring_buffers);
 704 +       if (tahoe97x) {
 705 +               for (i=0; i < card->no_ports; i++) {
 706 +                       /* Make sure DS21554 is there */
 707 +                       card->ports[i].dsbase->idr = 0x00;
 708 +                       card->ports[i].dsbase->tc1 = 0xaa;
 709 +                       card->ports[i].dsbase->rc1 = 0x55;
 710 +                       if (((card->ports[i].dsbase->idr & 0xf0) == 0xa0) && (card->ports[i].dsbase->tc1 == 0xaa) && (card->ports[i].dsbase->rc1 == 0x55)) {
 711 +                               printk(KERN_INFO "%s: DS21554 (port %d) detected at 0x%x\n", card->dev_name, i, card->ports[i].dsphys);
 712 +                               /* Clear registers */
 713 +                               memset(card->ports[i].dsbase, 0, 256);
 714 +                               /* Default settings */
 715 +                               card->ports[i].g703_on = 1;
 716 +                               card->ports[i].settings.egl = 0;
 717 +                               card->ports[i].g703_coding = G703_HDB3;
 718 +                               card->ports[i].g703_idlecode = 0x54;
 719 +                               card->ports[i].settings.crc4 = 1;
 720 +                               /* Unframed */
 721 +                               card->ports[i].settings.slot_map = 0xffffffff;
 722 +                               init_ds21554(&card->ports[i]);
 723 +                       } else
 724 +                               printk(KERN_INFO "%s: DS21554 (port %d) test failed!\n", card->dev_name, i);
 725 +               }
 726 +       }
 727 +
 728 +       if (card->tx_ring_buffers < 1) {
 729 +               printk(KERN_ERR "%s: RAM test failed\n", card->dev_name);
 730 +               t9xx_pci_remove_one(pdev);
 731 +               return -EFAULT;
 732 +       }
 733 +
 734 +       /* Enable interrupts on the PCI bridge */
 735 +       p = &card->plxbase->intr_ctrl_stat;
 736 +       writew(readw(p) | 0x0040, p);
 737 +
 738 +       /* Allocate IRQ */
 739 +       if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) {
 740 +               printk(KERN_WARNING "%s: could not allocate IRQ%d.\n", card->dev_name,
 741 +                      pdev->irq);
 742 +               t9xx_pci_remove_one(pdev);
 743 +               return -EBUSY;
 744 +       }
 745 +       card->irq = pdev->irq;
 746 +
 747 +       sca_init(card, 0);
 748 +
 749 +       for(i = 0; i < card->no_ports; i++) {
 750 +               port_t *port = &card->ports[i];
 751 +               struct net_device *dev = hdlc_to_dev(&port->hdlc);
 752 +               port->phy_node = i;
 753 +
 754 +               spin_lock_init(&port->lock);
 755 +               dev->irq = card->irq;
 756 +               dev->mem_start = card->ramphys;
 757 +               dev->mem_end = card->ramphys + card->ramsize - 1;
 758 +               dev->tx_queue_len = 50;
 759 +               dev->do_ioctl = t9xx_ioctl;
 760 +               dev->open = t9xx_open;
 761 +               dev->stop = t9xx_close;
 762 +               port->hdlc.attach = sca_attach;
 763 +               port->hdlc.xmit = sca_xmit;
 764 +               port->settings.clock_type = CLOCK_EXT;
 765 +               if(register_hdlc_device(&port->hdlc)) {
 766 +                       printk(KERN_ERR "%s: unable to register hdlc "
 767 +                              "device\n", card->dev_name);
 768 +                       t9xx_pci_remove_one(pdev);
 769 +                       return -ENOBUFS;
 770 +               }
 771 +               port->card = card;
 772 +               sca_init_sync_port(port);       /* Set up SCA memory */
 773 +
 774 +               printk(KERN_INFO "%s: %s node %d\n",
 775 +                      hdlc_to_name(&port->hdlc), card->dev_name, port->phy_node);
 776 +       }
 777 +
 778 +       sca_flush(card);
 779 +       return 0;
 780 +}
 781 +
 782 +
 783 +
 784 +static struct pci_device_id t9xx_pci_tbl[] __devinitdata = {
 785 +        { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
 786 +          PCI_VENDOR_ID_TAHOE, PCI_ANY_ID,
 787 +          0, 0, 0 },
 788 +        { 0, }
 789 +};
 790 +
 791 +static struct pci_driver t9xx_pci_driver = {
 792 +        name:           "Tahoe9xx",
 793 +        id_table:       t9xx_pci_tbl,
 794 +        probe:          t9xx_pci_init_one,
 795 +        remove:         t9xx_pci_remove_one,
 796 +};
 797 +
 798 +static int __init t9xx_init_module(void)
 799 +{
 800 +#ifdef MODULE
 801 +        printk(KERN_INFO "%s\n", version);
 802 +#endif
 803 +       return pci_module_init(&t9xx_pci_driver);
 804 +}
 805 +
 806 +
 807 +
 808 +static void __exit t9xx_cleanup_module(void)
 809 +{
 810 +       pci_unregister_driver(&t9xx_pci_driver);
 811 +}
 812 +
 813 +MODULE_AUTHOR("Piotr Kaczmarzyk <piotr@tahoe.pl>");
 814 +MODULE_DESCRIPTION("Tahoe 9xx serial port driver");
 815 +MODULE_LICENSE("GPL v2");
 816 +MODULE_DEVICE_TABLE(pci, t9xx_pci_tbl);
 817 +module_init(t9xx_init_module);
 818 +module_exit(t9xx_cleanup_module);
 819 --- linux/drivers/net/wan/Kconfig       2003-03-06 14:56:13.000000000 +0100
 820 +++ linux/drivers/net/wan/Kconfig       2003-03-30 22:37:04.000000000 +0200
 821 @@ -437,6 +437,21 @@
 822           "alias hdlcX farsync" to /etc/modules.conf for each interface, where
 823           X is 0, 1, 2, ...
 824
 825 +config TAHOE9XX
 826 +       tristate "Tahoe 9xx support"
 827 +       depends on HDLC && PCI
 828 +       help
 829 +         This driver is for Tahoe 931/932/971/972 cards
 830 +         If you have such a card, say Y or M here and see
 831 +         <http://www.tahoe.pl/>
 832 +
 833 +         If you want to compile the driver as a module ( = code which can be
 834 +         inserted in and removed from the running kernel whenever you want),
 835 +         say M here and read <file:Documentation/modules.txt>.  The module
 836 +         will be called tahoe9xx.o.
 837 +
 838 +         If unsure, say N here.
 839 +
 840  config DLCI
 841         tristate "Frame relay DLCI support"
 842         depends on WAN
 843 --- linux/include/linux/hdlc/ioctl.h    1970-01-01 01:00:00.000000000 +0100
 844 +++ linux/include/linux/hdlc/ioctl.h    2003-07-31 14:46:58.000000000 +0200
 845 @@ -12,6 +12,8 @@
 846         unsigned int clock_type; /* internal, external, TX-internal etc. */
 847         unsigned short loopback;
 848         unsigned int slot_map;
 849 +       unsigned short crc4;
 850 +       unsigned short egl;
 851  } te1_settings;                  /* T1, E1 */
 852
 853  typedef struct {